Transient Synchronization Stability Analysis and Enhancement Control for Power Self-Synchronization Control Converters

Abstract

Conventional grid-forming control often destabilizes voltage source converters (VSCs) in stiff grids, and transient synchronization instability will occur in the grid fault condition. Therefore, power self-synchronization control (PSSC) is first introduced for enhancing the small-signal stability of grid-forming control in the case of a short circuit ratio ranging from 1 to infinity. Meanwhile, the transient synchronization instability for the grid-forming converter with PSSC in the grid fault condition is analyzed by the phase portrait, and a transient stability enhancement control (TSEC) scheme is combined with a PSSC-based VSC, which can efficiently eliminate the risk of losing synchronization in the arbitrary SCR. Finally, experimental results are provided to confirm the theoretical analysis.

1. Introduction

The voltage source converter (VSC) has been wildly used as an interface between renewable energy generation and the grid. The control techniques for VSCs can be categorized as grid-following control and grid-forming control [1,2].

The VSC usually applies grid-following control to synchronize with the grid via a phase-locked loop (PLL), and the VSC is controlled as a current source whose stable operation relies on a stiff grid condition [3]. However, with the large-scale integration of new energy into the grid by VSCs, the proportion of synchronous generators (SGs) in the system gradually decreases, which leads to a decline in grid strength and poses a great challenge to the stability of grid-following converters [4,5,6].

In order to ensure the stable operation of power systems with a high penetration of power electronics, VSCs are requested to participate in the formation of system voltage and frequency, which is achieved by grid-forming control [7,8]. By imitating the physical mechanism of synchronous generators, different grid-forming control schemes follow the same principle, i.e., (1) the inverter is regulated as a voltage source, and (2) the inverter achieves synchronization through the output power (or DC voltage) rather than by sampling the external AC grid voltage [2,9,10].

Grid-forming VSCs behave as voltage sources which can enhance the synchronization performance in weak grids. Refs. [11,12] indicate that a VSC with PSC is more robust in weak grids in accordance with the Nyquist criterion. Nevertheless, the grid-forming VSC is prone to small-signal instability in stiff grids. [13,14] discovered that the stability margin of a grid-forming VSC decreases with an increasing short circuit ratio (SCR), and the VSC has a higher risk of sub-synchronous oscillation. Ref. [15] has derived the impedance model of a droop-controlled VSC in the stationary frame, and according to the impedance-based stability analysis, it can be concluded that the stability problem of the droop-control VSC is more prominent in stiff grids. The small-signal model of the virtual synchronous generator (VSG)-based VSC is derived in reference [16]; it was revealed that a pair of complex conjugate poles, which are close to the imaginary axis in rigid grids, will result in instability. As indicated in [17], the interactive instability problem between the grid-forming converter and the AC grid is notably characterized by sub-synchronous oscillations.

Ref. [18] introduced a dual-mode control strategy incorporating grid impedance adaptation for droop-control VSCs. The inverter functions in current source mode under conditions of low grid impedance, transitioning to voltage source mode when the grid impedance increases. However, this scheme is complicated in application and it changes the major software structure on the grid-forming control. Ref. [19] proposed a universal controller that combines grid-following and grid-forming control strategies. This approach aims to enhance stability against different system conditions by using PSC as a guide to design a robust grid-following controller. When the SCR approaches 1, a low-frequency power resonance may be induced via an improperated coefficient in alternating voltage control [20]. Ref. [21] added an active susceptance loop, which enhances system damping without varying software structure and enables us to use a standard voltage-oriented vector current control. But the proposed control is more complicated and the condition in an extremely large SCR, which is not discussed.

In order to tackle the oscillation challenge faced by grid-forming converters in stiff grids, ref. [22] presents a new and practical control strategy known as power self-synchronization control (PSSC), where the modulating voltage is estimated as the output voltage of the VSC, rather than the Point of Common Coupling (PCC) voltage. Ref. [22] has built an impedance model and small-signal state space model. PSSC can effectively suppress oscillation with an arbitrary SCR and provide positive damping within a broad frequency band. However, there still is the large-signal stability of the PSSC-VSC.

Numerous studies have concentrated on the transient synchronization stability problem of grid-forming VSCs. The phase portrait, the Lyapunov direct method, and the equal area criterion (EAC) are commonly applied for analyzing nonlinear dynamic systems [23,24,25]. Ref. [26] compared the transient synchronization stability of four grid-forming control strategies during symmetrical grid voltage sags using phase portraits. Additionally, [27] analyzed mathematical formulations for the maximum fault clearance duration and angle in PSC-based VSCs under voltage sag conditions.

This article fills the gap in the transient stability synchronization analysis of PSSC-VSCs by using the phase portrait. A transient stability enhancement control (TSEC) strategy is applied in PSSC, which further avoids the inverter losing synchronization with the grid with an arbitrary SCR during the fault. The comparison between different controllers is listed in

Table 1. Controller comparison.

Controller	Strategy	Features
The dual-mode controller	Current source mode in the stiff grid; voltage source mode in the weak grid	(1) Complicated to realize (2) Change in software structure
The universal controller	Using PSC as a guide to design a grid-following controller	(1) Small-signal instability may happen with an SCR ≈ 1
The robust grid-forming controller	An active susceptance loop is added	(1) Case with a large SCR is unclear (2) Complex structure
The PSSC controller + TSEC controller	The modulation voltage approximates the VSC output voltage	(1) Keep VSC small signal and synchronization stable with an arbitrary SCR (2) Simple to realize (3) Without voltage sensor

, in which the benefits of the proposed method are highlighted.

The PSSC scheme is systematically introduced to enhance the stability of a grid-forming converter in a stiff grid in Section 2. In Section 3, the nonlinear dynamic equation of the power angle for the PSSC-VSC is established, and the mechanism of transient synchronous instability is analyzed by the phase portrait. In Section 4, to solve the issue of transient synchronization instability, mode-adaptive transient stability control is developed for the PSSC-VSC, and the power angle dynamic behaviors with transient stability control are illustrated through the phase portrait. The experimental results in Section 5 validate the theoretical analysis presented. A summary is provided in Section 6.

2. System Description and Dynamic Modeling

2.1. System Description

Figure 1 shows the single-line diagram of a three-phase grid-connected PSSC-VSC. L_f is the filter inductor. The grid impedance of the VSC connected to the PCC is considered a pure inductance L_g. v_i, v_PCC, and v_g are the VSC output voltage, PCC voltage, and grid voltage in the stationary frame, respectively. v_dc is the dc voltage. i_Labc is the VSC output current after the filter inductor in the stationary frame. The subscript dq denotes the variables in the dq-frame. v_dqref, v_odqref, and v_oref represent the input voltage reference of the inner control loop and the modulated voltage in the dq-frame and in the stationary frame, respectively. e_dq is the output of the integrator in the current control loop, and the high-frequency components of the input thereby can be filtered.

As illustrated in Figure 1, the controller operates within the dq-frame and is divided into two main components. PSSC manages power synchronization in the outer control loop, while the inner control loop employs a dual-loop control scheme, which includes a voltage control loop and a current control loop.

2.2. Control Loop

The external power loop adopts power self-synchronization control. As shown in Figure 2, the voltage, which is regulated in the voltage control loop and used for the power calculation, is the significant difference between PSSC and PSC.

In PSSC, the instantaneous power is calculated by the sampled grid current and the state variable e_dq rather than the grid voltage. The integrator output of the current control loop is equivalent to v_odqref as the system reaches a steady state. Thereby, e_dq is equal to v_odqref in the steady state, and the active power can be transmitted based on the phase difference between v_i and v_g.

The active power control law of the VSC can be written as

$$\omega ={\omega }_0+K_{\mathrm{p}}(P_{\mathrm{ref}}-P_{\mathrm{e}})$$

(1)

where ω₀ is the reference frequency, ω is the desired frequency of the reference voltage, K_p is the P-f controller coefficient, and P_e and P_ref are the instantaneous active power and the reference value, respectively.

Due to the dynamic difference between the outer loop and inner loop, which is more than ten times slower than the internal voltage and current loop [28], the internal loop of vector voltage and current control can be considered a unity gain with ideal reference tracking as the transient synchronization stability problem caused by the power loop.

In the conventional PSC-VSC, the voltage and current at the PCC should be sampled for voltage control and power calculation, and the capacitor filter in the AC side is necessary for voltage detection. Conversely, the proposed PSSC-VSC can calculate the active power by using e_dq and the current, while the cost for the filter capacitor and voltage sensor can ignored.

2.3. Stability Analysis of PSSC-VSC in Stiff Grids

It is worth nothing that the grid-forming VSC is prone to instability in the strong grid. When the grid-forming VSC is connected to an ultra-strong grid (SCR = ∞), the steady-state gains of the transfer functions in the active power control loop are close to infinity, and small disturbances in the control loop are amplified, which leads to system instability.

It is evident from [29] that when the PSC-VSC is connected to a stiff grid, the steady-state gains in the power loop approach infinity, which can easily lead to system instability under small disturbances. Ref. [29] has constructed a linearized small-signal model of the PSC-VSC in an active power loop. For PSSC, which does not sample the voltage of the PCC, the line inductance L_g in the original linearized small-signal model is replaced by the equivalent inductance, which is the sum of the filtering inductance L_f and the line inductance L_g. The linearized small-signal model of the PSSC-VSC in an active power loop can be written as

$$\Delta P_{\mathrm{e}}\left(\mathrm{s}\right)=V_{\mathrm{g}}{V}_{\mathrm{i}}\cos {\theta }_0\Delta \theta \left(\mathrm{s}\right)/{\omega }_0(L_{\mathrm{f}}+L_{\mathrm{g}}).$$

(2)

Due to the existence of L_f, the steady-state gains of the transfer functions can be constrained. The frequency response of the power control loop is improved by designing the control parameters, so that the PSSC-VSC is stabilized under stiff grid conditions.

From the analysis above, it can be seen that the PSSC-VSC utilizes filtering inductance and line impedance for power interaction, which shows excellent stability performance even under strong grid conditions. Furthermore, as shown in Figure 2, e_dq represents the output of the integrator in the current control loop. Therefore, high-frequency components at the input can be filtered out automatically.

3. Transient Synchronization Stability Analysis of PSSC-VSC

3.1. Dynamic Model of PSSC-VSC

It is assumed that the transmission line impedance is purely inductive and the resistive component is ignored, the voltage on the DC side of each VSC is assumed to be constant, and the frequency of the infinite grid is set as ω₀.

Figure 3 shows a simplified circuit of the PSSC-VSC connected to the grid, where X_f = ω₀L_f and X_g = ω₀L_g are the filter reactance and the line reactance, respectively. The phase difference between the PSSC-VSC output voltage v_i and the grid voltage v_g is defined as the power angle, and the grid voltage and VSC output are expressed as V_g∠θ_g and V_i∠θ_i, as shown in Figure 4. The active power output from the VSC to the infinite grid can be derived as

$$P_{\mathrm{e}}={\displaystyle \frac{3V_{\mathrm{i}}{V}_{\mathrm{g}}}{2(X_{\mathrm{g}}+X_{\mathrm{f}})}}\sin \delta$$

(3)

Considering θ = ωt, the power angle and the frequencies of VSC and the grid satisfy

$$\delta ={\theta }_{\mathrm{g}}-{\theta }_{\mathrm{i}}=\int \omega -{\omega }_0.$$

(4)

For Equation (4), the derivative of δ, i.e., ∆ω, is obtained as

$$\dot{\delta }=\omega -{\omega }_0.$$

(5)

ω₀ is subtracted from both sides of Equation (1), and substituting Equation (3) into Equation (1), it can be derived as

$$\mathsf{\omega }-{\omega }_0=K_{\mathrm{p}}\left[P_{\mathrm{ref}}-{\displaystyle \frac{3V_{\mathrm{i}}{V}_{\mathrm{g}}}{2(X_{\mathrm{g}}+X_{\mathrm{f}})}}\sin \delta \right].$$

(6)

Then, substituting Equation (5) into Equation (6), the dynamic behavior of the power angle for the PSSC-VSC can be obtained as

$$\dot{\delta }=K_{\mathrm{p}}\left[P_{\mathrm{ref}}-{\displaystyle \frac{3V_{\mathrm{i}}{V}_{\mathrm{g}}}{2(X_{\mathrm{g}}+X_{\mathrm{f}})}}\sin \delta \right].$$

(7)

From Equation (7), if the reference active power exceeds the maximum transmissible active power, i.e., P_ref > $3V_{\mathrm{i}}{V}_{\mathrm{g}}/2(X_{\mathrm{g}}+X_{\mathrm{f}})$, according to the trigonometry theorem, δ will have no feasible solution and $\dot{\delta }$ will never equal zero. Similar to the PSC-VSC, the PSSC-VSC still suffers from the transient synchronization instability issue.

In order to maintain PSSC-VSC transient synchronization stability during the fault, the reference active power is not allowed to exceed the maximum transmissible active power. The transient synchronization stable boundary of PSSC-VSC can be derived as

$${\displaystyle \frac{P_{\mathrm{ref}}}{\frac{3V_{\mathrm{i}}{V}_{\mathrm{g}}}{2(X_{\mathrm{g}}+X_{\mathrm{f}})}}}={\displaystyle \frac{P_{\mathrm{ref}}}{P_{\mathrm{MAX}}}} < 1.$$

(8)

3.2. Dynamic Response of Power Angle for PSSC-VSC

The mathematical relationship between $\dot{\delta }$ and δ is explicitly derived by Equation (7), which is critical to the transient stability analysis. However, due to the high nonlinearity, it is difficult to acquire an analytical solution of Equation (7). In contrast, a graphical evaluation can be easily carried out by the $\dot{\delta }$–δ curve, which is the so-called phase portrait. Based on the phase portrait, the change in δ can be readily predicted, i.e., δ will increase if $\dot{\delta }$ > 0 and decrease if $\dot{\delta }$ < 0, and $\dot{\delta }$ = 0 corresponds to the equilibrium points.

According to the parameters listed in

Table 2. System parameters.

Symbol	Value	Symbol	Value	Symbol	Value
f0	50 Hz	Lf	4 mH	Pref	10 kW
Vdc	750 V	Vg	311 V	Kp	0.0002
Lg	20 mH	Vi	311 V	KLL	−0.75

, the phase portrait under a normal condition (V_g = 1 p.u.) is plotted with the solid line in Figure 4. There are two equilibrium points, where point a (the solid dot) is the stable equilibrium point (SEP), since δ can return to SEP. However, point b (the open circle) is the unstable one, since a small disturbance will force δ to depart from this point. It is known from Equation (3) that a voltage sag of the grid can cause a decrease in the maximum transmissible active power, which may be smaller than P_ref, and will lead to the loss of synchronization. Depending on the depth of the voltage sag, there will be two scenarios.

In the first scenario, the equilibrium points still exist after the fault. V_g dropping to 0.7 p.u. leads to a higher phase portrait; it still crosses zero at points d and e which are the two equilibrium points. At the moment of the fault occurring, the operating point jumps from a to c. Then, δ starts to increase due to $\dot{\delta }$ > 0, which forces the operating point to move from c to d, shown as the red line with arrows. Once the operating point reaches point d, a new steady state is achieved due to $\dot{\delta }$ = 0, and δ will stop at δ₂ and never exceed δ₂, as shown in Figure 5 by the green line with arrows. In the second scenario, V_g dropping to 0.2 p.u. causes the loss of equilibrium points and δ will diverge to infinity as $\dot{\delta }$ > 0 always remains, shown as the blue line with arrows.

4. Transient Stability Enhancement for PSSC-VSC

4.1. Transient Stability Enhancement Control Scheme

To address the transient stability problem of the PSSC-VSC, a mode adaptive scheme for transient stability enhancement control (TSEC) [30] is developed for PSSC. Additionally, the concept of virtual orthogonal power (VOP) is proposed to enhance the transient stability. By utilizing mathematical relations involving trigonometric functions, the VOP P_ν of the PSSC-VSC can be precisely defined and calculated by

$$P_{\mathsf{\nu }}={\displaystyle \frac{3V_{\mathrm{i}}{V}_{\mathrm{g}}}{2(X_{\mathrm{g}}+X_{\mathrm{f}})}}\cos \delta .$$

(9)

During grid voltage sags, P_ref is always larger than the output active power P_e, and the integral link for the active power error in the PSC loop leads to the power angle continuing to increase. Consequently, it is necessary to dynamically adjust P_ref when the power angle surpasses the critical threshold of π/2 rads.

From Figure 6, P_e/P_ν changes cyclically with δ. According to the tangent property, δ is related to P_e/P_ν by Equation (10) in the range from 0 to π.

$$\mathsf{\delta }=\left\{\begin{array}{c}\mathrm{a}\mathrm{r}\mathrm{c}\mathrm{t}\mathrm{a}\mathrm{n}(P_{\mathrm{e}}/P_{\mathsf{\nu }}) P_{\mathrm{e}}/P_{\mathsf{\nu }}>0\\ \mathrm{a}\mathrm{r}\mathrm{c}\mathrm{t}\mathrm{a}\mathrm{n}(P_{\mathrm{e}}/P_{\mathsf{\nu }})+\mathsf{\pi } P_{\mathrm{e}}/P_{\mathsf{\nu }}<0\end{array}\right.$$

(10)

where δ serves as a direct indicator of the power angle of the VSC. As illustrated in Figure 6, the PSSC-VSC operates in mode 1 when 0 < δ < π/2 and mode 2 when π/2 < δ < π. Furthermore, the ratio P_e/P_ν undergoes sharp variation when δ approaches π/2.

Based on the correlation between P_e/P_ν and the power angle δ, a novel TSEC method is proposed, as shown in Figure 7. In this proposed approach, the transient stability enhancement control scheme is activated when δ approximates π/2 and deactivated when δ significantly deviates from π/2. In this paper, the critical conditions for disabling and enabling the transient synchronization stability control method occur when δ is less than 1.5 rad and greater than 1.6 rad, respectively. P_e/P_ν is restricted to the upper or lower limit by the limitation block, as shown in Figure 7.

P_ref is continually amended to an appropriate value via adding the limited P_e/P_ν to it, which causes δ to slightly change around π/2 rad and avoids δ increasing to infinity, as shown in the dashed-line area of Figure 7. When adopting TSEC, the reference power P_ref is adjusted to (1 + P_e/P_ν)P_ref, which is called the equivalent reference power $P_{\mathrm{ref}}^{\mathrm{eq}}$. The original power control loop of PSSC, i.e., Equation (1), is also corrected to Equation (11), corresponding to Figure 7.

$$\mathsf{\omega }={\omega }_0+K_{\mathrm{p}}\left[\underset{P_{\mathrm{ref}}^{\mathrm{eq}}}{\underbrace{(1+{\displaystyle \frac{P_{\mathrm{e}}}{P_{\mathsf{\nu }}}})P_{\mathrm{ref}}}}-P_{\mathrm{e}}\right]$$

(11)

Figure 8 shows the flowchart of TSEC. Firstly, the power angle, the output active power, and the virtual orthogonal power are obtained in real time. Then, determining whether the startup condition is met, if the faults cause δ > 1.6 rad, the proposed control scheme is activated to maintain VSC synchronizing with the grid. After the faults have been cleared, δ will decrease until it is smaller than 1.5 rad, and the proposed control scheme is switched to regular PSSC.

4.2. Dynamic Response of Power Angle for PSSC-VSC Adopting TSEC

When TSEC is activated, combining Equations (7) and (10) can yield the nonlinear dynamic equation of the power angle:

$$\dot{\delta }=K_{\mathrm{p}}\left[\left(1+{\displaystyle \frac{P_{\mathrm{e}}}{P_{\mathsf{\nu }}}}\right)P_{\mathrm{ref}}-{\displaystyle \frac{3V_{\mathrm{i}}{V}_{\mathrm{g}}}{2(X_{\mathrm{g}}+X_{\mathrm{f}})}}\sin \delta \right].$$

(12)

The power angle is δ₀ (point a) in a normal state, as shown in Figure 9. During the fault, point a will instantly change to a*. Due to the lack of SEP, the power angle will increase as a result of $\dot{\delta }$ > 0 and move from a* to b due to the phase portrait. While δ exceeds the trigger value (point b), which is smaller than π/2 rad, transient synchronization stability control will be activated and will operate in mode 1, which causes the operating point to move from b to b*. Since P_e/P_ν is larger than zero, P_ref in mode 1 will rise, which further increases δ from b* to c, shown by the green line in Figure 9. It is noted that P_e/P_ν will be restricted to the upper limit K_UL.

When the power angle slightly crosses π/2 rad, P_e/P_ν immediately jumps from the upper limit K_UL to the lower limit K_LL, and the PSSC-VSC operates in mode 2, as depicted by the solid blue line in Figure 9. The operating point shifts from c to c*. By appropriately selecting the K_LL, $\dot{\delta }$ can be smaller than zero in c*, and the power angle will reduce to π/2 rad, as shown by the blue line with arrows. Upon the power angle dropping below π/2 radians once more, the PSSC-VSC reverts to mode 1, leading to an instantaneous change in the operating point from d to d*.

It is easy to find that the slope of δ is smaller than zero in dot c*. Thus, the lower limit K_LL is crucial and should be set appropriately. In mode 2, the K_LL must satisfy

$$\dot{\delta }=K_{\mathrm{p}}\left[(1+K_{\mathrm{LL}})P_{\mathrm{ref}}-{\displaystyle \frac{3V_{\mathrm{i}}{V}_{\mathrm{g}}}{2(X_{\mathrm{g}}+X_{\mathrm{f}})}}\sin \delta \right] < 0.$$

(13)

δ is regarded as π/2 rad, and the K_LL can be derived according to (13) as

$$K_{\mathrm{LL}}<{\displaystyle \frac{3V_{\mathrm{i}}{V}_{\mathrm{g}}}{2(X_{\mathrm{f}}+X_{\mathrm{g}})P_{\mathrm{ref}}}}- 1.$$

(14)

5. Experimental Verification

In this section, the experimental tests are used to verify the correctness of the theoretical analysis. The following cases are verified in the experimental tests: (1) the transient behaviors of the power angle for the PSSC-VSC; (2) the effectiveness of the PSSC with TSEC. The experimental tests are implemented on the real-time digital simulator based on the NovaCor 2.0 hardware simulation platform, as shown in Figure 10.

5.1. Dynamic Response of Power Angle for PSSC-VSC during Fault

First, the transient responses of the PSSC-VSC under different grid voltage sag conditions are tested. The waveforms of the active power P_e, the output voltage V_i, the output current I, and the power angle δ are displayed. Figure 11a shows the experimental results with PSSC, where the controller parameters in Table 2 are adopted. When V_g drops to 0.7 p.u., there still exists an equilibrium point after the fault. In Figure 11a, δ exhibits a gradual increase and attains a new steady state without any overshoot, which confirms the first-order dynamic behavior of the PSSC-VSC. The experimental dynamic behavior of δ corresponds to the theoretical analysis in Figure 4. The active power delivered to the grid immediately decreases due to the grid voltage sag, as shown in Figure 11a. However, when V_g drops to 0.4 p.u., the equilibrium points no longer exist, and the output active power of the PSSC-VSC is smaller than P_ref, which leads to constant increases in δ. Figure 11b illustrates the emergence of low-frequency oscillations in the waveforms of P, δ, V, and I, and the results are consistent with the analysis.

5.2. Verification of PSSC-TSEC Inverter during Symmetrical Fault

The experimental results of the PSSC-VSC with TSEC during a symmetrical fault are elaborated in Figure 12.

Figure 12 shows the waveforms of the PSSC-VSC with TSEC when V_g drops to 0.4 p.u. It can be observed in Figure 12 that when δ crosses 1.6 rad, transient stability enhancement control is enabled to adaptively change the equivalent P_ref. P_e/P_ν jumps continuously between positive and negative values, which also triggers the rapid change in $P_{\mathrm{ref}}^{\mathrm{eq}}$, and transient synchronization stability control is switched between mode 1 and mode 2. Since the power angle is fixed at π/2 rad, even if there is no SEP after the voltage droop, the output active power of the PSSC-VSC can be kept constant. After the grid voltage recovers to the normal value, the power angle gradually decreases until it is below 1.50 rad; then, the PSSC-VSC will return from TSEC to conventional PSSC.

In order to demonstrate the benefits and broad application of the proposed controller in arbitrary SCR, the experimental results with an SCR = ∞ and an SCR = 1.2 are elaborated in Figure 13. The power synchronization coefficient K_p = 0.0006 and P_ref = 3 kW in both scenarios. And L_g = 0 and L_f = 7 mH when the SCR = ∞.

Figure 13 shows the waveforms of the PSSC-VSC with TSEC when V_g drops to 0.3 p.u. It can be observed in Figure 13 that when δ crosses 1.6 rad, transient stability enhancement control is enabled. The combination of PSSC and TSEC guarantees the synchronization of the inverter with the grid under ultra-strong or ultra-weak grid conditions, which also indicates the widespread application of the proposed controller in engineering.

The scenario of a big load change is also considered in this article. The load is set to a pure resistance and the value is 6 Ω. Figure 14 shows the waveforms as the load switches off and switch on. When the load is connected to the system, the active power and current between the inverter and the grid will both decrease, which corresponds to the reduction in δ. It is obvious from Figure 14 that the load change will not affect the stability of the PSSC-based inverter.

5.3. Verification of PSSC-TSEC Inverter during Asymmetrical Fault

It is confirmed that PSSC-TSEC is still useful in the conditions of an asymmetrical fault, and the waveforms are demonstrated in Figure 15.

Figure 15a,b correspond to the scenario of a single-phase short-circuit fault and a two-phase short-circuit fault which occurred in the transmission line, respectively. When the asymmetric fault occurs, TSEC is activated and the inverter power angle is regulated to stay at 1.6 rad. After the fault disappears, TSEC is cut off and the inverter returns to normal PSSC operation, which illustrates that TSEC has no influence on the system during regular operation. The effectiveness of PSSC-TSEC during an asymmetrical fault can further reflect the value in engineering applications.

6. Conclusions

This article investigates the transient synchronization stability of PSSC-based VSCs. A comprehensive large-signal model is developed to characterize its dynamics; the power angle transient response is evaluated by phase portraits. The main contributions are outlined below:

(1)

Although the PSSC-based VSC can keep the small signal stable in SCR ranges from 1 to ∞, it still faces the problem of the loss of synchronization with the grid during faults.

(2)

A large-signal model is established and it is found that the imbalance between the output active power and the reference active power causes the transient instability of the PSSC-based VSC.

(3)

The dynamic behavior of the power angle is elucidated. Since the large-signal model of the PSSC-based VSC is equipped with a first-order nature, there is no overshot in the power angle response.

(4)

To keep the PSSC-based VSC synchronized with the grid during faults, transient stability enhancement control is adopted which obviously keeps the PSSC-VSC synchronizing with the grid with an arbitrary SCR during the fault.

(5)

The PSSC-based VSC integrating TSEC scheme has a broad application perspective. It is simple to set the software and the structure of essential controller does not need to vary during the fault. Most importantly, the proposed controller is still effective in both ultra-strong and ultra-weak grids.

(6)

The inverter controlled by PSSC-TSEC can maintain synchronization with the grid in both symmetrical and asymmetrical faults.