A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation
Abstract
:1. Introduction
2. Delta-Sigma ADC Architecture
3. System Simulation and Circuit Implementation of CTDSM
3.1. Specification Planning of Delta-Sigma Modulator
3.2. Simulink Model Development and Simulation
3.3. CTDSM System Circuit
3.3.1. Operational Amplifier with Current Reuse
3.3.2. First Stage Common-Mode Feedback Circuit
3.3.3. Second Stage Common-Mode Feedback Circuit
3.3.4. Simulation Results of the Operational Amplifier
3.3.5. Quantiser and 1-Bit NRZ DAC
4. System Simulation and Layout
4.1. System Simulation
4.2. Layout
4.3. Measurement Results
4.4. Literature Comparison
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
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Delta-Sigma Modulator | Specification |
---|---|
ENOB [bits] | >12 bits |
SNDR [dB] | >74 dB |
Power Consumption [μW] | <50 μW |
VDD [V] | 1.2 V |
Input Signal [V] | 0.6 ÷ 0.3 V |
Signal Bandwidth [kHz] | 10 kHz |
Order | 2 |
OSR | 128 |
Quantiser bit | 1 |
Technology | UMC 0.18 um |
] | Value | C [μF] | Value |
---|---|---|---|
1348.22 | 3.09 | ||
94.8 | 3.09 | ||
674.11 |
Specification. | Pre-Simulation | Post-Simulation | Measurement | |
---|---|---|---|---|
Process Technology | UMC 0.18 um | |||
Supply Voltage MI | 1.2 | |||
Bandwidth [Hz] | 10 k | |||
Input Amplitude [V] | 0.3 | |||
SNDR [dB] | 74 @TT-Corner | 82.75 | 81.15 | 78.42 |
Resolution [bits] | 12 @TT-Corner | 13.45 | 13.18 | 12.73 |
Dynamic Range [dB] | As large as possible | 86 | 84 | 84 |
Power [μW] | <50 @2.56MHz | 22.24 | 22.76 | 15.97 |
FOM 1 [pJ/conv.] | As small as possible | 0.0994 | 0.1226 | 0.1175 |
FOM 2 [dB] | As large as possible | 172.53 | 170.43 | 171.97 |
Ref. | [19] | [20] | [21] | [22] | [23] | [24] | [25] | [26] | This Work |
---|---|---|---|---|---|---|---|---|---|
Type | DT | SI-DT | CT | DI-DT | CT | DT | CT | ADSM | CT |
OSR | 100 | 128 | 80 | 64 | 128 | 256 | 256 | 128 | 128 |
SNDR [dB] | 84 | 71.9 | 64 | 80.4 | 95.2 | 89 | 80 | 92 | 78.42 |
ENOB [bits] | 13.66 | 11.65 | 10.34 | 13.06 | 15.52 | 12.73 | 10 | 15 | 12.73 |
BW [HZ] | 20k | 10k | 2k | 10k | 25k | 10k | 1 | 10k | 10k |
Power [μW] | 860 | 12,100 | 96 | 24.8 | 800 | 670 | 15 | 290 | 15.97 |
VDD | 1 | 3.3 | 1.6 | 1.0 | 1.0 | 1.8-5 | 1.2 | 1 | 1.2 |
Process [um] | 0.18 | 0.35 | 0.15 | 0.065 | 0.065 | 0.18 | 0.065 | 0.18 | 0.18 |
FOM 1 [pJ/conv.] | 1.66 | 188.26 | 18.53 | 0.145 | 0.34 | 4.93 | 1155.26 | 0.45 | 0.1175 |
FOM 2 [dB] | 157.67 | 141.17 | 137.19 | 167.56 | 177.9 | 165.54 | 153.24 | 187 | 171.97 |
Publication | IEDE Trans. Circuit sys. | IEEE Trans. On Power Electronics | IEEE Trans. Circuit sys. | IEEE Trans. Instrum. Meas. | IEDE JSSC | IEEE ASSCC | IEEE Access | MDP Sensors | Measurement |
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Shiue, M.-T.; Ou, Y.-C.; Li, G.-S. A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation. Electronics 2024, 13, 3459. https://doi.org/10.3390/electronics13173459
Shiue M-T, Ou Y-C, Li G-S. A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation. Electronics. 2024; 13(17):3459. https://doi.org/10.3390/electronics13173459
Chicago/Turabian StyleShiue, Muh-Tian, Yang-Chieh Ou, and Guan-Shum Li. 2024. "A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation" Electronics 13, no. 17: 3459. https://doi.org/10.3390/electronics13173459