An Analog Integrated Multiloop LDO: From Analysis to Design

Abstract

This paper introduces a multiloop stabilized low-dropout regulator with a DC power supply rejection ratio of 85 dB and a phase margin of 80°. It is suitable for low-power, low-voltage and area-efficient applications since it consumes less than 100 μA. The dropout voltage is only 400 mV and the power supply rails are 1 V. Furthermore, a full mathematical analysis is conducted for stability and noise before the circuit verification. To confirm the proper operation of the implementation process, voltage and temperature corner variation simulations are extracted. The proposed regulator is designed and verified utilizing the Cadence IC Suite in a TSMC 90 nm CMOS process.

1. Introduction

In the rapidly evolving field of electronics, power management solutions are critical to the performance and reliability of modern devices [1,2,3]. Low-dropout (LDO) regulators, which maintain a constant output voltage despite variations in input voltage or load conditions, are essential components in these systems [4,5,6]. Their ability to provide precise voltage regulation with minimal noise makes them invaluable in a variety of applications, from consumer electronics to industrial equipment [7,8,9,10]. As technology advances, the demand for efficient, reliable and compact LDO designs continues to grow, driving innovation in this crucial area of power management [4,6,11,12].

The core function of an LDO regulator is to provide a stable output voltage while operating with a small difference between the input and output voltage, known as the dropout voltage [4,13,14,15]. This characteristic is particularly beneficial in battery-powered devices where maximizing efficiency is paramount [16]. Unlike switching regulators, which can generate significant noise and electromagnetic interference, LDOs offer a cleaner, quieter alternative, making them ideal for sensitive analog and digital circuits [17,18]. The simplicity of LDO designs also contributes to their popularity, as they typically require fewer external components and occupy a smaller footprint.

As electronic devices become more sophisticated and power-hungry, the challenges associated with LDO regulator design become more pronounced [19,20]. Engineers must balance various performance parameters, such as load regulation, power supply rejection ratio (PSRR), transient response, and thermal management [21,22,23,24]. Additionally, the trend towards miniaturization demands that these regulators not only perform efficiently but also occupy minimal space. Addressing these challenges requires innovative design strategies and a deep understanding of the underlying principles of LDO operation.

Prior development of LDO regulators focused on low-quiescent current [25] and improving the transient response with various techniques. These techniques are capable of minimizing compensation capacitance and speed up the transient response by using capacitorless LDO regulators with fast feedback technique [26]. In order to support a wide load capacitor, a weighted current feedback (WCF) technique was developed to improve the transient performance metrics under low quiescent power design objectives [27]. This paper develops a multiloop compensation technique whose purpose is to improve the transient performance of the LDO regulator by minimizing the compensation capacitor but at the same time achieving excellent stability performance.

There are many commercial applications where LDO regulators are a necessary circuit. Some of the most recent applications are LDOs for charging mobile smart phones by using an independent solar charger [28], which implement a simple and classic LDO design. Another technique which has been adopted for Li-ion battery LDO-based chargers is a three-mode control comprising trickle constant current, fast constant current and constant voltage modes [29]. This work introduces an LDO regulator which uses a multiloop compensation technique for low-power applications and research purpose.

This work illustrates the following concepts:

• In the literature, there are different publications in which a multiloop compensation technique is analyzed for a variety of operational amplifiers, while in this work, an LDO which employs this technique is proposed.
• A low-voltage, low-power and area-efficient NMOS LDO is introduced for efficient power management and high performance.
• A fully mathematical analysis for stability and noise performance is conducted, which presents the trade-off between the circuit’s parameters and performance. This can be used as a promising tool for optimal pre-simulation (design) parameter selection.

This paper delves into the fundamental aspects of multiloop LDO regulators, exploring their design considerations, performance and related analysis and modeling of the proposed architecture. The remainder of this paper is organized as follows: Section 2 introduces the proposed LDO architecture along with the multiloop amplifier’s transistor-level implementation. A pure mathematical modeling approach based on a small-signal model for stability and noise analysis is provided in Section 3. The related simulation results of the proposed LDO are summarized in Section 4. A comparison study and discussion are summarized in Section 5. Lastly, Section 6 concludes this work.

2. LDO Architecture

2.1. Typical LDO Architecture

LDO regulators are essential components in modern applications [21,22,23,24]. Figure 1 depicts a typical LDO structure, which comprises a bandgap reference circuit (BGR) [10,30], which will not be analyzed in this paper, an error amplifier, which provides the essential gain value, and a large transistor, called the pass-transistor, which delivers the current to the load capacitor $C_{Load}$ of the LDO.

N-channel metal-oxide semiconductor (NMOS) LDOs, in general, have many advantages, such as low output resistance, straightforward compensation and better load regulation; however, their main drawback is the limited dropout voltage, which is the reason why they may seem inappropriate for low-voltage applications [21,22,23,24]. This is why in the implemented design, a native NMOS transistor, $Mpas{s}_{na}$, is selected to serve as a pass device [31]. Their nearly zero threshold voltage makes them suitable for LDO designs that require a very low dropout voltage. Furthermore, the low voltage requirements of modern applications [32,33,34,35,36] make the LDO design even more challenging. The low supply voltage makes it impossible to use simple cascode amplification stages to achieve high PSRR, and therefore, cascade amplification stages must be used, making stability analysis very complex. So, in this paper, a new three-stage amplifier architecture will be presented, which will be used as an error amplifier to the LDO regulator using a multiloop Miller compensation technique [37] in order to improve the stability performance, along with a detailed stability and noise analysis.

2.2. High-Level Architecture

The structure of the proposed three-stage error amplifier (EA) is depicted in Figure 2, where the output resistance and capacitance of each stage are denoted by $R_{1-3}$ and $C_{1-3}$, respectively. $C_c$ is the compensation capacitor and $C_L$ is the load capacitance, which, in this case, is the parasitic capacitance $C_{gs}$ of the pass transistor. The transconductance gain stages $g_{m1-3}$ form a three-stage amplifier while the two feed-forward paths are realized by the gain stages $g_{mf1}$ and $g_{mf2}$, respectively. The purpose of implementing the feed-forward path from the input of the first stage to the output of the second is to introduce a left-handplane zero in order to improve the stability performance of the structure. The feedback network is realized by the compensation capacitor $C_c$ in the Miller architecture, which can be used to place the dominant pole of the system to the desired position but also introduces a right-handplane zero to the system. The main advantage of the proposed architecture is that the left-handplane zero added by the implementation of the feed-forward path $g_{mf1}$ to the system should be used to compensate the negative phase shift of the first non-dominant pole. Furthermore, the use of only one compensation capacitor saves valuable chip area while keeping the slew rate performance of the amplifier almost unaffected. The push-pull output and second stage formed by the transconductance and the feed-forward paths $g_{m2}$ and $g_{mf1}$, as well as $g_{m3}$ and $g_{mf2}$, enhance the transient performance of the proposed amplifier while keeping the power consumption low at steady state.

2.3. Multiloop Amplifier

The circuit implementation of the proposed architecture is depicted in Figure 3 and will be described in detail in this sub-section. The first stage of the amplifier is realized by a folded cascode NMOS operational transconductance amplifier OTA. NMOS OTA was preferred over a p-channel metal-oxide semiconductor (PMOS) due to the fact that the power supply voltage is 1 V while the reference voltage is quite high in comparison with the supply voltage at $0.6$ V. So, the use of a PMOS OTA is prohibitive because it would be impossible to bias the PMOS current mirror which provides the necessary bias current to the differential pair. It consists of the transistors $M_{n1}$ and $M_{n2}$, which comprise a simple differential pair realizing the first transconductance gain $g_{m1}$. The second transconductance stage consists of the transistor $M_{n6}$ connected in a simple common source topology along with the PMOS current mirror $M_{p5}, M_{p6}$, which inverts the phase of the signal, thus making the gain positive. The transistor $M_{n7}$ represents the first feed-forward path and it can be easily biased by properly scaling the NMOS current mirror $M_{n4}, M_{n5}$, as well as the PMOS current mirror $M_{p5}, M_{p6}$, forming a push-pull stage. Finally the output gain stage is formed by the transistor $M_{p7}$ in a common source topology, while the second feed-forward stage $g_{mf2}$ is realized by the transistor $M_{n8}$. Yet again, the second feed-forward stage comprises a push-pull output stage, which can be easily biased by sizing properly the current mirror $M_{n4}, M_{n5}$ as well as the transistor $M_{n8}$. The compensation capacitor $C_c$ represents the feedback network, which will by used to stabilize the amplifier, while the $C_L$ capacitor is the load capacitance of the amplifier, in this case, the parasitic capacitance $C_{gs}$ of the pass transistor. The transistor dimensions are depicted in

Table 1. Transistor dimensions.

Transistor	W/L ($\mathsf{\mu }$m/$\mathsf{\mu }$m)
$M_{n1},M_{n2}$	$8/0.5$
$M_{n3}$	$19.3/1$
$M_{n4},M_{n5}$	$8/1$
$M_{n6},M_{n7}$	$0.8/1$
$M_{n8}$	$19.2/1$
$M_{p1},M_{p2}$	$24/1$
$M_{p3},M_{p4}$	$40/1$
$M_{p5},M_{p6}$	$2/1$
$M_{p7}$	$16/1$

.

3. LDO Analysis and Modeling

3.1. Stability Analysis

In this section, an analytical stability analysis will be conducted. The computation of the transfer function is a necessity in order to properly analyze the circuit; the small signal model of the proposed architecture is depicted in Figure 4 [37,38]. Applying the Kirchhoff voltage and current laws leads to the following system of equations in the Laplace frequency domain:

$$V_1={\displaystyle \frac{g_{m1}{R}_1{V}_{in}+s{R}_1{C}_c{V}_{out}}{1+s{R}_1(C_c+C_1)}}$$

(1)

$$V_2={\displaystyle \frac{g_{m2}{R}_2{V}_2-g_{mf1}{R}_2{V}_{in}}{1+s{R}_2{C}_2}}$$

(2)

$$V_{out}={\displaystyle \frac{-g_{m3}{R}_3{V}_2+(s{C}_c{R}_3-g_{mf2}{R}_3)V_1}{1+s{R}_3(C_c+C_3)}}$$

(3)

where $V_i$ is the AC voltage across the i-node, $g_{mi}$ is the conventional transconductance gain of each stage, $R_i$ and $C_i$ are the output resistance and capacitance of each stage, while $g_{mfi}$ represents the transconducnce gain of each feed-forward path.

The solution of the above system results in the transfer function of the circuit by taking into consideration the following assumptions: (1) the compensation capacitor $C_c$ is much greater than the parasitic capacitor $C_{1-3}$ and the load capacitor $C_L=C_{gs}$. (2) the gain of each stage is much greater than 1.

$$G\left(s\right)={\displaystyle \frac{V_{out}}{V_{in}}}={\displaystyle \frac{N\left(s\right)}{D\left(s\right)}}$$

(4)

The nominator of the transfer function is

$$N\left(s\right)=s^2{C}_c{C}_2{R}_1{R}_2{R}_3{g}_{m1}+s{R}_1{R}_2{R}_3(g_{m3}{g}_{mf1}{C}_c-g_{m1}{g}_{mf2}{C}_2)-A_{dc}$$

(5)

where $A_{dc}=g_{m1}{g}_{m2}{g}_{m3}{R}_1{R}_2{R}_3$. The nominator of the transfer function is a second-degree polynomial function whose roots are the zeros of the system. It is easily understood that there is one positive and one negative root since the constant term of the polynomial is a negative number. So, a right-handplane zero is introduced, which should lie at very high frequencies by properly choosing the value of the transconductance gain $g_{mf2}$, as well as a left-handplane zero, which will cancel the negative phase shift of the first non-dominant pole by tuning the value of the first feed-forward transconductance gain $g_{mf1}$.

The denominator of the transfer function is

$$D\left(s\right)=s^3{C}_c{C}_1{R}_1{R}_2{R}_3+s^2{C}_c{C}_2{R}_1{R}_2{R}_3{g}_{mf2}+s{C}_c{R}_1{R}_2{R}_3{g}_{m2}{g}_{m3}+1$$

(6)

Due to the computational complexity which the transfer function introduces to the analytical computation of the poles, the Open-Circuit Time Constants (OCTC) method is applied [39]. OCTC gives an estimation (usually pessimistic) for the position of the poles of a circuit. The accuracy of this method is sufficient when designing a circuit by providing much simpler equations, especially when dealing with complicated transfer functions. So, by applying this method, the dominant pole is derived as

$$p_{-3db}={\displaystyle \frac{1}{C_c{R}_1{R}_2{R}_3{g}_{m2}{g}_{m3}}}$$

(7)

which is expected, as it can also be approximated using the first-order coefficient and the constant term of the denominator of the transfer function. In amplifier design, a single-pole approximation is usually desirable in order to achieve both high DC gain, which means high DC PSRR when used as an error amplifier in an LDO, and decent stability performance. The calculation of the unity gain frequency ${\omega }_t$ is a necessity when stabilizing an amplifier. In a single-pole approximation, the unity gain frequency can be easily derived as

$${\omega }_t=A_{dc}\ast p_{-3db}={\displaystyle \frac{g_{m1}}{C_c}}$$

(8)

From the last result, it is obvious that in order to increase the bandwidth of the amplifier, the first stage should be biased in such a manner as to result in a higher transconductance gain $g_{m1}$ or the capacitance of the compensation capacitor should be reduced. The system must have a decent phase margin in order to ensure that it is always stable and robust. The phase margin is given by

$${\varphi }_{pm}={90}^o-ta{n}^{-1}\left({\displaystyle \frac{{\omega }_t}{p_{-3db}}}\right)-ta{n}^{-1}\left({\displaystyle \frac{{\omega }_t}{{\omega }_{p1}}}\right)-ta{n}^{-1}\left({\displaystyle \frac{{\omega }_t}{{\omega }_{z1}}}\right)-ta{n}^{-1}\left({\displaystyle \frac{{\omega }_t}{{\omega }_{p2}}}\right)-ta{n}^{-1}\left({\displaystyle \frac{{\omega }_t}{{\omega }_{z2}}}\right)$$

(9)

where ${\omega }_{p1}$ and ${\omega }_{p2}$ represent the non-dominant poles of the system and ${\omega }_{z1}$ and ${\omega }_{z2}$ are the right- and the left-handplane zeros, respectively. As mentioned above, the frequencies where the second non-dominant pole and the right-handplane zero lie are much higher than the unity gain frequency, so it must be ensured that ${\omega }_{p1}={\omega }_{z1}$ in order to achieve the optimal phase margin.

3.2. Noise Analysis

Noise in LDO regulators is a typical parameter that should be taken into consideration when designing. It refers to the thermal and flicker noise of transistors and resistors specified as the output voltage spectral density ($V/\sqrt{\mathrm{Hz}}$) or as the integrated voltage density ($V_{rms}$), which is the integration of the output voltage spectral density over a bandwidth [37,38]. The main noise contributors in LDO regulators are $S{n}_{ref}\left(f\right)$, $S{n}_{EA}\left(f\right)$, $S{n}_{pass}\left(f\right)$, $S{n}_R\left(f\right)$, which represent the output voltage density of the reference voltage, the error amplifier, the pass transistor and the resistance R of the feedback network, respectively [23]. So, the noise of an LDO regulator is given by

$$S_n\left(f\right)=S{n}_{ref}\left(f\right)+S{n}_{EA}\left(f\right)+S{n}_{pass}\left(f\right)+S{n}_R\left(f\right)$$

(10)

The noise provided by the error amplifier is typically much higher than the noise of the voltage reference, the pass transistor and the feedback network. So, by taking into consideration this assumption, the noise of the LDO regulator is derived as

$$S_n\left(f\right)=S{n}_{EA}\left(f\right)$$

(11)

So, it is essential to analytically calculate the output voltage density of the three-stage proposed error amplifier, which is given by the following equation:

$$S{n}_{EA}\left(f\right)=S{n}_1\left(f\right)+{\displaystyle \frac{S{n}_2\left(f\right)}{A_{v1}}}+{\displaystyle \frac{S{n}_3\left(f\right)}{A_{v1}{A}_{v2}}}$$

(12)

where $S{n}_i\left(f\right)$, $A_{vi}$ are the output voltage density and the voltage gain of the i-stage, respectively. So, by assuming that the voltage gain is much greater than 1, the output voltage density of the error amplifier depends only on the noise provided by the first stage.

$$S{n}_{EA}\left(f\right)=S{n}_1\left(f\right)$$

(13)

The output spectral density of each component is calculated by the equivalent thermal noise in the input of each transistor $v_{eq}^2$, multiplied by the voltage gain $A_v={(vout/v_{eq})}^2$. The equivalent thermal noise in the input of each transistor is given by

$$v_{eq}^2=4KT\left({\displaystyle \frac{2}{3g_m}}\right)\delta f$$

(14)

The first stage consists of a folded cascode differential pair, so the output spectral density is

$$S{n}_{EA}\left(f\right)=2S{n}_{M{n}_{1,2}}+{\left({\displaystyle \frac{g{m}_{M{n}_{4,5}}}{g{m}_{M{n}_{1,2}}}}\right)}^2(S{n}_{M{n}_4}+S{n}_{M{n}_5})$$

(15)

$$S{n}_{EA}\left(f\right)=4KT{\displaystyle \frac{4}{3g_{m1}}}(1+\sqrt{{\displaystyle \frac{{\mu }_p{(W/L)}_{M{n}_{4,5}}}{{\mu }_n{(W/L)}_{M{n}_{1,2}}}}})\delta f$$

(16)

where ${\mu }_p$ and ${\mu }_n$ is the mobility of the holes and electrons, respectively, which is strongly dependent on the temperature. Equation (16) implies that in order to reduce the noise of the LDO regulator, the transconductance gain $g_{m1}$ of the first stage should be increased. Furthermore, the $W/L$ ratio of the transistors $M_{n4}$ and $M_{n5}$ should be the minimum possible as long as the biasing of the first stage remains unaffected.

4. Simulation Results

In this section, the performance of the previous analyzed architecture will be presented. The circuit was simulated in the TSMC 90 nm process. All the simulation results are conducted in the implemented layout shown in Figure 5. The simulation results have been derived from the layout, and they include parasitics related to the resistance (R) and capacitance (C). More specifically, the post-layout simulation results also take into account the effects of the parasitic R&C and the coupling capacitance (CC). Additionally, due to the use of techniques suitable for reducing parasitics and the use of parasitic models in the design, the corresponding schematic results did not deviate from the layout results. The implemented LDO regulator is tested for all processes (TT, FF, SS, FS, SF), voltage (0.8 V, 0.9 V, 1 V) and temperature (−25 °C, 27 °C, 125 °C). During the simulation design process, various problems arose, but in this paper, the two main difficulties will be addressed. While the temperature of the environment is decreasing, the threshold voltage of the transistors Vth is increasing rapidly. So, it is very difficult to bias the pass transistor and the current mirrors in the cold corner variations (−25 °C) of the designer to increase the size of these transistors and consume some valuable chip area, but the area saved by lowering the compensation capacitance is much more optimal. The second main problem for the designer is to properly choose the bias current for the first stage in order to minimize the noise of the circuit while maintaining excellent stability performance. The results of the performance parameters are summarized in

Table 2. Performance results.

Parameter	Min	Typ	Max
Supply voltage (V)	$0.9$	1	$1.1$
Regulated output voltage (mV)	$599.5$	600	$600.2$
PSRR@DC (dB)	$50.36$	$85.76$	$94.57$
PSRR@100kHz (dB)	$49.75$	$69.94$	$73.51$
PSRR@1MHz (dB)	$34.44$	$51.19$	$54.18$
Worst PSRR (dB)	$17.26$	$18.00$	$21.41$
Output noise@1Hz (dBV/$\sqrt{\mathrm{Hz}}$)	$101.23$	$104.58$	$105.99$
Output noise@1kHz (dBV/$\sqrt{\mathrm{Hz}}$)	$132.86$	$135.15$	$136.25$
Output noise@10kHz (dBV/$\sqrt{\mathrm{Hz}}$)	$141.86$	$144.27$	$154.33$
Output noise@100kHz (dBV/$\sqrt{\mathrm{Hz}}$)	$147.96$	$151.94$	$153.08$
Output noise@1MHz (dBV/$\sqrt{\mathrm{Hz}}$)	$149.82$	$155.74$	$157.17$
DC gain (dB)	$47.89$	$82.83$	$90.98$
Phase margin ${(}^{\circ })$	$75.52$	$79.90$	$143.6$
Unity gain frequency (MHz)	$3.33$	$6.03$	$7.77$

, where the column ‘Typ’ refers to the nominal corner case (TT, $V_{DD}$ = 1 V, 27 °C), while the other two columns, ‘Min’ and ‘Max’, refer to the lowest and highest values of each index as these are evaluated after the simulations. The load condition for the simulation is $I_{load}$ = 200 μA $\left|\right|$$C_{load}$ = 300 pF.

The PSRR response on the various corner cases is depicted in Figure 6. It is quite obvious that, in most cases, the DC PSRR value is quite high (over 80 dB), while the “peak” of the PSRR is always over 18 dB. The main benefit of this implementation is the outstanding stability performance. Based on the measurement results, the LDO regulator is verified to be stable and robust over PVT corner variations with the phase margin always over 75°, while maintaining a relatively high bandwidth due to the fact that the unity gain frequency is over 3 MHz. The trend in the simulations results is that the best performance is achieved in the FF, 125 °C, 1.2 V corner variation, while the worst performance is in the SS, −25 °C, 0.9 V corner variation.The above goals were achieved using an on-chip capacitor with a capacitance of only 2 pF, which saves valuable chip area and highlights the value of the multiloop compensation technique, which improves the spectacular Miller compensation technique. Lastly, Figure 7 depicts the noise response of the LDO regulator, which seems almost unaffected over the PVT corner variations, but is strongly dependent on the compensation.

5. Comparison and Discussion

In this section, the proposed architecture is compared with other related LDO regulators that utilize alternative techniques. In

Table 3. Comparison table.

	Process	Supply Voltage	Load Conditions	DC PSRR
This work	90 nm	1 V	$I_{load}$ = 200 $\mathsf{\mu }$A $\left|\right|$$C_{load}$ = 300 pF	85 dB
[21]	65 nm	$1.2$ V	$I_{load}$ = 20 mA $\left|\right|$$R_{load}$ = 100 $\Omega$	92 dB
[22]	130 nm	$1.2$ V	$I_{load}$ = 50 mA $\left|\right|$$C_{load}$ = 4.7 $\mathsf{\mu }$F	46 dB
[40]	130 nm	1.15–1.8 V	$I_{load}$ = 50 $\mathsf{\mu }$A $\left|\right|$$C_{load}$ = 400 pF	80 dB
[41]	65 nm	$1.2$ V	$I_{load}$ = 100 $\mathsf{\mu }$A $\left|\right|$$C_{load}$ = 240 pF	70 dB
[42]	180 nm	$1.8$ V	$I_{load}$ = 50 mA $\left|\right|$$C_{load}$ = 100 pF	62 dB

and

Table 4. Comparison table. * the stability is affected by the size of the $C_c$ capacitor.

	Phase Margin	UGBW	Power Consumption	Estimated Area
This work	79.9°	6 MHz	95 $\mathsf{\mu }$W	0.034 mm2
[21]	*	*	462 $\mathsf{\mu }$W	0.092 mm2
[22]	*	*	78 $\mathsf{\mu }$W	0.4 mm2
[40]	53°	$1.65$ MHz	32.4 $\mathsf{\mu }$W	0.049 mm2
[41]	40°	40 MHz	$N/A$	0.087 mm2
[42]	50°	1 MHz	144 $\mathsf{\mu }$W	0.14 mm2

, the architecture is compared in terms of the typical metrics, which are the necessary variables of merit when designing an LDO. In general, the supply voltage is a critical specification, along with the PSRR metric. The most important metric is the stability of the system, since without it, the system will always be unstable and would not operate properly in all other metrics.

Specifically, the proposed architecture outperforms the other architectures in terms of stability while maintaining a relatively low power consumption (less than 100 μW). The multiloop technique provides a very robust design with high stability metrics (the highest value in terms of the phase margin) without the need for a compensation capacitor of high capacitance and power-hungry design, saving valuable chip area and energy. Despite the fact that the unity gain bandwidth is quite high (around 6 MHz), the stability performance is almost unaffected. Additionally the DC PSRR metric is at very high levels—approximately 85 dB in the nominal case. Lastly, the supply voltage has been dropped down to 1 V, which makes the proposed architecture suitable for low-voltage supply applications.

6. Conclusions

This work introduced an analog integrated low-power multiloop stabilized LDO regulator for low-voltage and low-power applications. It comprises a multiloop error amplifier, a native pass-transistor and a resistor used as a feedback network. The proposed architecture was designed and tested in the TSMC 90 nm CMOS process. Post-layout simulations were conducted, which confirmed the proper operation of the circuit over PVT variations. The architecture proved to be stable and robust over all variations, with a phase margin always over 75°. Valuable chip area was saved by using a compensation capacitor of only 2 pF, which highlights the value of the multiloop compensation technique. It is obvious that various techniques could be developed to further improve the performance of the LDO regulator. In future research, a combination of an LDO regulator along with a BGR circuit which uses the multiloop compensation technique presented in this paper would be possible to be implemented.