Analysis of Power Electronic Traction Transformer under Non-Single Frequency PWM Control

Abstract

In the context of locomotive traction systems, the power electronic traction transformer (PETT) represents a pivotal component, fulfilling essential functions pertaining to electrical isolation and power control. The majority of existing PETT prototypes employ a combination of a cascade structure and an ISOP structure. The aforementioned scheme effectively reduces the voltage withstand level of the power devices on the input side, yet it also necessitates the utilisation of a greater number of power devices and passive components within the PETT. In order to further reduce the number of power devices used, this paper proposes a new cascaded PETT design. The proposed PETT will adopt a scheme combining a cascade structure and a hardware circuit multiplexing. This paper first analyses the operation principle of the new circuit under non-single frequency PWM control. It then derives the design equations for some hardware parameters and control circuits. Finally, it verifies the effectiveness of the proposed PETT through simulation analysis.

1. Introduction

The power electronic traction transformer (PETT) is regarded as a potential alternative to conventional transformers in locomotive traction systems, offering a number of advantages [1]. These include a reduction in weight and size, enhanced efficiency, and a lower injection of current harmonics into the grid. In 2012, the world’s inaugural PETT for locomotives was developed and deployed by ABB in conjunction with Swiss Federal Railways [2,3]. This was followed by a series of comprehensive investigations into the potential of PETT, involving numerous research organisations worldwide, such as ABB [4,5,6], Alstom [7], Bombardier [8], Siemens [9], etc. These studies led to the development of PETT prototypes and proof-of-concept machines in various forms.

The cascaded PETT has become a typical circuit structure for PETT design [10,11,12,13,14,15,16], and a detailed illustration of the specific circuit topology can be found in Figure 1. The PETT illustrated in Figure 1 can be regarded as a combination of a cascaded multilevel AC/DC converter and an isolated DC/DC converter. The input side of the AC/DC converter is connected to the AC traction grid, whereby the AC input is converted into a medium-voltage DC voltage. The DC/DC converter achieves electrical isolation while increasing the frequency of the transformer’s transmission voltage, which will result in a significant reduction in the size and weight of the on-board transformer. Furthermore, the incorporation of controllable power devices enhances the intelligence of the locomotive.

As the AC/DC converter is directly linked to the traction network (15 kV/16.7 Hz), the objective is to limit the number of switching devices and reduce the voltage withstand level of these components. In order to achieve this, it is necessary to utilise a CHB structure with 6.5 kV IGBT modules. In order to further reduce the losses in the circuit, the DC/DC converter can be designed as a resonant converter [17,18,19,20,21]. The resonant cavity, which encompasses L-type, LC-type, and LLC-type configurations, guarantees the zero-current and zero-voltage conduction of the power devices within the DC/DC converter.

In order to further reduce the number of power devices employed, a novel PETT is designed in this paper, and the specific circuit structure is shown in Figure 2. In the proposed PETT, the number of power units is N_s. The PETT has the following characteristics:

(i)

Each power unit is an AC/DC converter and contains a medium-frequency transformer (MFT). The principal aspect of the MFT is constituted by a series of cascaded H-bridge modules, which function as alternating current AC/DC converters. The number of H-bridge modules in this configuration is designated as N. On the secondary side of the MFT, one H-bridge module is employed as an AC/DC converter.

(ii)

The two power units collectively constitute a unit group, and there is a distinction between the control signals of these two power units, which will be elucidated subsequently.

(iii)

With regard to feature 2, it is necessary for the number of power units in the PETT to be even.

The proposed circuit employs a reduced number of switching devices and capacitors in comparison to the conventional circuit illustrated in Figure 1, while maintaining the same input size. This allows for the low-cost design of PETTs. Consequently, novel circuitry offers substantial benefits in terms of reducing the size of PETTs and increasing their power density. The proposed circuit employs a reduced number of switching devices in comparison to the same type of circuit, presented in [22], for the same size of input. In comparison to same type of circuit, outlined in [23], the proposed circuit employs multiple low-voltage-level and low-capacity MFTs in lieu of a single high-voltage and high-capacity MFT. This results in a reduction in the voltage level and capacity of a single MFT, which facilitates the modular and redundant design of PETTs. In comparison with the same type of circuit, presented in [24], the proposed circuit employs a multi-frequency modulation strategy, which involves a more straightforward control methodology and is more straightforward to implement.

The prevailing design of on-board PETTs still belongs to the multistage conversion type of converter, which requires a large number of active devices and therefore reduces the power density and increases the manufacturing costs. Simplifying the conversion process of PETT is an effective way to improve the power density. In this paper, the method of multi-frequency modulation enables the bridge arm of the CHB circuit to output a fundamental-frequency AC voltage as well as a high-frequency AC voltage, which in turn reduces the number of stages of the power conversion and can effectively reduce the number of components involved and improve the power density. It is valuable in terms of reducing the cost and volume of multilevel PETTs, promoting the development of PETTs, and accelerating the construction of intelligent locomotive traction systems.

2. Analysis of the Proposed PETT

2.1. Analysis of the Working Principle

The H-bridge circuit represents the fundamental circuit structure of PETTs, and an analysis of this circuit is beneficial in terms of researching PETTs. In the case of the H-bridge circuit, under PWM control, the frequency and waveform of the AC-side voltage are in accordance with a modulating waveform [25,26]. The following section will examine the output law of the H-bridge circuit under PWM control, utilising two modulating waves with disparate frequencies and waveforms as illustrative examples. For the purposes of this discussion, the two modulating waves will be denoted as u_r1 and u_r2. The following assumptions will be made:

(i)

The modulating waveform u_r1 will be taken to be sinusoidal, with frequency f₁.

(ii)

The modulating waveform u_r2 will be taken to be a square wave, with frequency f₂.

In accordance with the aforementioned assumptions, the AC-side voltage of the H-bridge circuit can be decomposed into a sinusoidal voltage component and a square-wave voltage component. For the purposes of discussion, the aforementioned voltage components are henceforth designated u_f1 and u_f2, respectively. It is possible to decouple u_f1 and u_f2 and subsequently transmit them independently through the filter circuit due to their differing frequencies. The aforementioned concept may be employed in the redesign of the PETT circuit, illustrated in Figure 1. This entails the replacement of the two series-connected H-bridges on the primary side of the MFT with a single H-bridge, thereby yielding the novel PETT circuit depicted in Figure 2.

The following clarification is provided for the sake of clarity and exposition. In the proposed PETT, the H-bridge on the primary side of the MFT is designated as H₁, and the H-bridge on the secondary side is designated as H₂. H₁ is responsible for implementing the AC/DC converter, while also forming a DC/DC converter with the MFT and H₂. Furthermore, the f₂ should be sufficiently high to provide a high-frequency square-wave voltage on the primary side of the MFT. It can be stated that the multiplexing of the H-bridge circuit is achieved through the utilisation of multi-frequency PWM control, which represents the operational principle of the proposed PETT. It is assumed that the hardware parameters of the cascade sub-modules in Figure 2b are identical and that the switching devices are numbered in accordance with the circuit depicted in Figure 2. It is evident that H₁ comprises switching devices V₁~V₄ and capacitor C_sm, while H₂ is constituted by switching devices S₁~S₄ and capacitor C_dc.

The different polarities of the modulating waves allow for the classification of PWM control into unipolar and bipolar types. Each of these control methods possesses distinct advantages and disadvantages, which are contingent upon the specific application. In the case of unipolar PWM control, the AC side of the H-bridge is capable of outputting positive, negative, and neutral levels. In the case of bipolar PWM control, the H-bridge AC side outputs positive and negative levels. It is important to note that the equivalent switching frequency of unipolar PWM control is twice that of bipolar PWM modulation. Consequently, it is possible to reduce switching losses while simultaneously reducing the total harmonic distortion (THD) of the H-bridge AC-side voltage, which in turn leads to a reduction in the fluctuations in the AC-side input current. In light of the benefits associated with unipolar PWM control, this paper proposes the implementation of unipolar PWM control as the control strategy for PETTs.

Table 1. Switching combinations of H₁ under unipolar PWM control.

Modal	Switching Device				uab
	V1	V2	V3	V4
1	0	1	0	1	0
2	0	1	1	0	−usm
3	1	0	0	1	usm
4	1	0	1	0	0

illustrates the complete set of switching combinations for V₁~V₄ under unipolar modulation. Here, a switching signal of “0” indicates that the device is in an off state, while a switching signal of “1” denotes that the device is in an on state. At this time, H1 exhibits the following characteristics:

(i)

At u_ab > 0, the value of u_ab will switch between u_sm and 0, where u_sm is the voltage of the capacitor C_sm on the DC side of H₁.

(ii)

At u_ab < 0, the value of u_ab will switch between −u_sm and 0.

One possible PWM strategy for realising the switching combinations demonstrated in Table 1 is given in Figure 3, and several important waveforms relevant to this strategy are given.

The introduction of a three-valued logic switching function, δ, with δ = V₁ − V₃, allows the voltage uab and the DC-side current i_sm of H₁ to be expressed in terms of the switching function as

$$\left\{\begin{array}{l}{u}_{ab}=\delta u_{sm}\\ i_{sm}=\delta i_{ab}\end{array}\right.,$$

(1)

where i_ab is the base wave current on the AC side of H₁.

The non-single frequency modulation strategy adopted in this paper allows for the decomposition of the voltage u_ab into a sinusoidal AC component u_f1 and a square-wave AC component u_f2. The corresponding switching functions, designated as δ_f1 and δ_f2, respectively, enable the expression of the voltage component of uab and the DC-side current ism as

$$\left\{\begin{array}{l}{u}_{f1}={\delta }_{f1}{u}_{sm}\\ u_{f2}={\delta }_{f2}{u}_{sm}\\ i_{sm}={\delta }_{f1}{i}_g-{\delta }_{f2}{i}_r\end{array}\right.,$$

(2)

where i_g is the grid current at the network side and i_r is the resonant current of the LC resonant circui.

Figure 4 depicts a partially enlarged representation of Figure 3b for u_ab ≥ 0. It is assumed that the frequency of the triangular carrier u_c is f_s and that its peak value is U_cm. The rms value of u_sm is denoted as U_sm, and it is that U_cm = U_sm. If the modulation ratio of the modulating wave u_r1 is m₁, the modulating wave u_r1 can be expressed as u_r1 = m₁U_smsinω₁t.

Figure 4 illustrates the relationship between the on-time ton of switch V₁ and the period T_s of the carrier wave. Based on the similarity of triangles, T_on satisfies the following relationship with T_s:

$${\displaystyle \frac{T_{\mathrm{on}}}{T_{\mathrm{s}}}}={\displaystyle \frac{U_{cm}+m_1{U}_{sm}\sin {\omega }_{1}t}{2U_{cm}}},$$

(3)

The duty cycle function of the switch V₁ when employing u_r1 modulation is represented as d_f1(V₁). By employing Equation (3), it is possible to derive the following equation: d_f1(V₁) = 0.5 + 0.5m₁sinω₁t. Similarly, the duty cycle function of the switch V₃ is represented as follows: d_f1(V₃) = 0.5 − 0.5m₁siω₁t. If the duty cycle function corresponding to the switching function δf1 is denoted as d_f1, it can be expressed as d_f1 = m₁sinω₁t.

If the modulation ratio of the modulating wave u_r2 is m₂, the modulating wave u_r2 can be expressed as

$$u_{r2}=m_2{U}_{sm}{\displaystyle \sum _{j=1}^{\infty }\frac{4}{j\pi }\sin \left(j{\omega }_{2}t\right)},$$

(4)

where j is an odd number.

In the context of u_r2 modulation, the duty cycle functions of the switch V₁ and V₃ are designated as d_f2(V₁) and d_f2(V₃), respectively. By means of Equations (3) and (4), the following can be obtained:

$$\left\{\begin{array}{l}{d}_{f2}\left(V_1\right)=0.5+0.5m_2{\displaystyle \sum _{j=1}^{\infty }\frac{4}{j\pi }\sin \left(j{\omega }_{2}t\right)}\\ d_{f2}\left(V_3\right)=0.5-0.5m_2{\displaystyle \sum _{j=1}^{\infty }\frac{4}{j\pi }\sin \left(j{\omega }_{2}t\right)}\end{array}\right.,$$

(5)

The duty cycle function corresponding to the switching function δ_f2 is designated as d_f2. This can be obtained through Equation (5):

$$d_{f2}=m_2{\displaystyle \sum _{j=1}^{\infty }\frac{4}{j\pi }\sin \left(j{\omega }_{2}t\right)},$$

(6)

In this paper, open-loop control is used to control H₂, and the on/off switching devices S₁~S₄ are controlled by square-wave pulses with a duty cycle of 0.5.

Table 2. Switching combinations of H₂.

Modal	Switching Device				ucd
	S1	S2	S3	S4
5	1	0	0	1	udc
6	0	1	1	0	−udc

shows all the switching combinations of S₁~S₄, where a switching signal of “0” means the device is off and a switching signal of “1” means the device is on. The control process is as follows: when u_cd > 0, S₁ and S₄ are on; when u_cd < 0, S₂ and S₃ are on.

The introduction of a three-valued logic switching function, σ, with σ = 2S₁ − 1, allows the voltage ucd and the DC-side current idc of H₂ to be expressed in terms of the switching function as

$$\left\{\begin{array}{l}{u}_{cd}=\sigma u_{dc}\\ i_{dc}=\sigma i_{cd}\end{array}\right.,$$

(7)

where i_cd is the base wave current on the AC side of H₂.

If the ratio of the MFT is represented by the symbol N_T, then the voltage and current on the primary and secondary sides of the MFT are satisfied:

$$\left\{\begin{array}{l}N{\delta }_{f2}{u}_{sm}=N_T\sigma u_{dc}\\ i_{dc}=N_T\sigma i_r\end{array}\right.,$$

(8)

If the duty cycle function corresponding to the switching function σ is represented by the symbol D, this is expressed as follows:

$$D={\displaystyle \sum _{j=1}^{\infty }\frac{4}{j\pi }\sin \left(j{\omega }_{2}t\right)},$$

(9)

From Equations (6) and (9), it can be demonstrated that d_f2 = m₂D. Consequently, Equations (2) and (8) can be expressed in terms of the duty cycle function as

$$\left\{\begin{array}{l}{u}_{f1}=d_{f1}{u}_{sm}\\ u_{f2}=d_{f2}{u}_{sm}\\ i_{sm}=d_{f1}{i}_g-d_{f2}{i}_r\\ m_2{i}_{dc}=N_T{d}_{f2}{i}_r\\ m_{2}N{u}_{sm}=N_T{u}_{dc}\end{array}\right.,$$

(10)

2.2. Current Loop of the Proposed PETT

In this section, the current loop of the proposed PETT under unipolar PWM control is discussed. When e_g > 0, the modes of H₁ are mode 3 and mode 4. When the switching combination of H₁ is in mode 3, the voltage across the inductor L_s is less than 0. Depending on the direction of the current i_ab, H₁ possesses 2 current loops. Figure 5a,b illustrate the aforementioned two current loops. When the switching combination of H₁ is in mode 4, the voltage across the inductor L_s is greater than 0. At this time, the current loop of H₁ is shown in Figure 5c. The details can be analysed as follows:

In Figure 5a, i_ab < 0. At this point, the current i_ab flows into point b, through V₄, the capacitor C_sm, and V₁, and subsequently out of point a. In this process, u_ab = u_sm, and the inductor L_s stores energy. The switching combination of H₂ is in mode 5 and i_cd < 0. At this point, the current flows in from point d, through S₄, the capacitor C_dc, and S₁, and finally out from point c. In this process, u_cd = u_dc.

In Figure 5b, i_ab > 0. At this point, the current i_ab flows in from point a, through the anti-parallel diode of V₁, the capacitor C_sm, and the anti-parallel diode of V₄, and finally out from point b. The inductor L_s releases energy. In this process, u_ab = u_sm, and the inductor L_s releases energy. The switching combination of H₂ is in mode 5 and i_cd > 0. At this time, the current i_cd current flows from point c, flows through the anti-parallel diode of S₁, the capacitor C_dc, and the anti-parallel diode of S₄, and finally out from point d. In this process, u_cd = u_dc.

In Figure 5c, i_ab < 0. At this point, the current i_ab flows in from point b, flows through V₁ and the anti-parallel diode of V₃, and finally out from point a. In this process, u_ab = 0. The current loop of H₂ remains the same as in Figure 5a.

When e_g < 0, the modes of H₁ are mode 2 and mode 1. When the switching combination of H₁ is in mode 2, the voltage across the inductor L_s is greater than 0. Depending on the direction of the current i_ab, H₁ is equipped with 2 current loops. Figure 5d,e illustrate the aforementioned two current loops. When the switching combination of H₁ is in mode 1, the voltage across the inductor L_s is less than 0. At this time, the current loop of H₁ is shown in Figure 5f. The specific analyses are as follows:

In Figure 5d, i_ab > 0. At this point, the current i_ab flows in from point a, flows through V₂, the capacitor C_sm, and V₃, and finally out from point b. In this process, u_ab = −u_sm and the inductor L_s stores energy. The switching combination of H₂ is in mode 6 and i_cd > 0. At this time, i_cd flows in from point c, flows through S₂, the capacitor C_dc, and S₃, and finally flows out from point d. In this process, u_cd = −u_dc.

In Figure 5e, i_ab < 0. At this point, the current i_ab flows in from point b, flows through the anti-parallel diode of V₃, the capacitor C_sm, and the anti-parallel diode of V₂, and finally flows out from point a. In this process, u_ab = −u_sm, and the inductor L_s releases energy. The switching combination of H₂ is in mode 6 and i_cd < 0. At this point, the current i_cd flows from point d, through the anti-parallel diode of S₃, the capacitor C_dc, and the anti-parallel diode of S₂, and finally out from point c. In this process, u_cd = −u_dc.

In Figure 5f, i_ab > 0. At this point, the current i_ab flows in from point a, flows through V₄ and the anti-parallel diodes of V₂, and finally flows out from point b. In this process, uab = 0. The current loop of H₂ remains the same as it is in Figure 5d.

2.3. Mathematical Modelling of the Proposed PETT

The equivalent circuit of the proposed PETT is shown in Figure 6, where half of the power unit AC-side voltages are (Nu_f1 + Nu_f2) and the other half of the power unit AC-side voltages are (Nu_f1 − Nu_f2). The loop 1 in Figure 6 is analysed and the KVL equation is written as follows:

$$e_g-r_s{i}_g-L_{\mathrm{s}}{\displaystyle \frac{d}{dt}}{i}_g-N_{s}N{u}_{f1}=0,$$

(11)

where e_g is the traction grid voltage, i_g is the grid input current, Ls is the grid-side filter inductance, N_s is the number of power units, N is the number of sub-modules inside a single power unit, and u_f1 is the voltage component of the sub-module AC-side voltage with frequency f₁.

Let us assume that the grid voltage e_g is e_g = E_msinω₁t and the voltage component u_f1 is u_f1 = E_m1sinω₁t. From Equation (11), the first-order linear differential equation can be obtained as follows:

$${i^{\prime }}_g\left(t\right)+{\displaystyle \frac{r_s}{L_{\mathrm{s}}}}{i}_g\left(t\right)={\displaystyle \frac{E_m-E_{m1}}{L_{\mathrm{s}}}}\sin \left({\omega }_{1}t\right),$$

(12)

The solution to Equation (12) is as follows:

$$i_g\left(t\right)={\displaystyle \frac{E_m-E_{m1}}{r_s^2+{\omega }_1^2{L}_s^2}}\left(r_s\sin {\omega }_{1}t-L_s\cos {\omega }_{1}t\right)+c_1{e}^{-{\displaystyle \frac{r_s}{L_s}}t},$$

(13)

Considering i_g(t = 0) = 0, the value of the constant c₁ in Equation (13) can be obtained. Also, the phase angle φ₁ is introduced and satisfied:

$$\left\{\begin{array}{l}\sin {\phi }_1={\displaystyle \frac{r_s}{\sqrt{r_s^2+{\omega }_1^2{L}_s^2}}}\\ \cos {\phi }_1={\displaystyle \frac{{\omega }_1{L}_{\mathrm{s}}}{\sqrt{r_s^2+{\omega }_1^2{L}_s^2}}}\end{array}\right.,$$

(14)

From the preceding analysis, it can be inferred that

$$i_g\left(t\right)={\displaystyle \frac{E_m-N_{s}N{E}_{m1}}{\sqrt{r_s^2+{\omega }_1^2{L}_s^2}}}\sin \left({\omega }_{1}t-{\phi }_1\right)+{\displaystyle \frac{E_m-E_{m1}}{r_s^2+{\omega }_1^2{L}_s^2}}{L}_s{e}^{-{\displaystyle \frac{r_s}{L_s}}t},$$

(15)

Equation (15) shows that the steady-state current of i_g does not contain the harmonics associated with f₂, and the current i_g can be expressed as i_g = I_msin(ω₁ − φ₁).

The loop 2 in Figure 6 is analysed and the KVL equation is written as

$$N{u}_{f1}+N{u}_{f2}-L_{\mathrm{r}}{\displaystyle \frac{d}{dt}}{i}_r-u_{cr}-u_T=0,$$

(16)

where u_T is the primary-side voltage of MFT.

Since the resonant frequency of the LC resonant circuit is the same as that of u_f2, then L_r and C_r satisfy L_rC_r = 1/ω₂. The following can be obtained:

$$\left\{\begin{array}{l}N{u}_{f1}-L_{\mathrm{r}}{\displaystyle \frac{d}{dt}}{i}_r-u_{cr}=0\\ N{u}_{f2}-u_T=0\end{array}\right.,$$

(17)

The second-order linear differential equation can be obtained from (17):

$${u^{″}}_{cr}\left(t\right)+{\displaystyle \frac{1}{L_{\mathrm{r}}{C}_{\mathrm{r}}}}{u}_{cr}\left(t\right)={\displaystyle \frac{N{E}_{m1}}{L_{\mathrm{r}}{C}_{\mathrm{r}}}}\sin \left({\omega }_{1}t\right),$$

(18)

The solution to Equation (12) is as follows:

$$u_{cr}\left(t\right)=c_2\sin \left({\omega }_{2}t\right)+c_3\cos \left({\omega }_{2}t\right)+{\displaystyle \frac{{\omega }_1^2}{{\omega }_2^2-{\omega }_1^2}}N{E}_{m1}\sin \left({\omega }_{1}t\right),$$

(19)

The derivative operation on Equation (19) gives the current of the LC filter circuit as

$$i_{r1}\left(t\right)=c_2{\omega }_2{C}_r\cos \left({\omega }_{2}t\right)-c_3{\omega }_2{C}_r\sin \left({\omega }_{2}t\right)+{\displaystyle \frac{{\omega }_1^3}{{\omega }_2^2-{\omega }_1^2}}N{E}_{m1}{C}_r\cos \left({\omega }_{1}t\right),$$

(20)

Considering i_r(t = 0) = 0, the value of the constant c₂ in Equation (20) can be determined. Upon the substitution of this value into Equation (20), the result is as follows:

$$i_{r1}\left(t\right)=-{\displaystyle \frac{{\omega }_1^3}{{\omega }_2^2-{\omega }_1^2}}N{E}_{m1}{C}_r\cos \left({\omega }_{2}t\right)-c_3{\omega }_2{C}_r\sin \left({\omega }_{2}t\right)+{\displaystyle \frac{{\omega }_1^3}{{\omega }_2^2-{\omega }_1^2}}N{E}_{m1}{C}_r\cos \left({\omega }_{1}t\right),$$

(21)

Equation (21) shows that the LC filter current contains harmonics related to f₂. However, in the actual design, when the angular frequency ω₂ is much larger than ω₁, and the smaller C_r is selected as the filter capacitor, the coefficients of the first and third terms on the right side of the middle equation of Equation (20) are smaller, and the maximum or minimum value of the current ir can then be considered to be I_rm = |c₃|ω₂C_r. Considering that the maximum transmitted power satisfies P_m = 0.5E_mI_m = 0.5N_sNE_m2I_rm, the value of the constant c₃ can be obtained. Upon the substitution of this value into Equation (21), the result is as follows:

$$i_{r1}\left(t\right)={\displaystyle \frac{E_m{I}_m}{N_{s}N{E}_{m2}}}\sin \left({\omega }_{2}t\right)+{\displaystyle \frac{{\omega }_1^3}{{\omega }_2^2-{\omega }_1^2}}N{E}_{m1}{C}_r\left[\cos \left({\omega }_{2}t\right)-\cos \left({\omega }_{1}t\right)\right],$$

(22)

Similarly, an examination of the analysis of loop 3 in Figure 6 reveals that

$$i_{r2}\left(t\right)=-{\displaystyle \frac{E_m{I}_m}{N_{s}N{E}_{m2}}}\sin \left({\omega }_{2}t\right)+{\displaystyle \frac{{\omega }_1^3}{{\omega }_2^2-{\omega }_1^2}}N{E}_{m1}{C}_r\left[\cos \left({\omega }_{2}t\right)-\cos \left({\omega }_{1}t\right)\right],$$

(23)

The presence of time-varying AC quantities in the mathematical model obtained is not favourable for control system design. It is also necessary to transform it into a mathematical model in the dq coordinate system by means of coordinate transformation. For single-phase systems, a virtual orthogonal component must be constructed when performing coordinate transformation. In this paper, we will construct the virtual β-axis orthogonal to the α-axis by delaying a quarter cycle, then construct the αβ coordinate system, and finally complete the construction of the dq coordinate system.

The mathematical model of the proposed PETT in the coordinate system of the dq coordinate system is as follows:

$$\left\{\begin{array}{l}{L}_{\mathrm{s}}{\displaystyle \frac{d}{dt}}{i}_d+r_s{i}_d=e_d-N_{s}N{d}_d{u}_{sm}+{\omega }_1{L}_s{i}_q\\ L_{\mathrm{s}}{\displaystyle \frac{d}{dt}}{i}_q+r_s{i}_q=e_q-N_{s}N{d}_q{u}_{sm}-{\omega }_1{L}_s{i}_d\\ C_{\mathrm{sm}}{\displaystyle \frac{d}{dt}}{u}_{sm}+{\displaystyle \frac{m_2{C}_{\mathrm{dc}}}{N_T}}{\displaystyle \frac{d}{dt}}{u}_{dc}=d_{f1}{i}_g-{\displaystyle \frac{m_2{u}_{dc}}{N_T{R}_{eq}}}\end{array}\right.,$$

(24)

where R_eq is the equivalent load of a single power unit, R_eq = R_L/N_s.

3. Control Strategy of the Proposed PETT

In the field of PWM converter control, the double closed-loop strategy is a well-established approach that offers the benefits of a rapid dynamic response and high interference immunity [27,28,29,30,31]. Typically, this strategy comprises voltage outer-loop control and current inner-loop control. For the PETT circuit under consideration, the double closed-loop control represents a straightforward and effective control strategy.

3.1. Analyse of the Current Inner-Loop Control System

The present loop control circuit is designed in accordance with the specifications set forth in Equation (24). Given the symmetry between the i_q current loop and the id current loop, the design method for the latter will be outlined in this section. When the PI controller is employed as the current controller and feedforward control quantities are introduced, the control equation can be designed as follows:

$$\left\{\begin{array}{c}{N}_{s}N{d}_d{u}_{sm}=e_d-{\displaystyle \frac{k_{p1}s+k_{i1}}{s}}\left(i_d^{\ast }-i_d\right)+{\omega }_1{L}_s{i}_q\\ N_{s}N{d}_q{u}_{sm}=e_q-{\displaystyle \frac{k_{p1}s+k_{i1}}{s}}\left(i_q^{\ast }-i_q\right)-{\omega }_1{L}_s{i}_d\end{array}\right.,$$

(25)

where k_p1 and k_i1 are the proportional and integral regulation gains of the current controller, respectively; i_d* is the command value of the current i_d; i_q* is the command value of the current i_q; and the third term on the right side of the equation is the feed-forward control quantity.

The current loop, illustrated in Figure 7, is constructed in accordance with Equation (25). In Figure 7, G₁(s) is the transfer function of the id current controller. G₂(s) is the transfer function of the H-bridge converter under PWM control. G₃(s) is the open-loop transfer function of the system unit. The specific expression for the aforementioned transfer functions is as follows:

$$\left\{\begin{array}{l}{G}_1(s)=k_{p1}+{\displaystyle \frac{k_{i1}}{s}}\\ G_2(s)={\displaystyle \frac{1}{T_{i}s+1}}\\ G_3(s)={\displaystyle \frac{1}{s{L}_s+r_s}}\end{array}\right.,$$

(26)

where T_i is the sampling period of the current loop and is the same as the switching period T_s, meaning that T_i = T_s.

In the absence of the consideration of e_d, the open-loop transfer function of the i_d current loop can be expressed as follows:

$$F_1(s)={\displaystyle \frac{N_{s}N}{r_s}}{\displaystyle \frac{k_{i1}}{s}}\left({\displaystyle \frac{1}{T_{i}s+1}}\right)\left({\displaystyle \frac{k_{p1}}{k_{i1}}}s+1\right){\displaystyle \frac{1}{\left(\frac{L_s}{r_s}s+1\right)}},$$

(27)

Equation (27) shows that the id current loop comprises two poles, namely, s₁= −1/T_i and s₂ = −L_s/r_s. In the majority of cases, the main pole is identified as s₂ due to the considerable value of f_i. In order to achieve a faster response, it is possible to utilise the controller’s zeros in order to offset s₂. This can be achieved by setting k_p1/k_i1 = L_s/r_s. At this juncture, the switching function F₁(s) is as follows:

$$F_1(s)={\displaystyle \frac{N_{s}N{k}_{i1}}{r_s}}{\displaystyle \frac{1}{s\left(T_{i}s+1\right)}},$$

(28)

Then, the closed loop transfer function of the id current loop is as follows:

$$G_i(s)={\displaystyle \frac{N_{s}N{k}_{i1}}{r_s{T}_i{s}^2+r_{s}s+N_{s}N{k}_{i1}}},$$

(29)

3.2. Analysis of the Voltage Outer-Loop Control System

The present loop control voltage is designed in accordance with the specifications set forth in (24). When the PI controller is employed as the voltage controller, the control equation can be designed as

$$d_{f1}{i}_g={\displaystyle \frac{k_{p2}s+k_{i2}}{s}}\left(u_{sm}^{\ast }-u_{sm}\right)+{\displaystyle \frac{m_2}{N_T}}{\displaystyle \frac{k_{p3}s+k_{i3}}{s}}\left(u_{dc}^{\ast }-u_{dc}\right),$$

(30)

where k_p2 and k_i2 are the proportional adjustment gain and integral adjustment gain of the voltage u_sm controller; k_p3 and k_i3 are the proportional adjustment gain and integral adjustment gain of the voltage u_dc controller; u_sm* is the command value of the voltage u_sm; and u_dc* is the command value of the voltage u_dc.

Considering the preceding analysis, it can be assumed that i_g = I_msin(ω₁t − φ₁) and i_r = I_rmsinω₂t. With regard to the DC-side fundamental wave and double frequency fluctuation, the DC-side current component of H₁ can be expressed as follows:

$$d_{f1}{i}_g=0.5m_1{I}_m\cos {\phi }_1-0.5m_1{I}_m\cos \left(2{\omega }_{1}t-{\phi }_1\right),$$

(31)

$$\begin{array}{cc}\hfill d_{f2}{i}_r=& {\displaystyle \frac{2}{\pi }}{m}_2{I}_{rm}-{\displaystyle \frac{2}{\pi }}{m}_2{I}_{rm}\cos \left(2{\omega }_{2}t\right)\hfill \\ & +{\displaystyle \frac{1}{2}}{m}_2{I}_{rm}{\displaystyle \sum _{j=3}^{\infty }\left\{\left.\frac{4}{j\pi }\left[\cos \left(j{\omega }_{2}t-{\omega }_{2}t\right)-\cos \left(j{\omega }_{2}t+{\omega }_{2}t\right)\right]\right\}\right.}\hfill \end{array},$$

(32)

The voltage loop, illustrated in Figure 8, is constructed in accordance with Equation (30). In Figure 8, G₄(s) and G₆(s) are the transfer functions of the u_sm voltage controller and the udc voltage controller, respectively. G₅(s), G₇(s), and G₈(s) are the open-loop transfer functions of the system devices. The specific expression for the aforementioned transfer functions is as follows:

$$\left\{\begin{array}{l}{G}_4(s)=k_{p2}+{\displaystyle \frac{k_{i2}}{s}}\\ G_5(s)={\displaystyle \frac{1}{s{C}_{sm}}}\\ G_6(s)=k_{p3}+{\displaystyle \frac{k_{i3}}{s}}\\ G_7(s)={\displaystyle \frac{1}{L_r{C}_r{s}^2+1}}\\ G_8(s)={\displaystyle \frac{1}{s{C}_r}}\end{array}\right.,$$

(33)

As illustrated in Figure 8, both Equations (31) and (32) are time-varying links. This introduces challenges in the design of the voltage loop, which can be addressed by considering the maximum proportional gain of the link as a potential replacement. In the absence of the consideration of the e_d, the equivalent structure diagram, as illustrated in Figure 9, is obtained through the simplification of the control structure diagram, as shown in Figure 8. This is achieved through the combination of comparison points, the shifting of the lead point backwards, and the application of series equivalence and parallel equivalence.

In Figure 9, the specific expression of G₉(s) is as follows:

$$G_9(s)=0.5m_1-0.64m_2{\displaystyle \frac{G_7(s)G_8(s)}{NsN{G}_3(s)}},$$

(34)

When u_dc* = 0, the open-loop transfer function between the input signal u_sm* and the output signal u_sm can be obtained as follows

$$F_2(s)={\displaystyle \frac{G_4(s)G_i(s)G_9(s)G_5(s)}{1+\frac{m_2^{2}N}{N_T^2}{G}_6(s)G_i(s)G_9(s)G_5(s)}},$$

(35)

When u_sm* = 0, the open-loop transfer function between the input signal u_dc* and the output signal u_sm can be obtained as follows

$$F_3(s)={\displaystyle \frac{m_2{G}_6(s)G_i(s)G_9(s)G_5(s)}{N_T+N_T{G}_4(s)G_i(s)G_9(s)G_5(s)}},$$

(36)

3.3. Integrated Control Strategy

In summary, the overall control block diagram of the proposed PETT is presented in Figure 10. The voltage control loop employs PI controllers, while the control voltages u_sm and u_dc adhere to the prescribed values of u_sm* and u_dc*, respectively. The outputs of the aforementioned controllers are employed as inputs to the current loop following the implementation of requisite arithmetic operations. Subsequently, the modulating signal waveform, designated as d_f1, is generated following the completion of the current loop and coordinate transformation. The values of m₂ are then obtained through the operation of u_sm* and u_dc*. This, in turn, generates the aforementioned modulating signal waveform, designated as d_f2. Subsequently, the aforementioned two modulating signals (d_f1 and d_f2) are superimposed, whereupon PWM modulation is performed. The resulting output is the control signal for H₁. In conclusion, a fixed-frequency square-wave pulse is employed as the control signal for H₂.

The extensive use of power electronic equipment will inevitably result in an increase in the total harmonic distortion (THD) of the incoming current. Improvements in THD can be achieved through the optimisation of the topology, the enhancement of the hardware performance, and the optimisation of the control algorithm, with the objective of ensuring the power quality. When the proposed PETT adopts the control strategy shown in Figure 10, the PWM control can be combined with the selective harmonic elimination (SHE) technique to eliminate the lower harmonics and reduce the THD value under the traditional PWM control while also ensuring the fundamental amplitude. This method necessitates only minimal alterations to the control circuit and is straightforward to implement. Furthermore, the introduction of a harmonic compensator can serve to mitigate the effects of harmonic currents. By rotating the positive-sequence component of the kth harmonic by kω1 while the negative-sequence component rotates by −kω1, a mathematical model of the controlled object in the kth harmonic rotating coordinate system is obtained. This model is then used to design the parameters of the harmonic compensator. This scheme necessitates a significant alteration to the control circuit. As the improvement of the THD is not the primary objective of this study, a detailed examination of this topic is not provided here.

3.4. Loss Analysis of the Proposed PETT

A reasonable loss analysis constitutes an essential component of the converter design process. Calculating the power loss of the converter and subsequently predicting the efficiency of the converter facilitates the subsequent optimisation of the converter’s efficiency. Concurrently, forecasting the temperature distribution of the switching devices and magnetic components supports subsequent work on the thermal design of the entire machine. This section presents a discussion of the power loss, including the conduction loss and switching loss, caused by the proposed PETT switching under the control strategy illustrated in Figure 10. The discussion employs an N-channel type IGBT module as a case study.

(i)

Conduction loss

Upon the activation of the IGBT module, two distinct operational states are observed: forward conduction and reverse conduction (anti-parallel diode conduction). Figure 11 illustrates the conduction sequence of the switching devices and the current waveforms flowing through the IGBTs and diodes in H₁ under unipolar PWM control.

As illustrated in Figure 11, at each current cycle, both the IGBT and the diode are operational for only half of the cycle. Let us consider first that the conduction loss of a single IGBT when the modulating waveform is sinusoidal (frequency f₁) is as follows:

$$p_{CT,f1}={\displaystyle \frac{1}{T_{f1}}}{\displaystyle {\int }_0^{\frac{T_{f1}}{2}}{v}_{ce}(t)}{i}_{ce}(t)d_{f1}(t)dt,$$

(37)

where T_f1 is the operating period of the IGBT, d_f1(t) is the duty cycle function, i_ce(t) is the on-state current, and v_ce(t) is the on-state voltage drop. The latter is solved by the following (38):

$$v_{ce}(t)=u_{ce0}+r_{ce}{i}_{ce}(t),$$

(38)

where u_ce0 and r_ce are obtained from the IGBT output characteristic curve provided by the IGBT manufacturer.

It has been previously established that i_ce(t) = I_msin(ω₁t − φ₁) and d_f1(V₁) = 0.5 + 0.5m₁sinω₁t. Upon substituting i_ce(t) and d_f1(t) into (37) and (38), the conduction loss of a single IGBT in one operating cycle is obtained as follows:

$$p_{CT,f1}={\displaystyle \frac{u_{ce0}{I}_m}{2\pi }}+{\displaystyle \frac{r_{ce}{I}_m^2}{8}}+{\displaystyle \frac{m_1{u}_{ce0}{I}_m}{8}}+{\displaystyle \frac{m_1{r}_{ce}{I}_m^2}{3\pi }},$$

(39)

Similarly, the conduction loss of a single diode in one operating cycle is obtained as follows:

$$p_{CD,f1}={\displaystyle \frac{u_{t0}{I}_m}{2\pi }}+{\displaystyle \frac{r_t{I}_m^2}{8}}-{\displaystyle \frac{m_1{u}_{t0}{I}_m}{8}}-{\displaystyle \frac{m_1{r}_t{I}_m^2}{3\pi }},$$

(40)

where u_t0 and r_t are obtained by means of diode output characteristic curves provided by the manufacturer.

Next, let us consider the calculation of the conduction loss of a single IGBT and diode when the modulating waveform is a square wave (frequency f₂). It was previously shown that i_d(t) = I_rmsin(ω₂t). The duty cycle function is shown in Equation (5). This information can be used to determine the following:

$$p_{CT,f2}={\displaystyle \frac{u_{ce0}{I}_{rm}}{2\pi }}+{\displaystyle \frac{r_{ce}{I}_{rm}^2}{8}}+{\displaystyle \frac{m_2{u}_{ce0}{I}_{rm}}{2\pi }}+{\displaystyle \frac{m_2{r}_{ce}{I}_{rm}^2}{{\pi }^2}}{\displaystyle \sum _{j=1}\left[\frac{1}{j^2}-\frac{1}{\left(j+2\right)\left(j-2\right)}\right]},$$

(41)

$$p_{CD,f2}={\displaystyle \frac{u_{t0}{I}_{rm}}{2\pi }}+{\displaystyle \frac{r_t{I}_{rm}^2}{8}}-{\displaystyle \frac{m_2{u}_{t0}{I}_{rm}}{2\pi }}-{\displaystyle \frac{m_2{r}_t{I}_{rm}^2}{{\pi }^2}}{\displaystyle \sum _{j=1}\left[\frac{1}{j^2}-\frac{1}{\left(j+2\right)\left(j-2\right)}\right]},$$

(42)

(ii)

Switching loss

Switching loss is the loss generated during the turn-on and turn-off process of power electronic devices, including turn-on loss and turn-off loss. Switching losses can be obtained by both estimation and experimental measurement.

Approximating the switching process to be linear, the switching losses are estimated by using the voltage and current values at turn-on or turn-off, as are the rise and fall times. Alternatively, using the manuals provided by the device manufacturers, the switching losses under standard conditions are read and the switching losses are estimated based on the actual temperature, voltage, and current. Let us consider the parasitic parameters in the switching device, including the parasitic capacitance and parasitic inductance. The switching process of the device is not linear, and so the switching loss obtained by the prediction method is incorrect in relation to the actual loss. This also requires that more accurate switching loss predictions should be obtained through experimental calculations in situations where efficiency optimisation is required.

4. Parametric Design of the Proposed PETT

Grid-side inductance L_s affects the value of the DC-side voltage usm of H₁ and the waveform quality of the input current i_g. In addition, it places a limit on the maximum amount of power that can be transmitted. In the design of inductor L_s, it is essential to consider the metric of transient current tracking.

(i)

When the current i_g crosses zero, the rate of change of the current reaches its maximum value. In order to ensure the rapidity of the current response, the value of the inductor Ls should be as small as possible.

(ii)

Near the peak value of current i_g, harmonic pulsation is at its most serious. In order to suppress the harmonic current, the value of inductor L_s should be as large as possible.

In order to initiate the analysis, two switching cycles were selected: one near the current value of i_g = 0 and one near the peak value of i_g. The resulting tracking waveform of ig is presented in Figure 12. Figure 12a corresponds to one switching cycle in which the value of e_g changes from a negative to a positive value, while Figure 12b corresponds to one switching cycle in which the value of e_g is positive and the value of i_g reaches its peak.

In steady-state conditions, the value of the grid voltage e_g can be considered to be constant at 0 for one switching cycle, as illustrated in Figure 12a. If the effect of r_s is disregarded, the following system of equations is derived:

$$\left\{\begin{array}{ll}0=L_{\mathrm{s}}{\displaystyle \frac{\Delta i_1}{T_1}}-N_{s}N{u}_{\mathrm{sm}}\hfill & 0_1\le {\omega }_{1}t<T_1\\ 0=L_{\mathrm{s}}{\displaystyle \frac{\Delta i_2}{T_2}}\hfill & T_1\le {\omega }_{1}t<T_s\end{array}\right.,$$

(43)

In order to facilitate the rapid advancement of the command current by the i_g, it is essential to satisfy the following equation:

$${\displaystyle \frac{\left|\left|\Delta i_1\right|-\left|\Delta i_2\right|\right|}{T_s}}\ge {\displaystyle \frac{I_m\sin \left({\omega }_1{T}_s\right)}{T_s}},$$

(44)

Since the value of the switching period Ts is sufficiently small, sin(ω₁T_s)/T_s ≈ ω₁. The range of values of L_s can be determined by Equations (43) and (44) as follows:

$$L_s\le {\displaystyle \frac{N_{s}N{u}_{\mathrm{sm}}{T}_1}{I_m{\omega }_1{T}_s}},$$

(45)

In steady-state conditions, the value of the grid voltage e_g can be considered to be constant at E_m for one switching cycle, as illustrated in Figure 12b. If the effect of r_s is disregarded, the following system of equations is derived:

$$\left\{\begin{array}{ll}{E}_m=L_{\mathrm{s}}{\displaystyle \frac{\Delta i_3}{T_3}}\hfill & 0\le {\omega }_{1}t<T_3\\ E_m=L_{\mathrm{s}}{\displaystyle \frac{\Delta i_4}{T_4}}+N_{s}N{u}_{sm}\hfill & T_3\le {\omega }_{1}t<T_s\end{array}\right.,$$

(46)

Considering that |Δi₃| = |Δi₄| and T₃ + T₄ = T_s, the pulsation of current i_g can be obtained from (46) as follows:

$$\Delta i={\displaystyle \frac{N_{s}N{u}_{sm}-E_m}{L_{\mathrm{s}}{N}_{s}N{u}_{sm}}}{E}_m{T}_s,$$

(47)

If the maximum value of current pulsation is Δi_max, then the range of values of L_s can be determined as follows:

$$L_{\mathrm{s}}\ge {\displaystyle \frac{N_{s}N{u}_{sm}-E_m}{\Delta i_{\max }{N}_{s}N{u}_{sm}}}{E}_m{T}_s,$$

(48)

In conclusion, in order to satisfy the metric of transient current tracking, the value of L_s must satisfy the following inequality:

$${\displaystyle \frac{N_{s}N{u}_{sm}-E_m}{\Delta i_{\max }{N}_{s}N{u}_{sm}}}{E}_m{T}_s\le L_{\mathrm{s}}\le {\displaystyle \frac{N_{s}N{u}_{\mathrm{sm}}}{I_m{\omega }_1}},$$

(49)

The DC-side capacitor (C_sm) of H₁ serves two distinct functions: firstly, it stabilises the DC-side voltage, and secondly, it suppresses the DC-side harmonic voltage. In the case of H₁, the instantaneous value component of the input power on the AC side can be expressed as follows:

$$\left\{\begin{array}{cc}{p}_{f1}=\hfill & {\displaystyle \frac{1}{2}}{m}_1{u}_{sm}{I}_m-{\displaystyle \frac{1}{2}}{m}_1{u}_{sm}{I}_m\cos \left(2{\omega }_{1}t\right)\hfill \\ p_{f2}=\hfill & {\displaystyle \frac{2}{\pi }}{m}_2{u}_{sm}{I}_{rm}-{\displaystyle \frac{2}{\pi }}{m}_2{u}_{sm}{I}_{rm}\cos \left(2{\omega }_{2}t\right)\hfill \\ & +{\displaystyle \frac{2}{\pi }}{m}_2{u}_{sm}{I}_{rm}{\displaystyle \sum _{j=3}^{\infty }\left\{\left.\frac{1}{j}\left[\cos \left(j{\omega }_{2}t-{\omega }_{2}t\right)-\cos \left(j{\omega }_{2}t+{\omega }_{2}t\right)\right]\right\}\right.}\hfill \end{array}\right.,$$

(50)

Equation (50) shows that the instantaneous power on the AC side of H₁ consists of two parts, the DC and AC power. Similarly, the instantaneous power on the DC side of H₁ should also consist of two parts, namely, the average power consumed by the load and the ripple power of the ripple current flowing through the capacitor. The instantaneous power on the DC side can be expressed as follows:

$$p_{dc1}=u_{sm}{i}_{sm}-u_{sm}{C}_{sm}{\displaystyle \frac{d}{dt}}\Delta u_{sm},$$

(51)

where Δu_sm is the output DC ripple voltage value of H₁.

It is assumed that the power loss of the IGBT is not considered. In accordance with the law of energy conservation, the instantaneous input power of the H-bridge converter is approximately equal to the instantaneous output power on the DC side. This is expressed as follows:

$$\left\{\begin{array}{l}{u}_{sm}{i}_{sm}={\displaystyle \frac{1}{2}}{m}_1{u}_{sm}{i}_m-{\displaystyle \frac{2}{\pi }}{m}_2{u}_{sm}{i}_{rm}\\ u_{sm}{C}_{sm}{\displaystyle \frac{d}{dt}}\Delta u_{sm}=-{\displaystyle \frac{m_1{u}_{sm}{I}_m}{2}}\cos \left(2{\omega }_{1}t\right)+{\displaystyle \frac{4m_2{u}_{sm}{I}_{rm}}{3\pi }}\cos \left(2{\omega }_{2}t\right)\end{array}\right.,$$

(52)

The integration of both sides of Equation (52) results in the following:

$$C_{sm}\Delta u_{sm}=-{\displaystyle \frac{m_1{I}_m}{4{\omega }_1}}\sin \left(2{\omega }_{1}t\right)+{\displaystyle \frac{2m_2{I}_{rm}}{3\pi {\omega }_2}}\sin \left(2{\omega }_{2}t\right),$$

(53)

If the maximum allowable pulsation value of u_sm is denoted as Δu_max1, then Δu_max1 ≥ 2Δu_sm needs to be satisfied. According to Equation (53) the range of values of C_sm can be determined as follows:

$$C_{sm}\ge {\displaystyle \frac{4m_2{I}_{rm}}{3\pi {\omega }_2\Delta u_{\max 1}}}+{\displaystyle \frac{m_1{I}_m}{2{\omega }_1\Delta u_{\max 1}}},$$

(54)

Similarly, the range of values of C_dc can be determined as follows:

$$C_{dc}\ge {\displaystyle \frac{4N{m}_2{I}_{rm}}{3\pi {\omega }_2\Delta u_{\max 2}}},$$

(55)

where Δu_max2 is the maximum allowable pulsation value of u_dc.

5. Simulation Analysis

In order to ascertain the efficacy of the proposed PETT circuit, a 1.2 MW PETT was designed and presented in this paper. The specifications of the traction grid included 15 kV/16.7 Hz. The sub-module had a DC-side voltage of 3.6 kV and a DC output voltage of 1.2 kV. Based on the design methodology outlined in Section 2, Section 3 and Section 4, the design flow of the main circuit parameters of the proposed PETT is shown in Figure 13. The principal circuit parameters of the PETT can be derived from Figure 13. The fundamental characteristics of the proposed PETT circuit are presented in

Table 3. Parameters of PETT.

Circuits	Parameter	Values	Parameter	Values
Main circuit	Grid phase voltage RMS vg	15 kV	Grid frequency f1	16.7 Hz
	Rated power PN	1.2 MW	Grid-side inductance Ls	60 × 10−3 H
	Number of PM Ns	2	Number of SM N	4
	Resonant inductance Lr	56.7 × 10−3 H	Resonant capacitance Cr	1 × 10−6 F
	Sub-module capacitance Csm	6 × 10−3 F	Output-side capacitance Cdc	24 × 10−3 F
	Transformer ratio NT	4.8	Resonant frequency f2	668 Hz
Control Circuit	Control mode of H1	PWM	Control mode of H2	open loop control
	Switching frequency of H1	2 kHz	Switching frequency of H2	2 kHz
	DC-side voltage of H1	3.6 kV	DC-side voltage of H2	1.2 kV

.

In Figure 13, Equations (56)–(64) are specifically expressed as follows:

$$U_{sm}\ge {\displaystyle \frac{E_m}{N_{s}N}},$$

(56)

where E_m is the peak value of the phase voltage, in this case the value of 12,247 V, and U_sm is the design value of the sub-module capacitance voltage, in this case the value of 3600 V.

$$L_r{C}_r={\displaystyle \frac{1}{{\omega }_2^2}},$$

(57)

where ω₂ is the resonant frequency of the filter, which in this case takes the value of 2000 Hz.

$${\displaystyle \frac{N_{s}N{U}_{sm}-E_m}{4P_m{N}_{s}N{U}_{sm}\Delta i}}{E}_m^2{T}_{pwm}\le L_{\mathrm{s}}\le {\displaystyle \frac{N_{s}N}{2P_m{\omega }_1}}{U}_{\mathrm{sm}}{E}_m,$$

(58)

where P_m is the maximum transmitted power, which is taken here as 1.2 MW; T_PWM is the switching period of H₁, which is taken here as 10,000 Hz; ω₁ is the frequency of the grid voltage, which is taken here as 16.7 Hz; and Δi is the maximum permissible value of the current ripple, which is taken here as 5%.

$$L_{\mathrm{s}}\le {\displaystyle \frac{E_m\sqrt{{\left(N_{s}N{U}_{sm}\right)}^2-E_m^2}}{2{\omega }_1{P}_m}},$$

(59)

$$E_{m1}={\displaystyle \frac{1}{N_{s}N}}\sqrt{E_m^2+{\left({\displaystyle \frac{2{\omega }_1{L}_s{P}_m}{E_m}}\right)}^2},$$

(60)

$$N_T={\displaystyle \frac{mN{U}_{sm}-N{E}_{m1}}{U_{dc}}},$$

(61)

where U_dc is the design value of the output DC voltage of the PETT, which in this case is taken as 1200 V.

$$E_{m2}={\displaystyle \frac{N_T}{N}}{U}_{dc},$$

(62)

$$m_1={\displaystyle \frac{E_{m1}}{U_{sm}}}, m_2={\displaystyle \frac{E_{m2}}{U_{sm}}},$$

(63)

$$\left\{\begin{array}{l}{C}_{sm}\ge {\displaystyle \frac{2m_2{P}_m}{3\pi {\omega }_2{U}_{sm}\Delta u}}+{\displaystyle \frac{m_1{P}_m}{2{\omega }_1{E}_m{U}_{sm}\Delta u}}\\ C_{dc}\ge {\displaystyle \frac{2N{m}_2{P}_m}{3\pi {\omega }_2{N}_{s}N{E}_{m2}{U}_{dc}\Delta u}}\end{array}\right.$$

(64)

where Δu is the maximum permissible value of the capacitor voltage ripple, which in this case is taken as 3%.

The PET prototype, designed in accordance with Figure 1 and detailed in

Table 4. The cascade PETT design of different structures.

Structure	Specification of PETT	Specification of Switching Devices	Number
			Sub-Modules	Switching	Capacitors	MFT
Figure 1a	1.2 MW	AC/DC:6.5 kV IGBT DC/DC:3.3 kV IGBT	8	96	32	8
Figure 1b	AC: 15 kV/16.7 Hz		8	64	48	8
Figure 2	DC: 1.5 kV		8	40	12	2

, is compared with the designed PETT in this paper. It is observed that the proposed PETT employs a reduced number of sub-modules, switching devices, capacitors, and MFTs. It is shown that the proposed PETT has the advantage of requiring a reduced number of power devices and passive components under the condition of the same grid voltage, the same IGBT voltage level, and the same output voltage. Furthermore, this advantage is more pronounced when non-high-voltage IGBTs are employed.

In order to ascertain the veracity of the designed PETT circuit, a simulation model was constructed and analysed using PLECS 4.2. The simulation parameters are presented in Table 3. The simulation process is as follows: at 0 ≤ t < 3 s, the PETT operates at the rated load. At 3 s ≤ t < 6 s, the PETT operates at 80% of the rated load. At 6 s ≤ t < 9 s, the PETT operates at 60% of the rated load.

Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18 show the simulation results of some physical quantities at the primary side of the IF transformer. Specifically, Figure 14 gives the waveforms of current i_g and voltage e_g at the grid side of the PETT. When the PETT is running stably, the sinusoidal nature of the current is good, the power factor is kept at 1, and the voltage waveform can be tracked. The calculated value of the peak current is 195.96 A at a rated load and the simulation yields a peak value of 202.3 A with an error of 3%. At t = 3 s and t = 6 s, the sudden change in load causes a short oscillation in the current, which can quickly reach a steady state, and the peak current increases after stabilisation. The results of FFT analysis of the grid side current at rated load are given in Figure 15, which shows a THD of 10.08%.

Figure 16 illustrates the waveforms of the current i_r and voltage u_T at the primary side of the MFT. u_T is a square wave with a frequency of 668 Hz when the PETT is running stably, and the current i_r is of the same frequency and the same phase as u_T. Under the rated load, the peak value of voltage u_T is 5760 V, and the peak value of current ir is 166 A. At t = 3 s and t = 6 s, the sudden change in the load causes a brief oscillation in the current, which can quickly reach a steady state. The peak value of the current increases after stabilisation, and the peak value of the voltage remains unchanged after stabilisation. Figure 17 gives the results of FFT analysis of i_r at rated loads, showing a THD of 4.62%.

Figure 18 gives the waveforms of the voltage of capacitor C_sm in H₁. The value of the voltage u_sm is 3600 V during the stable operation of the PETT, which agrees with the design value. The ripple of the stabilised voltage is 1.1%, 1.4%, and 1.8% at different operating points. These values meet the design requirements. At the moment of a sudden load change, the u_sm stabilises again faster.

Figure 19 shows the waveforms of the voltage of capacitor C_dc in H₂. The value of the voltage u_dc is 1200 V during the stable operation of the PETT, which matches the design value. The ripple of the stabilised voltage is 0.50%, 0.58%, and 0.71% at different operating periods, which meets the design requirements. At the moment of a sudden load change, udc stabilises again faster.

6. Conclusions

Cascaded PTETTs are considered effective in terms of reducing the number of conventional low-frequency transformers in locomotives, with the advantages of light weight, small size, and high efficiency. However, the issue of the large number of switching devices and passive components in this type of converter cannot be ignored. In this paper, a novel PETT structure is introduced, and its feasibility is verified by theoretical analysis and simulation. The results show that the proposed PETT can achieve the multiplexing of the H-bridge through effective control, and the voltages at different frequencies are decoupled. The grid-side current can track the grid voltage better and achieve unit power factor operation. The sub-module capacitor voltage and output DC voltage can be better controlled to be in accordance with the design’s value and reach the steady state again faster when the load changes abruptly. Finally, the proposed PETT has positive significance, with reduced size and weight in relation to other PETTs and increased the power density.

Voltage equalisation strategies between multiple sub-modules of the proposed PETT will also be explored in the future. In addition, the development of accurate loss models will help to design more efficient PETTs, and these studies will further deepen the research on the proposed PETT and enable the successful use of the prototype on a locomotive.