A Control Strategy for Suppressing Zero-Crossing Current of Single-Phase Half-Bridge Active Neutral-Point-Clamped Three-Level Inverter

Abstract

Multi-level inverters have characteristics suitable for high-voltage and high-power applications through various topology configurations. These reduce harmonic distortion and improve the quality of the output waveform by generating a multi-level output voltage waveform. In particular, an active neutral-point-clamped topology is one of the multi-level inverters advantageous for high-power and medium-voltage applications. It has the advantage of controlling the output waveform more precisely by actively clamping the neutral point using an active switch and diode. However, it has a problem, which is that an unwanted zero-crossing current may occur if an inaccurate switching signal is applied at the time when the polarity of the output voltage changes. In this paper, a control strategy to suppress the zero-crossing current of a single-phase half-bridge three-level active neutral-point-clamped inverter is proposed. The operating principle of a single-phase half-bridge three-level active neutral-point-clamped inverter is identified through an operation mode analysis. In addition, how the switching signal is reflected in an actual digital signal processor is analyzed to determine the situation in which the zero-crossing current occurs. Through this, a control strategy capable of suppressing zero-crossing current is designed. The proposed method prevents a zero-crossing current by appropriately modifying the update timing of reference voltages at the point where the polarity of the output changes. The validity of the proposed method is verified through simulation and experiments. Based on the proposed method, the total harmonic distortion of the output current is significantly reduced from 12.15% to 4.59% in a full-load situation.

1. Introduction

Single-phase inverters and rectifiers are the most essential components in power conversion technology. They convert alternating current (AC) to direct current (DC) and DC to AC. These conversion technologies are widely used in home and industrial applications, including renewable energy sources such as solar power and fuel cells [1,2,3], electric and hybrid electric vehicle chargers [4,5], and power supplies [6,7].

Single-phase inverters have the characteristics of simple structure and cost-effectiveness. These single-phase inverters have various topologies, each with specific characteristics and advantages. Among the several common topologies of single-phase inverters, the single-phase half-bridge inverter, which consists of two switches, is widely used. This topology has the advantages of a simple structure, low cost, and ease of implementation but has the disadvantages of high voltage stress and limited output voltage size [8]. The single-phase full-bridge inverter enables better control and higher output voltage levels. However, its disadvantages include increased cost and switching loss due to the increased number of components used compared to the half-bridge [8]. Multilevel inverters have characteristics suitable for high-voltage and high-power applications, including diode clamps, flying capacitors, and cascaded H-bridge topologies. They can generate multiple levels in the output voltage waveform to reduce harmonic distortion, improve the quality of the output waveform, and achieve low electromagnetic interface (EMI) [9]. The active neutral-point-clamped (ANPC) topology is one method of designing multilevel inverters that are particularly advantageous for high-power and medium-voltage applications. It uses active switches such as IGBTs and diodes to actively clamp the neutral point, which can provide more precise control of the output waveform, thereby reducing harmonic distortion and improving power quality. In addition, the active clamping mechanism can reduce the switch’s voltage stress, enhancing its life and reliability. By optimizing the switching strategy of the ANPC topology, the ANPC inverter can achieve high efficiency suitable for high-power applications [10]. The ANPC topology has been used in applications such as solar inverters, wind inverters, and electric vehicle charging systems where efficiency, reliability, and power quality are essential [11].

An AC-to-AC conversion system utilizing single-phase half-bridge three-level ANPC (SH-ANPC) is shown in Figure 1. SH-ANPC can perform bidirectional power transfer operations by switches within the topology. Accordingly, as shown in the figure, it can be used as a rectifier that converts AC power into DC power or as an inverter that converts DC power into AC power. In this way, a bidirectional AC/AC converter can be configured by utilizing an SH-ANPC topology, and it can be configured as a single-phase inverter with DC-link voltage as an input source. In addition, a three-phase inverter can be configured by using three modularized SH-ANPCs. Therefore, an SH-ANPC topology can be widely used in various power conversion systems [12,13,14,15].

Although various studies have been conducted on the ANPC topology, the distortion at the zero-crossing point that appears during operation has not yet been prevented. SH-ANPC must suppress unnecessary current increases at points where voltage and current polarities change, like general half-bridge topology and single-phase PFC (power factor correction) converters [16]. The distortion at the zero-crossing point of the ANPC topology is a significant issue that affects power conversion efficiency and power quality, and such distortion can cause an unnecessary EMI and deteriorate the operational stability of other connected devices. The authors of [17] propose a hybrid pulse-width modulation (PWM) strategy that effectively improves the conventional PWM technique to alleviate zero-crossing distortion. This technique optimizes the switching pattern to minimize distortion at the zero-crossing point. Also this technique requires a dedicated field-programmable gate array (FPGA), rather than a digital signal processor (DSP), as it does not rely on the typical operation of complementary switching signals. In [18], a PWM control strategy that utilizes an immune-algorithm is proposed to resolve distortion at zero-crossing in a single-phase full-bridge inverter. This approach improves the power conversion efficiency of the inverter, enhances the output voltage quality, and enables system performance optimization. However, whether the approach can be applied to other single-phase inverter topologies has not been sufficiently analyzed. In [19], a carrier-based PWM method optimized for five-level ANPC converters is presented, enhancing harmonic performance and minimizing current ripple while simultaneously ensuring uniform loss distribution. Additionally, the study introduces an optimized phase-shifted PWM method which provides the same harmonic performance as conventional phase-disposition PWM while maintaining the control characteristics of traditional phase-shifted PWM.

Various studies have been conducted to solve the zero-crossing issue in various inverters and rectifiers other than SH-ANPC. In [20], a carrier-based pulse-width modulation method for a three-phase Vienna rectifier is proposed, considering variable power factor conditions. The method introduces compensation voltages to the three-phase reference voltages, considering the operational requirements based on the power factor. In [21], a control strategy for suppressing input current zero-crossing distortion in Vienna rectifiers is proposed. This strategy is designed by deriving the operational constraints of the Vienna rectifier, including the stationary operation region and the phase difference between input current and reference voltage. Based on this relationship, an interval clamping control strategy using negative-sequence current regulation is proposed. In [22], a novel zero-sequence component injection modulation method is introduced to improve the input quality of the Vienna rectifier under balanced or unbalanced DC-link voltages. By considering operational characteristics, three-phase compensation components are individually calculated based on the unbalance factor and added to the three-phase average duty cycles during abnormal periods. As a result, current harmonics in the Vienna rectifier are reduced, regardless of whether the DC-link voltages are balanced or unbalanced. However, since the proposed methods are difficult to apply to SH-ANPC topology, further research on approaches tailored to ANPC topology is necessary.

In this paper, a control strategy to suppress the zero-crossing current of SH-ANPC is proposed. The detailed operation mode is analyzed to find the relationship between the zero-crossing current and the operation mode of SH-ANPC. In addition, how the switching signal is reflected in a DSP is analyzed to determine the situation in which the zero-crossing current occurs. Through this, a control strategy capable of suppressing zero-crossing current is designed. The contents of this paper are as follows. Section 2 analyzes the operating principle of SH-ANPC. Section 3 analyzes the zero-crossing current phenomenon of SH-ANPC in detail. Section 4 covers the details of the proposed algorithm. Section 5 presents simulation and experimental results to verify the feasibility of the proposed algorithm. The validity of the proposed method is verified through simulation and experiments.

2. Operation Principle of SH-ANPC Inverter

The circuit diagram of a single-phase inverter composed of SH-ANPC is shown in Figure 2. Here, v_dc is the input voltage applied to the DC-link, and C_H and C_L are the upper and lower DC-link capacitors, respectively. s₁ to s₆ are IGBT switches constituting the SH-ANPC, and L and C are the output inductor and capacitor.

In the case of a general multi-level half-bridge inverter, the neutral point of the input or output and the middle node of the DC-link neutral point are connected. Through this, the input or output AC voltage is applied to CH and CL, respectively, depending on the switch operation status, so that the DC-link voltage has a voltage more than twice the maximum AC voltage. For example, when the maximum value of vac is about 300 V, the DC-link voltage is applied at least twice, which is 600 V. Additionally, the output voltage can be clamped to the middle node of the DC-link depending on the switching state to output zero voltage.

SH-ANPC has various switching strategies depending on the driving method of the six switches [12,17]. Accordingly, an appropriate switching strategy should be selected depending on the IGBT switch or package used in the converter hardware. In this paper, s₅ and s₆ operate at high speed frequencies, and switches s₁ to s₄ change the on/off state as the polarity of the AC voltage changes. In other words, using devices with better conduction characteristics is more advantageous than switching characteristics from _S1 to s₄ as rectifier switches. Additionally, s₅ and s₆ are high-speed switches, so both switching characteristics and conduction characteristics must be considered. The detailed waveforms of a PWM applied in this paper are shown in Figure 3. The first shows two saw-tooth carrier waveforms (V_carr^H, V_carr^L) and the reference waveform, noted as d, and the rest shows enlarged waveforms and the switching signals at the corresponding points.

Two saw-tooth carrier waveforms are used to make a three-level output waveform, and V_carr^H and V_carr^L have the maximum and minimum values of +V_M and −V_M, respectively. The final reference waveform from the control algorithm to obtain a sinusoidal output voltage is represented by d. When d is larger than the carrier waveform, s₅ is turned on, and in the opposite case, s₅ is turned off. In addition, s₆ operates complementarily with s₅. Since two carrier waveforms are used, when the polarity of d changes, the duty ratio of the high-speed switch changes abruptly from a value close to 1 to a value close to 0. The third and fourth waveforms show the rectifier switch operating at low speed. When the output voltage or d changes from negative to positive, _S1 and s₃ are turned on, and s₂ and s₄ are turned off. In the positive cycle, where the output voltage has a positive value, _S1 and s₃ are turned on, and in the negative cycle, where the output voltage has a negative value, s₂ and s₄ are turned on.

To implement PWM and switching operations, as shown in Figure 3, two carrier waveforms are required. However, since general DSPs or MCUs (micro controller units) implement PWM based on a counter function that increases steadily at each set period, it can be challenging to set a carrier waveform with a negative value. Therefore, if a method of changing the reference waveform as shown in Figure 4 is used, the implementation difficulty can be easily solved. When the value of d output from the control algorithm is between +V_M and −V_M, the modified reference waveform (d_m) can be expressed as follows.

$$d_m=\{\begin{array}{c}d,\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}Positive\hspace{0.17em}\hspace{0.17em}cycle\hspace{0.17em}\hspace{0.17em}of\hspace{0.17em}\hspace{0.17em}{v}_{ac}\hfill \\ V_M+d,\hspace{0.17em}\hspace{0.17em}Negative\hspace{0.17em}\hspace{0.17em}cycle\hspace{0.17em}\hspace{0.17em}of\hspace{0.17em}\hspace{0.17em}{v}_{ac}\hfill \end{array}$$

(1)

In other words, in the positive cycle, the original value d is used to compare it with a single carrier waveform (V_carr), and in the negative cycle, V_M is added to d to compare it with V_carr.

This method is relatively easy to implement compared to the process in Figure 3 because it can be implemented through a simple conditional statement in the firmware. In addition, since the switch operations are equal, as in Figure 3, it can be confirmed that the output values of the two methods are the same. In addition, since the characteristic of the dm value changing rapidly from 1 to 0 at the zero-crossing point is the same, it can be confirmed that the duty ratio of the high-speed switch changes significantly in the same way.

Figure 5 shows the circuit mode analysis of SH-ANPC for the switching states.

Table 1. Switching status table of SH-ANPC.

Switching Status		s1 & s3	s2 & s4	s5	s6
Positive reference	P status	On	Off	On	Off
	O status	On	Off	Off	On
Negative reference	N status	Off	On	Off	On
	O status	Off	On	On	Off

shows the definition of switching status for SH-ANPC. The voltages of C_H and C_L are 0.5v_dc each, and v_p is the output pole voltage. v_L and i_L are the inductor voltage and current. The orange arrows indicate the current conduction paths for each mode. Figure 5a,b show the modes when the rectification switches s₁ and s₃ are turned on and s₂ and s₄ are turned off in a positive cycle. Figure 5a shows the mode when the high-speed switch s₅ is turned on. At this time, v_p and v_L are as follows; accordingly, i_L has a positive current slope.

$$v_p=0.5v_{dc}$$

(2)

$$v_L=0.5v_{dc}-v_{ac}>0$$

(3)

This operation mode is defined as P status. In P status, the energy stored in the DC-link is transferred to the output. Figure 5b shows when the high-speed switch s₅ is turned off. At this time, v_p and v_L are as follows:

$$v_p=0$$

(4)

$$v_L=-v_{ac}<0$$

(5)

This operation mode is defined as the O status. In the O status, unlike the P status, the stored energy of the DC-link is not transferred to the output terminal because the v_p voltage is 0.

Figure 5c,d show the modes in a negative cycle when the rectification switches s₂ and s₄ are turned on and s₁ and s₃ are turned off. Figure 5c shows the mode when the high-speed switch s₅ is turned off. At this time, v_p and v_L are as follows; accordingly, i_L has a negative current slope.

$$v_p=-0.5v_{dc}$$

(6)

$$v_L=-0.5v_{dc}-v_{ac}<0$$

(7)

This operation mode is defined as N status. In N status, the energy stored in the DC-link is transferred to the output, the same as in P status. Figure 5d shows when the high-speed switch s₅ is turned on. At this time, v_p and v_L are as follows:

$$v_p=0$$

(8)

$$v_L=-v_{ac}>0$$

(9)

This operation mode is O status, the same as in Figure 5b.

3. Proposed Control Strategy for Suppressing Zero-Crossing Current of SH-ANPC

3.1. Analysis of Zero-Crossing Current Phenomenon of SH-ANPC

The previous section explained the operating principle and mode analysis of SH-ANPC. If rectification and high-speed switches are driven adequately according to the reference signal, the desired AC output can be converted as analyzed. However, when the switching pulse is formed with the PWM peripheral of the DSP or MCU, an unintended switching operation may occur. In particular, if the desired switching operation is not performed correctly at the zero-crossing point where the polarity of the AC voltage changes, a sizeable zero-crossing current may occur. In this section, the phenomenon of zero-crossing current is analyzed.

Figure 6 shows the switching pattern and the status of SH-ANPC when changing from a negative to a positive cycle. Here, d_r represents the reference waveform for the rectification switch. When forming a switching pulse using the PWM peripheral of the DSP, the values of the reference waveform, such as d_m and dr, are updated when the carrier waveform is zero or has the maximum value. The pink arrow indicates the update timing of the reference waveform. In the case of d_m, it should vary continuously in the time domain. However, it has a constant value during one switching period when implemented in a digital environment due to sample-and-hold. This characteristic is shown in the d_m waveform in Figure 6.

As shown in Figure 6a, when references are updated at the maximum value of V_carr, both d_m and d_r are compared appropriately with V_carr, so the desired switching signal is formed appropriately. Therefore, the status changes smoothly. That is, the status at the commutation point changes appropriately in the order of N → O → P so that a spike current does not occur. On the other hand, as shown in Figure 6b, when references are updated at the zero of V_carr (or its minimum value) d_m is compared directly with V_carr, and s5 turns off. However, d_r is compared after half a cycle even though the value has changed at the update time. This situation causes a 0.5T_sw time delay in changing the rectification switch. Due to this delayed switching signal, the N status is unnecessarily maintained at the commutation point (negative to positive). Consequently, a zero-crossing spike current occurs.

Figure 7 shows the switching pattern and the status of SH-ANPC when changing from a positive to a negative cycle. As shown in Figure 7a, when references are updated at the minimum value of V_carr, both d_m and d_r are compared appropriately with V_carr, so the desired switching signal is formed appropriately. Therefore, the status changes smoothly same as Figure 6a. The status at the commutation point changes appropriately in the order of P → O → N so that a spike current does not occur. On the other hand, as shown in Figure 7b, when references are updated at the maximum value of V_carr, d_m is compared directly with V_carr, and s5 turns on. However, d_r is compared after half a cycle even though the value has changed at the update time. This situation causes a 0.5T_sw time delay in changing the rectification switch, same as in Figure 6b. Due to this delay, the P status is unnecessarily maintained at the commutation point. Consequently, a zero-crossing spike current occurs. The analysis results in Figure 6 and Figure 7 show that the reference waveform must be updated appropriately for each commutation point to prevent zero-crossing current.

3.2. Proposed Control Strategy

In the previous section, we analyzed the zero-crossing current, which occurs depending on the update timing of the two reference values (d_r, d_m). In general, when implementing a converter control environment, the reference value is configured to update at a specific time of a carrier waveform. For example, it is set to update at the minimum value, as in Figure 6b, or at the maximum value, as in Figure 6a. Alternatively, it can be configured to update at both the minimum and maximum value, which is usually one of the methods for implementing double sampling to compensate for the error of the sensing value. However, as analyzed in the previous chapter, the zero-crossing current can be prevented only by appropriately detecting the rectification point and changing the configuration of the update timing. Accordingly, a control algorithm is proposed to adjust the timing at which the reference value is updated. The detailed flow chart is shown in Figure 8.

• Step 1: Check polarity change

Since the update timing of the reference value is typically fixed, unnecessary changes should be avoided. In other words, the appropriate update adjustment is necessary only when the polarity of the output voltage changes—accordingly, the timing when the polarity of the output voltage changes must first be determined. There are various methods to check the change in the polarity of the output voltage.

For example, it can be determined based on the sensed value of output voltage, or it can be resolved through the phase information from the phase lock loop (PLL) calculation. This paper uses the output voltage to check the changing polarity, which is the most straightforward method.

• Step 2: Change update timing

If the rectification point is defined by the previous step, the update timing should be adequately changed depending on the cycle polarity. If the output changes to a positive cycle, the configuration should be changed to update at maximum V_carr, as in Figure 6a. On the contrary, if the output changes to a negative cycle, the configuration should be changed to update at minimum V_carr, as in Figure 7a. If it is not the point of change in polarity, it should be restored to the default update timing.

As mentioned earlier, the update timing of reference voltages is typically fixed at specific points (such as the maximum, minimum, or both the maximum and minimum of Vcarr), and frequent changes can negatively impact the overall control algorithm. Therefore, the operation in step 2 should only be applied at the point where the polarity changes and within one sampling period in the firmware. The default update configuration should be restored once the sampling period passes the zero-crossing point.

• Step 3: Update reference and output switching signal

Finally, the change in d_r and d_m is applied at the modified update time to compare a carrier to references appropriately. Based on the proposed method, the switching signal has the appropriate output.

If the proposed method is applied sequentially, the unnecessary persistence of the status at the zero-crossing point can be prevented. Specifically, the unnecessary persistence of N status can be avoided at the point where the polarity changes from positive to negative, as shown in Figure 6b. Similarly, the unnecessary persistence of P status can be avoided when the polarity changes from negative to positive.

4. Verification Based on Simulations and Experiments

The validity of the proposed control strategy is verified through simulation and experiments. The parameters of SH-ANPC are shown in

Table 2. Parameter specifications of SH-ANPC.

Parameters	Symbol	Values
Input voltage	vdc	750 V
Output voltage	vac	220 Vrms
Equivalent output load	Req	4.5 Ω
DC-link capacitance	CH, CL	28.2 mF
Inductance	L	75 μH
Capacitance	C	100 μF
Switching frequency	fsw	8 kHz
IGBT module	s1 to s6	30-PT07NAA300S501-LF64F58Y

.

Figure 9 shows the simulation results when changing from a negative to a positive cycle. The first waveform shows i_L, and the remaining waveforms are enlarged waveforms when polarity changes. Figure 9a shows the simulation result when the delay in the rectifier switch occurs, as in Figure 6b. As in the analysis result, the N status is maintained for half a switching cycle due to the delay in rectification switches. Even though the polarity has changed, the current flows in the opposite direction, and a negative current spike occurs because v_p is maintained at −0.5V_dc. In addition, v_p is clamped to zero voltage by changing from N status to O status, and thus a negative current is maintained. In other words, it can be confirmed that the zero-crossing current maintains not only commutation timing but also the subsequent status.

On the other hand, Figure 9b is the result of when the switching signal is applied correctly, as in Figure 6a, and it can be confirmed that the current flows appropriately without the zero-crossing current. Also, v_p is output appropriately according to the mode change.

Figure 10 shows the simulation results when changing from a positive to a negative cycle. The waveform configuration is the same as in Figure 9. Figure 10a shows the simulation result when the delay in the rectifier switch occurs, as in Figure 7b. The unwanted P status is maintained due to the delay in rectification switches. Same as in Figure 9a, a positive current spike occurs because v_p is maintained at +0.5V_dc. After P status, v_p is clamped to zero at O status, and thus a zero-crossing spike current is continuously flowing. Figure 10b is the result when the switching signal is applied correctly, as in Figure 7a, and the current flows appropriately without the zero-crossing current.

The simulation results obtained by changing the output load conditions are shown in Figure 11. As in Figure 10, it can be confirmed that the zero-crossing current occurs regardless of the load size when the proposed method is not applied. In addition, when the proposed method is applied, an output current close to a sinusoidal wave is measured. The results of the total harmonic distortion (THD) of i_L in Figure 10 and Figure 11 are shown in

Table 3. Current THD results.

THD [%]	Light Load	Half Load	Full Load
Without algorithm	12.86	12.47	12.15
With algorithm	4.18	4.36	4.59

. It can be confirmed that the current THD is significantly reduced in all situations by applying the proposed method.

Through simulation results, the validity of the analysis results is verified by confirming that the analysis results performed in Section 3 are the same as the simulation results. In addition, it can be confirmed that the zero-crossing current problem can be prevented when the proposed strategy is applied.

A photograph of the prototype and a detailed block diagram of the experimental setup for verifying the proposed SH-ANPC control strategy is shown in Figure 12. A control board based on TI’s DSP (TMS320F28377D) is used to implement the proposed algorithm.

A photograph of the prototype for verifying the proposed SH-ANPC control strategy is shown in Figure 12. A control board based on TI’s DSP (TMS320F28377D) is used to implement the proposed algorithm. A double sampling configuration is applied to the firmware to minimize the sensing error. That is, reference values are updated at a minimum and maximum V_carr.

Figure 13 shows the experimental waveform results through the hardware of SH-ANPC. The upper waveforms represent the high-speed switch signal (s₅), the rectification switch signal (s₁), and the modified reference (d_m) in order. The lower waveforms represent the inductor current (i_L) measured through the current probe. Figure 13a shows the waveform in which the zero-crossing current occurs due to the delay in the rectification switch. In the implemented hardware, it can be confirmed that current distortion occurs relatively long due to the spike current generated at the rectification point. Figure 13a shows the waveform in which the zero-crossing current does not occur by the proposed control strategy. As with simulations, the effectiveness of the proposed strategy is verified through experimental results.

Figure 14 provides a detailed analysis of the waveform presented in Figure 13a. In this paper, the reference waveform is updated when V_carr reaches its maximum or minimum value. In other words, double sampling is used as the default at firmware of DSP, with two updates occurring within one switching period. As a result, the reference waveform can be reflected at the maximum or minimum value of V_carr at the zero-crossing point. This leads to an unintended 0.5T_sw delay, occurring irregularly at the zero-crossing point, as shown in Figure 6b and Figure 7b. To clearly illustrate this phenomenon, Figure 14 depicts the update situation at each zero-crossing. Consequently, an irregular zero-crossing current occurs in the double-sampling configuration.

A comparison of the different methods is shown in

Table 4. Comparison of characteristics with conventional methods.

Characteristics	[19]	[17]	[20]	[21]	[22]	Proposed Method
Hardware topology	Five-level ANPC	Three-level ANPC	Vienna Rectifier	Vienna Rectifier	Vienna Rectifier	Three-level ANPC
Type of algorithm	PWM	PWM	Sequence	Sequence	Sequence	Sequence
Complexity	Middle	Middle	High	High	High	Low
Improvement of current THD	Middle	Middle	High	High	High	High
Consideration of weak-grid conditions	Δ	X	O	O	O	Δ
Adaptability for SH-ANPC	X	O	X	X	X	O

. Reference [19] proposes a PWM technique for five-level ANPC, and its applicability to SH-ANPC is low. Reference [17] proposes a PWM method for reducing zero-crossing current, but it is not easy to guarantee the algorithm’s effect in a weak-grid situation. References [20,21,22] propose a new sequence to improve the performance of the Vienna rectifier. All three papers commonly propose a method that can significantly improve the current THD when the power factor is not unified or the grid voltage has a sizeable harmonic component. However, these methods are not suitable for an SH-ANPC topology. The proposed method is for SH-ANPC, so it is highly adaptable. Although it is relatively low in complexity, it has a significant advantage in improving the current THD.

5. Conclusions

This paper proposed a control strategy to suppress the zero-crossing current of SH-ANPC. The detailed operational mode of SH-ANPC was analyzed to produce a control strategy. In particular, it was confirmed that an unintended delay in rectification switches occursdepending on the reference update at the rectification point. In addition, it was analyzed that the zero-crossing current cannot be prevented with the standard updating configuration of the general PWM. Accordingly, in this paper, a method to avoid the zero-crossing current was developed by implementing a simple control strategy. The proposed method was verified through simulation and experiments.

In this paper, we conducted an analysis and verification assuming an ideal output grid voltage. In other words, it is essential to analyze the zero-crossing phenomenon in weak grid situations, including those affected by harmonic voltage. Furthermore, it is necessary to investigate the operation of the SH-ANPC in conditions below the unity power factor. In the future, we plan to verify the validity of the proposed method under weak grid conditions and explore advanced control strategies in the presence of various grid harmonics and power factor scenarios.