A Novel Single-Phase Five-Level Current-Source Inverter Topology

Abstract

Recent technological advances have renewed the research interest in current-source inverters (CSIs). Nonetheless, CSI research still falls behind its voltage-source counterpart with regards to topologies, modulation, and control. Acknowledging the above, this paper presents a novel single-phase five-level CSI topology. The proposed circuit utilises eight switches and two inductors for the generation of five distinct output levels while maintaining low output voltage THD and $dv/dt$. Furthermore, by offsetting the inductor currents from a binary 1:2 to a trinary 1:3 ratio, the proposed inverter can generate seven current levels at its output. The inverter offers built-in short-circuit protection and can boost a low input DC voltage to a higher peak AC output voltage. These merits, alongside an electrolytic-capacitor-free design, simple current balancing mechanism, and fault-tolerant characteristics, make it a promising candidate for PV module-integrated inverter (MII) systems. The current topology utilises two inductors but is fully functional with single-inductor operation. The paper provides a functional analysis of the inverter topology alongside the inverter switching states and corresponding conduction paths. A detailed analysis of the inductor current dynamics as well as a current-balancing algorithm for dual- and single-inductor operations are given. The theoretical analysis of the proposed circuit and its functional operation are verified using simulations and experimental results carried out on a laboratory prototype.

1. Introduction

Converter topologies can be generally divided into two groups: namely, voltage-source inverters (VSIs) and current-source inverters (CSIs) [1,2]. Traditionally, superior efficiency and structural simplicity have tipped the research scale in favour of voltage-fed inverters [3] and have left CSIs lagging behind with respect to topologies, control methods, modulation strategies, and modelling [4]. Wide industry adoption of VSIs has, in turn, influenced the semiconductor market, resulting in enhancement-mode devices that lack reverse-blocking (RB) capabilities [5]. This has further consolidated the role of VSIs in the power conversion arena and has limited CSI applications to high-power, low-switching-frequency conversion [6,7,8].

However, recent advances in semiconductor technology have opened new avenues for CSI applications. Wide bandgap (WBG) devices facilitate switching frequencies an order of a magnitude higher compared with their Si counterparts and are capable of withstanding higher junction temperatures [9]. Increased switching frequencies result in notable volume reduction of DC link inductors and lead to higher converter power densities. This is not necessarily the case with VSIs, for which DC link capacitors are mostly sized to withstand current ripples [10]. Increased system operating temperature, made possible through a combination of high-temperature-resilient inductors and WBG devices with increased junction temperatures, can ease cooling requirement and result in even denser converters. Finally, the emergence of single-chip RB-IGBTs [11] and fabrication progress made with their WBG siblings, RB-SiC [12] and RB-GaN [13], is expected to further improve CSI densities by reducing package count and minimizing parasitic inductance.

Industry trends towards higher-performance systems, mainly in terms of efficiency, power density, reliability, and lifespan, also encourage the re-evaluation of traditional converter configurations. CSIs’ inherent voltage boosting characteristics, electrolytic-capacitor-free design, and low output voltage to total harmonic distortion (THD) are all highly desirable features, which if taken into account during the design stage, can make CSIs a leading candidate in many power conversion applications [14].

Solar photovoltaic (PV) systems are a distinct domain in which CSI conversion can prove beneficial. Binding energy targets necessitate improved PV systems with increased returns on investment (ROIs) [15]. Voltage-fed PV inverters employ aluminium electrolytic capacitors (AEC) that degrade system reliability and increase downtime and maintenance costs [16]. CSIs, on the other hand, use power inductors capable of withstanding harsh thermal cycles and match the lifespan of PV modules: namely, 25 years [17,18,19]. Matching the lifetime of PV modules is extremely important for module-integrated inverter (MII) systems, for which power electronics are mounted directly on the module and are exposed to extreme weather conditions [20]. MII systems hold great potential in residential PV applications as they improve energy harvesting [21], increase system efficiency and reliability [17], and lower installation costs [22]. This potential has led to studies on the reliability of power electronics components in a module-mounted environment [23,24]. Power inductors also mitigate DC voltage ripple and, hence, reduce PV module stress [25] and improve the efficacy of maximum power point tracking (MPPT) [26]. An intrinsic voltage boosting characteristic is another distinct advantage of current-fed conversion. It supports the elimination of the DC-DC converter and step-up transformer stages in DC-AC applications wherein the DC voltage is lower than the output AC peak voltage [27]. This is predominantly the case with fuel cells and PV applications [28]. For the latter, voltage boosting lays the foundation for a single-stage transformerless PV-CSI system [29,30]. Moreover, CSIs’ inductive DC link provides short-circuit protection and increases system safety [31,32].

More electric aircraft (MEA) and electric vehicles (EVs) can also benefit from the advancement of CSI technology. In these systems, higher power densities are attained by increasing the electric machine (EM) rotational speed [33]. Increased shaft speed corresponds to a higher motor drive frequency, which in turn results in slimmer DC links. Furthermore, it has been demonstrated that improved performances can be achieved with EMs designed for higher rated voltages. CSIs feature low output voltage THD and favourable $dv/dt$, which applies less stress on EM terminals and prevents winding insulation ageing [34] and insulation failure [35]. These features, combined with their voltage boosting characteristics, make CSIs a viable choice for low DC voltage transport drives [14].

Other applications that can benefit from CSI integration appear in the literature. Fuel cell stacks feature low output DC voltage that varies according to operating conditions. A single-stage CSI can boost the low output voltage to the higher peak line voltage while regulating the voltage variations [27]. Current-fed conversion has also been proposed for wind turbine power conversion due to its simple configuration, low device count, low $dv/dt$, reliable short-circuit protection, and inherent four-quadrant operation [36]. Another field in which CSI can prove advantageous is superconducting magnetic energy storage (SMES) systems [37]. SMES systems’ lossless inductive characteristic render them a strong candidate for replacing the traditional CSI DC link. By integrating SMES into CSIs, energy can flow in the absence of lossy power inductors while providing more reactive power compared to VSIs [38]. For similar reasons, the integration of SMES coils has been suggested for CSI-fed wind turbine systems [39]. Finally, the application of CSI-based static synchronous compensators (STATCOMs) has shown to posses a dynamic response comparable to that of VSI while attaining excellent steady-state tracking [40].

Various multilevel single-phase CSIs as well as their application to module-integrated and three-phase PV systems have been covered in the literature, the significance of which are described below. Ref. [41] provides a comprehensive review of CSI-based conversion systems for PV applications. Another study focusing on multi-stage CSI-based grid-connected PV systems is given in [42]. The paper outlays CSIs’ improved gain, performance, energy quality, and lifetime and thereby emphasises their viability in renewable applications. A current-source grid inverter for a hybrid PV and SMES energy system is described in [43]. The hybrid system shares a single CSI, which offers simplified control of the AC side. A three-level CSI topology employing a single inductor, five switches, and a freewheeling diode is proposed in [44]. A SiC-based implementation of this inverter is then presented in [45], wherein system reliability is analysed in light of load overvoltage. Another transformerless single-phase three-level topology is introduced in [46] for PV systems. The proposed CSI mitigates leakage current by coupling the grid neutral line to the negative terminal of the PV panel. Mitigating leakage current in transformerless grid-tied PV systems is of utmost importance, as leakage current may result in grid current distortion, power losses, and safety issues [47]. Another work addressing the same phenomenon is presented in [48], wherein the reduction of ground leakage current is gained by adding auxiliary switches to a fully bridged CSI. A unidirectional n-level CSI cell is presented in [49]. Its five-level configuration employs eight switches and three inductors to generate the desired output levels. An equivalent bidirectional nine-level version of the inverter is shown in [50]. Its reduced bidirectional five-level equivalent circuit can be derived, for which eight switches and two inductors are required to generate a five-level output. Another five-level CSI structure was proposed in [51]; it employs a symmetrical circuit with eight switches and two inductors. The paper also provide a generalised circuit capable of generating n-levels. A three-phase seven-level CSI topology from which a single-phase equivalent circuit can be derived is proposed in [52]. The reduced single-phase topology makes use of four inductors and eight switches to generate five current levels. A simplified topology of the one presented in [49] is proposed in [53]. This topology employs six switches and a single inductor to generate five output levels.

This paper proposes a novel CSI topology utilising eight switches and two inductors for the generation of five distinct current levels. By offsetting the inductor currents from a binary $1:2$ to a trinary $1:3$ ratio, the inverter can generate seven output levels. The inverter can also operate in a single inductor mode while generating the same output levels at the cost of increasing the inductor current ripple. Different from the above-mentioned papers, the balancing mechanism for the inductor currents is analysed in detail for both dual- and single-inductor operation. Furthermore, a preliminary analysis of switches’ stress and power loss is given. In order to verify the functional operation of the inverter, a laboratory prototype was developed and tested in an open-loop mode; the results closely match those of the theoretical and simulative analysis.

The rest of the paper is structured as follows: Section 2 presents the proposed CSI circuitry alongside its switching states and corresponding conduction paths. The section also mathematically analyses the dynamics of the inductor currents and provides a mechanism for their balancing. In Section 3, the simulation results of a Simulink/MATLAB model are presented and analysed. Section 4 provides verification of the theoretical and simulation sections in terms of the experimental results. Finally, conclusions emphasizing the main results and advantages of the proposed inverter are given in Section 5.

2. Materials and Methods

Figure 1 shows a schematic of the proposed current-source inverter. As seen in the figure, the inverter consists of two inductors and eight reverse-blocking switches. Each switch is realised using a transistor–diode pair connected in series. Switches $S_{12}$, $S_{13}$, $S_{22}$, and $S_{23}$ operate as H-Bridge (HB) converters that reverse the output current at each fundamental half-cycle.

2.1. Inverter Switching States

Table 1. Switch states for the various output current levels.

${\mathit{S}}_{11}$	${\mathit{S}}_{12}$	${\mathit{S}}_{13}$	${\mathit{S}}_{14}$	${\mathit{S}}_{21}$	${\mathit{S}}_{22}$	${\mathit{S}}_{23}$	${\mathit{S}}_{24}$	${\mathit{V}}_{{\mathit{L}}_1}-{\mathit{V}}_{{\mathit{L}}_2}$	${\mathit{i}}_{\mathit{o}}$
1	1	0	0	1	0	1	0	0	$I_d$
1	1	0	0	0	0	1	1	$-v_o$	$I_{d}2$
0	1	0	1	1	0	1	0	$+v_o$
0	0	0	1	0	0	0	1	0	0
0	0	1	1	1	1	0	0	$-v_o$	$-I_{d}2$
1	0	1	0	0	1	0	1	$+v_o$
1	0	1	0	1	1	0	0	0	$-I_d$

lists the practical switching states of the proposed inverter, while Figure 2 depicts their corresponding conduction paths. An ideal DC current source of magnitude $I_d$ is assumed throughout this section. For simplicity’s sake, inductor currents $i_{L_1}$ and $i_{L_2}$ are each assumed to carry half the source current $I_d/2$.

Figure 2a depicts the conduction path of inverter output current $I_d$. In this state, switches $S_{11}$ and $S_{21}$ each carry half the source current. The currents are then merged, delivered to the load, and fed back to the source using switches $S_{12}$ and $S_{23}$.

Figure 2b depicts one of the two possible conduction paths for output current $I_d/2$. Here, inductor current $I_{L_1}$ is driven to the load via $S_{11}$ and $S_{12}$ and then fed back to the source via $S_{23}$. Inductor current $I_{L_2}$ is fed back through $S_{24}$ directly to the source. Another switching state delivering $I_d/2$ to the load is shown in Figure 2c. Similar to the previous state, inductor current $I_{L_2}$ is fed to the load and back to the source through switches $S_{21}$, $S_{12}$, and $S_{23}$, while inductor current $I_{L_1}$ is fed back directly to the source through $S_{14}$. The above switching states refer to the positive current half-cycle for which HB switches $S_{12}$ and $S_{23}$ are on at all times.

The zero-current state is illustrated in Figure 2d. Here, inductor currents $I_{L_1}$ and $I_{L_2}$ are fed back to the source through, respectively, switches $S_{14}$ and $S_{24}$. It should be noted that the zero-current state is independent of the state of HB switches $S_{12}$, $S_{13}$, $S_{22}$, and $S_{23}$, which can be set according to practical considerations.

The switching states for the negative current half-cycle are shown in Figure 2e–g. Reversing the inverter output current is accomplished by toggling the HB switches so that switches $S_{12}$ and $S_{23}$ are turned off, while switches $S_{13}$ and $S_{22}$ are turned on at all times.

Similar to the positive case, output current $-I_d/2$ can be realised using two different switching states. The first state is shown in Figure 2e, whereby inductor current $I_{L_2}$ is routed through switches $S_{21}$ and $S_{22}$ to the load and back to the source via $S_{13}$. In this state, inductor current $I_{L_1}$ is fed back directly to the source via $S_{14}$. Output current $-I_d/2$ can also be attained by turning on switches $S_{11}$, $S_{22}$, and $S_{13}$ as shown in Figure 2f. Here, inductor current $I_{L1}$ is fed back to the source via $S_{24}$.

Finally, output current $-I_d$ is realised through the conduction path depicted in Figure 2g. Similar to the positive case, inductor currents $i_{L_1}$ and $i_{L_1}$ flow through, respectively, switches $S_{11}$ and $S_{11}$, are merged and routed to the load via $S_{22}$, and are fed back to the source through $S_{13}$.

The above analysis relates to binary inverter operation wherein a current of the same magnitude $I_d/2$ is flowing through inductors $i_{L_1}$ and $i_{L_2}$. By asymmetrically dividing the source current between the inductors such that a trinary current ratio $i_{L_1}:i_{L_2}=1:3$ is obtained, a seven-level CSI is derived. This can be easily deduced by offsetting the inductor currents accordingly and following the analysis given in this section. It is not within the scope of this paper to analyse the means of current offsetting or to analyse the effect on the inverter’s operation in light of it.

2.2. Inductor Current Balancing

For the inverter to operate normally, inductor currents must be balanced within a fundamental cycle. This is maintained by selectively employing the redundant switching states for output currents $i_o=\pm I_d/2$ as depicted in Figure 2. From Kirchhoff’s current law, we get

$$i_{L_1}+i_{L_2}=I_d$$

(1)

for all switching states illustrated in Figure 2. Applying Kirchhoff’s voltage law to Figure 2b,e yields

$$v_{L_1}-v_{L_2}=-v_o$$

(2)

which results in

$$L_1\frac{d{i}_{L_1}}{dt}-L_2\frac{d{i}_{L_2}}{dt}=-v_o$$

(3)

Substituting (1) into (3), the following equation can be derived:

$$\frac{d{i}_{L_1}}{dt}=-\frac{v_o}{L_1+L_2}$$

(4)

Similarly, applying the above analysis to Figure 2c,f, we get

$$\frac{d{i}_{L_1}}{dt}=+\frac{v_o}{L_1+L_2}$$

(5)

Based on (4) and (5), the following rule for the balancing of inductor currents can be derived:

$$S_{11}=S_{24}=\frac{1+sgn\left(i_o\right)sgn\left(v_o\right)sgn\left(i_{L_1}-i_{L_2}\right)}{2},\left\{i_o=\pm \frac{I_d}{2}\right\}$$

(6)

where $sgn\left(\right)$ denotes the sign function:

$$sgn\left(x\right)=\left\{\begin{array}{cc}+1& x⩾0\\ -1& x<0\end{array}\right.$$

(7)

and $S_{11}=S_{24}=\overline{S_{21}}=\overline{S_{14}}$ for inverter output currents $\pm I_d/2$.

HB switches are determined according to the output current polarity as follows:

$$S_{12}=S_{23}=\frac{1+sgn\left(i_o\right)}{2}$$

(8)

while $S_{13}=S_{22}=\overline{S_{12}}=\overline{S_{23}}$ regardless of the output current.

It should be noted that the above analysis can be adapted for single-inductor operation of the inverter. In this case, one of the inductors is replaced by a short circuit, while the current of the remaining inductor is balanced to half the source current. Current balancing in single-inductor operation mode follows similar lines to that of the dual-inductor operation described above. In this case, for intermediate current levels $i_o=\pm I_d/2$, the instantaneous load voltage can be applied to a single inductor in either polarity by appropriately selecting between redundant switching states. Thus, (4) and (5) are reduced to

$$\frac{d{i}_{L_1}}{dt}=\pm \frac{v_o}{L_1}$$

(9)

where the positive and negative signs correspond to, respectively, Figure 2b,e and Figure 2c,f. The resulting balancing rule then becomes

$$S_{11}=S_{24}=\frac{1+sgn\left(i_o\right)sgn\left(v_o\right)sgn\left(i_{L_1}-i_{s}2\right)}{2},\left\{i_o=\pm \frac{I_d}{2}\right\}$$

(10)

where $i_s$ is the instantaneous current supplied by the source. It should be noted that in this case, the single inductor will experience a voltage drop equal in magnitude to the full extent of the instantaneous load voltage. As a result, its current derivative will double, leading to increased current ripple compared to the dual-inductor case.

2.3. Sizing Considerations

While transistor sizing is not within the scope of this paper, it is worth dwelling on two key factors affecting transistor rating: namely, switching frequency and maximum current. As described above, the maximum current carried by HB switches equals the source current $I_d$. Since HB switches determine the polarity of the output current, they commutate at the fundamental frequency: toggling every half-cycle of the output current.

Switch pairs $\left\{S_{11},S_{14}\right\}$ and $\left\{S_{21},S_{24}\right\}$ direct, respectively, inductor currents $i_{L1}$ and $i_{L2}$ through and away from the load. Hence, they carry a maximum current equal to half the source current $I_d/2$. These switches operate at the carrier frequency.

The above characteristics are summarised in

Table 2. Sizing factors.

Switches	Maximum Current	Switching Frequency	Role
$S_{12},S_{13},S_{22},S_{23}$	$I_d$	$f_0$	HB
$S_{11},S_{14},S_{21},S_{24}$	$I_{d}2$	$f_{\Delta }$	non-HB

, where $f_0$ and $f_{\Delta }$ denote, respectively, the fundamental and carrier frequencies.

As the power loss of a switch is directly related to the product of the current flowing though it and its switching frequency, the above combination supports a moderate rating choice for both HB and non-HB switches.

3. Simulation Verification

A Simulink/MATLAB R2023b model was developed to verify the operation of the proposed converter. Sine-PWM (SPWM) was used to generate the gating signals for the various transistors. For simplicity’s sake, the DC current source was implemented using an ideal DC voltage source with a magnitude of 15 V connected in series with a 100 mH inductor. The simulation parameters are summarised in

Table 3. Simulation parameter summary.

Parameter	Value	Units	Comments
$f_0$	50	Hz	Fundamental frequency
$f_{\Delta }$	1050	Hz	Carrier frequency
$V_s$	15	${\mathrm{V}}_{\mathrm{DC}}$	Source voltage
$L_s$	100	mH	Source inductance
$R_{load}$	$22.5$	$\Omega$	Load resistance
$C_f$	140	uF	Filter capacitor

.

Normal inverter operation requires the balancing of inductor currents $i_{L1}$ and $i_{L2}$. This was attained by employing a simple hysteresis control that implemented the balancing rule developed in Section 2.2.

Inverter output current $i_{INV}$ and inductor currents $i_{L1}$ and $i_{L2}$ are shown in Figure 3. As expected, the inverter output current features five discrete levels, while inductor currents $i_{L1}$ and $i_{L2}$ fluctuate around their $1A$ DC level.

Figure 4 depicts the load voltage $v_o$ in the time and frequency domains. As can be seen in Figure 4a, $v_o$ features a sinusoidal waveform with a very low $dv/dt$ and a peak voltage of 30 V. Recalling the 15 V magnitude of the DC source, the amplified output voltage to some extent reflects the voltage boosting capability of the proposed inverter. Analysis of the inverter voltage boosting ratio as well as the modulation scheme for realising it is outside the scope of this paper and will be addressed in a future publication.

The normalised harmonic content of the load voltage is shown in Figure 4b,c. Close examination of these figures reveals two notable features. The first is a dominant harmonic component of the 21st order and with an amplitude of about $1.75\%$ of the fundamental component. This is coherent with the 1050 Hz carrier frequency listed in Table 3. The second feature is a normalised third harmonic component with an amplitude of $1\%$. This is an outcome of a low current oscillation originating from the inverter interaction with the current source (constructed from a DC voltage source in series with a choke inductor). The load voltage THD index was $2.28\%$.

4. Experimental Verification

This section presents selected experimental results for the verification of the theoretical and simulation sections. All waveforms were captured using an R&S RTM3000 oscilloscope and imported to the MATLAB environment for spectral analysis and figure generation. Current and voltage waveforms were acquired using, respectively, Keysight’s current probe N2893A and voltage probe N2791A.

The experimental setup is depicted in Figure 5. The functional performance of the proposed inverter was investigated using the SiC-MOSFET-based laboratory prototype shown in Figure 5a. As can be seen, the proposed inverter was implemented using two-layer 100 mm × 100 mm PCB. For testing flexibility, the load, inductors, and DC source were kept external to the switching circuit and were interfaced to the inverter via designated connectors. A two-layer PCB arrangement was chosen such that the gate driver boards connect perpendicularly to the motherboard through connectors residing adjacent to the MOSFET’s source and drain terminals. As with the simulation, the current source was implemented using a laboratory DC voltage source with a magnitude of 15 V connected in series with a 100 mH choke inductor. The experimental parameters are summarised in

Table 4. Experimental parameter summary.

Parameter	Value	Units	Comments
$f_0$	50	Hz	Fundamental frequency
$f_{\Delta }$	1050	Hz	Carrier frequency
$t_{dt}$	$0.5$	us	Off-delay
$V_s$	15	${\mathrm{V}}_{\mathrm{DC}}$	Source voltage
$L_s,L_1,L_2$	100	mH	Source and coil inductances
$R_{load}$	$22.5$	$\mathrm{\Omega }$	Load resistance
$C_f$	140	uF	Filter capacitor
$SiCMOSFET$	$C3M0065100K$		Wolfspeed
$Curretnprobe$	$N2893A$		Keysight
$Voltageprobe$	$N2791A$		Keysight
$Controller$	$F28379D$		C2000 Delfino MCU
$Diode$	$C4D10120D$		Wolfspeed
$Currenttransducer$	$LA55-P$		LEM
$Voltagetransducer$	$LV25-P$		LEM

.

Inductor current balancing was maintained using the scheme depicted in Section 2.2. To this end, measurements of the load voltage and inductor currents were acquired using, respectively, LEM’s current transducer $LA55-P$ and voltage transducer $LV25-P$. The acquired measurements were then fed to the ADC module of a TI F28379D evaluation board, wherein a simple hysteresis control was implemented. In the case of the voltage measurement, additional shift-and-scale circuitry was required to adjust the voltage transducer AC output to the acceptable voltage range at the ADC input. The balancing index was then fed to a PWM modulator to determine, amongst other things, gate signals $S_{11}$, $S_{14}$, $S_{21}$, and $S_{24}$ according to (6).

Figure 6 shows the experimental waveforms for the inverter output current $i_{INV}$ and inductor currents $i_{L1}$ and $i_{L2}$. As with the simulation case, $i_{INV}$ shows five discrete levels. Similar to the simulated inductor currents, $i_{L1}$ and $i_{L2}$ fluctuate around a $1A$ average, although the peak–peak value of both currents is substantially larger than the simulated one. This is an outcome of low-frequency oscillations in the source current and the combined effect of measurement and quantization errors. The measurement errors are a result of sensor errors, shift-and-scale distortions, and EMI emitted by the inverter.

The fluctuating currents reflect the inverter operation and increase the harmonic content of its output current. This can be mitigated by increasing inductances and operating the inverter in a closed-loop mode.

Figure 7 shows the load voltage $v_o$ in the time and frequency domains. As depicted in Figure 7a and in accordance with the simulation results illustrated in Section 3, $v_o$ features a sinusoidal waveform with low $dv/dt$ and a peak voltage of $30V$. Here again, the $15V_{DC}$ is amplified to a $60V_{pp}$ output voltage, which emphasis the inverter’s voltage boosting capability.

The normalised harmonic content of $v_o$ is shown in Figure 7b,c, which depict, respectively, 100 and 40 lower-order harmonics of the output voltage. As with the simulation results, the largest harmonic component of the output voltage appears at the switching frequency and amounts to $1.65\%$ of the fundamental amplitude. The load voltage features a THD of $3.7\%$, which is higher than the one attained in the simulation model. This is attributed to the larger fluctuations of the inductor currents arising from looser inductor balancing and the control system’s measurement and quantification errors. These fluctuations also impair the symmetry of the inverter current, which, in turn, results in a small DC component, as can be seen in Figure 7b,c.

As can be inferred from Table 1, the following relations hold for the case of zero off-delay.

$$S_{11}=\overline{S_{14}},S_{12}=S_{23},S_{21}=\overline{S_{24}},S_{22}=S_{13}$$

(11)

From (11), neglecting the off-delay effect, switches $S_{11}$, $S_{12}$, $S_{21}$, and $S_{22}$ provide a complete picture of the inverter switching states and directly reflect the state of the other four switches. Hence, the acquisition of only four gate waveforms is required.

Figure 8 shows the gating signals for switches $S_{11}$, $S_{12}$, $S_{21}$, and $S_{22}$. As described above, neglecting the off-delay effect, these waveforms are identical to, respectively, those of switches $\overline{S_{14}}$, $S_{23}$, $\overline{S_{24}}$, and $S_{13}$. For probing convenience, all waveforms were measured at the ePWM pins of the TI F28379D controller board.

Gating signals for switches $S_{11}$ and $S_{21}$ are depicted, respectively, in Figure 8a,c. Corresponding to the analysis given in Section 2.3, these switches, as well as their complementary switches $S_{14}$ and $S_{24}$, commutate at the carrier frequency.

The gating signals for switches $S_{12}$ and $S_{22}$ are shown, respectively, in Figure 8b,d. As can be seen, these switches commutate at a low fundamental frequency. Their twin switches $S_{23}$ and $S_{13}$ commutate at the same frequency.

To summarise, switches $S_{11}$ and $S_{21}$ (and hence also switches $S_{14}$ and $S_{24}$) carry half the source current and switch at the high carrier frequency. On the other hand, switches $S_{12}$ and $S_{22}$ (and hence also switches $S_{13}$ and $S_{23}$) carry the full source current and switch at a low fundamental frequency. This verifies the analysis summarised in Table 2. As the switching loss is proportional to the product of the current flowing through the switch and its switching frequency, the above observations result in a relatively moderate rating for both the HB and non-HB switches.

It is worth pointing out the extra commutation of switches $S_{12}$ and $S_{22}$ near the zero crossing of the inverter output current. These commutations are an outcome of toggling between the zero and intermediate current states $\pm I_d/2$. This can be cancelled altogether by applying a conditional switching rule that matches the correct HB switching state to each half-current cycle.

5. Conclusions

In this study, a novel single-phase five-level CSI topology was introduced. The proposed inverter utilizes eight switches and two DC link inductors to generate five distinct current levels at its output. The proposed CSI features a symmetrical structure and operates with the source current evenly divided between its two inductors. By offsetting the inductor currents from a 1:2 ratio to a 1:3 ratio, the proposed circuit can generate seven current levels. Furthermore, the proposed CSI can operate in single-inductor mode while generating the same number of output levels. This, on the other hand, comes with the cost of doubling the inductor current ripple.

An analysis of the inverter’s functional operation was provided alongside its switching states and corresponding conduction paths. A mathematical analysis of the inductor current’s dynamics as well as the algorithm for its balancing was detailed and verified. The balancing of inductor currents is achieved by employing redundant switching states. A mechanism for inductor current balancing was also provided for the case of single-inductor operation.

The proposed inverter employs an HB submodule to reverse the output current’s polarity. As analysed and verified, the four HB switches thus commutate at the low fundamental frequency while carrying the full source current. The four non-HB switches, on the other hand, switch at the high carrier frequency while carrying half the source current. This favourable feature averages the switching loss of the HB and non-HB switches, allowing for a relatively moderate switch rating.

Open-loop inverter operation and a simple hysteresis control for the balancing of inductor currents were verified by both simulation and experimental means. The testing conducted on a fully functioning laboratory prototype showed high correlation with both the theoretical and simulation sections. While the full extent of the inverter’s voltage boosting capabilities can only be assessed through employing a space vector modulation technique, a stationary operating point with a voltage boost ratio of $1:4$ was demonstrated in both the simulation and the experimental sections.

Future work will focus on closed-loop operation, loss modelling, sizing, and analysis of the inverter voltage boosting capability through a designated modulation scheme.