A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

Round 1

Reviewer 1 Report

Dear Authors,

please find here after my comments/suggestions:

- However, as CMOS devices enter the 17
nanoscale region, difficulty with matching in the presence of increased variability becomes 18
more critical.The capacitor mismatch between the capacitors in DAC severely degraded 19
the linearity of a pipelined ADC.

-> The paper focuses on the capacitor mismatch, so the sentence could be changed as it follows:

"However, as CMOS devices enter the 17
nanoscale region, mismatch between the capacitors in DAC could severely degraded 19 the linearity of a pipelined ADC. "

- are gradually replaced over time

-> have been gradually replaced over time

- Once power on, the ADC is calibrated first

-> Once powered on, the ADC is calibrated first

 - After 40
calibration, the error code is usually stored in one-time-programmable (OTP) or electronic 41
fuse (Efuse) module, it will never change

-> The statement " t will never change" is quite strong. Re-Calibration could

be needed if the temperature changes or if the power supply is noisy. >Please comment about that.

- In this way further relax the power and area 54
requirement.

-> In this way, the power and area 54
requirement cab be relaxed

- It can be seen the curve in practice (red solid line) 75
appears an obvious deviation from the ideal case (black dotted line)

-> The deviation (black dotted line) from the ideal case (red solid line) can be seen from the plot in Fig.xx

-> Attention should be paid when Verr < 0 for the reason 82
that the missing code decreases the ADC performance greatly[ 26 ].

-> More than a missing code, it seem a jump in the DNL. Please comment.

- second stages need to be calibrated for a desired linearity.

-> second stages need to be calibrated for a desidered linearity.

- As shown here in Fig.5 (a), all the top plate of the capacitors in MDAC are 103
applied to a common mode voltage VCM, whereas for the bottom plate, the situation seems 104
to be different.

-> the statement "the situation seems 104
to be different. " should be clarified

- Change the input voltage to a stable input common mode 112
voltage VIN,cm.

-> hanging sentence, please modify it

- When D(i)=1, Ci is switched to VRN , otherwise 114
switched to VRP.

 -> hanging sentence, please modify it

- Once 133 the ADC is power on,

-> Once 133 the ADC is powered on,


- Take the mismatch of C4 into consideration,

->Taking the mismatch of C4 into consideration,

- The error 162 of C4 can be concluded as:

-> The error 162 of C4 is shown ....

- concluded in Table1)

-> shown in Table1)

-> Once get the error code of stage1 and stage2, store it in memory until the normal 179
conversion mode.

-> Once  the error code of stage1 and stage2 is evaluated , it is stored  in memory until the normal 179
conversion mode.

- far exceed the shortcomings.

->exceed by far the shortcomings.

- And the ADC consumes 154mW

-> The ADC consumes 154mW

English should be improved. Please check the list of suggestions

Author Response

Dear Reviewer,

I hope this email finds you well. I am writing to express my heartfelt gratitude for the time and effort you have invested in reviewing our manuscript. Your insights and suggestions have been invaluable in enhancing the quality of our work.

I have prepared a detailed response to your review comments, addressing each point raised and outlining the changes we have made or plan to make in the manuscript. Please find the attachment with the response for your reference.

Thank you once again for your valuable feedback.

Best regards,

Zhenwei Zhang

Author Response File: Author Response.pdf

Reviewer 2 Report

The article “A 16bit 125MS/s pipelined ADC with digital foreground calibration based on capacitor reuse” represents the original work of the authors. In this paper a comprehensive analysis is presented. The results and analysis were obtained on the basis of the presented investigation.

 The proposed calibration method achieves better performance with both lower power budget and less circuit complexity.

 The topic and the data presented are interesting. Also, the investigation is attractive and addresses a specific gap in the field. An overview and discussion of published research in the field of high speed and high resolution analog-to-digital converters provided. Also, it is presented and what has been added to this area (which is important due to increase of the wireless communication) compared to other published material is highlighted. Namely, the results represent proposed calibration method which achieves lower power consumption and less required area.

Although some figures should be improved, the results are clearly presented in this paper.

 The conclusions are consistent with the presented evidence and arguments. Also, they deal with the main question posed. Additionally, used references are appropriate and are mostly recent.

Considering that interesting research is presented the paper should be accepted (after minor corrections).

Some suggestions to the authors:

 -        The paper should be prepared in accordance to the instructions for the authors.

-        In the Abstract:   “…is presented in this letter”. It would be better to write “… paper” or “manuscript”

-        In Introduction:   “…which strongly calls for…”  It would be better to write “… requires”

-        In line 19, there is abbreviation “DAC” but it is note explained, like others “ADC …” . Although someone can know, or predict the meaning, it would be better to explain-write.

-        Table 2 clearly represents the performance comparison with state-of-art ADCs. It may be useful to additionally discuses the comparison and to highlight the proposed solution. It is especially important to emphasize reducing of the area and less circuit complexity.   

-        Minor editing of English language required. Overall, the paper itself can be improved by correcting minuscule grammatical errors, such as missing articles and fixing the improper singular and plural use of suffixes on some nouns and pronouns. Although there aren't many mistakes, fixing the ones that exist will greatly polish up the paper.

-        Minor editing of English language required. Overall, the paper itself can be improved by correcting minuscule grammatical errors, such as missing articles and fixing the improper singular and plural use of suffixes on some nouns and pronouns. Although there aren't many mistakes, fixing the ones that exist will greatly polish up the paper.

Author Response

Dear Reviewer,

I hope this email finds you well. I am writing to express my heartfelt gratitude for the time and effort you have invested in reviewing our manuscript. Your insights and suggestions have been invaluable in enhancing the quality of our work.

I have prepared a detailed response to your review comments, addressing each point raised and outlining the changes we have made or plan to make in the manuscript. Please find the attachment with the response for your reference.

Thank you once again for your valuable feedback.

Best regards,

Zhenwei Zhang

Author Response File: Author Response.pdf

Reviewer 3 Report

In this paper, the authos proposed a foreground calibration technique for pipeline ADC. The calibration happens on the first 2 stages by reconfiguring the MDAC cap array. Here are my comments:

1. The cap variation will be dominated my mismatch instead of process. The reviewer suggests to update line 71: "owing to process variation, the capacitors in MDAC differ from each other"

2. After calibration is done after power up, how would the performance change with VDD or temperature variation? This is a common question for all foreground calibration techniques. As the main error source comes from the cap mismatch,  I don't expect the calibration affected by VDD/temperature change. But it would be more convincing to add post-calibrated SNR vs VDD and SNR vs temp. 

Author Response

Dear Reviewer,

I hope this email finds you well. I am writing to express my heartfelt gratitude for the time and effort you have invested in reviewing our manuscript. Your insights and suggestions have been invaluable in enhancing the quality of our work.

I have prepared a detailed response to your review comments, addressing each point raised and outlining the changes we have made or plan to make in the manuscript. Please find the attachment with the response for your reference.

Thank you once again for your valuable feedback.

Best regards,

Zhenwei Zhang

Author Response File: Author Response.pdf

Reviewer 4 Report

The paper describes a 16bit 125MS/s pipelined ADC with digital foreground calibration.

The manuscript is well written and shows the advantage of having the ADC with digital foreground calibration. The measurements results demonstrate the idea and the performance comparison with the state-of-the-art is good.

The manuscript however need to have some improvements.

1 – Seams that the ADC is noise limited as shown by the SNR. If this is a 16 bit ADC why the noise level is so high ?

2 – Please provide the THD and ENOB for different frequency in Fig 12.

3 – Include the MDAC error amplifier schematic and sizing.

4 – Why the SNDR lowers for higher frequencies ?

5 – Is missing the noise analysis in manuscript.

6 – Is missing the Monte Carlo capacitor mismatch analysis to confirm e effectiveness of the foreground calibration method.

Author Response

Dear Reviewer,

I hope this email finds you well. I am writing to express my heartfelt gratitude for the time and effort you have invested in reviewing our manuscript. Your insights and suggestions have been invaluable in enhancing the quality of our work.

I have prepared a detailed response to your review comments, addressing each point raised and outlining the changes we have made or plan to make in the manuscript. Please find the attachment with the response for your reference.

Thank you once again for your valuable feedback.

Best regards,

Zhenwei Zhang

Author Response File: Author Response.pdf

Round 2

Reviewer 4 Report

The authors have answered to the identified questions, therefore the manuscript can be accepted in present form.