Design and Implementation of 3 kW All-SiC Current Source Inverter

Abstract

In this paper, the optimal design and implementation of a silicon-carbide (SiC) power semiconductor-based current source inverter (CSI) with a power rating of 3 kW focusing on high power density are discussed in detail. The proposed methodology integrates analytical and numerical techniques to optimize the design of passive components, including filter capacitors and the DC-link inductor, and provides a comprehensive analysis of power semiconductor losses. The losses in the DC-link inductor as well as in the output capacitor are strongly dependent on the modulation strategy. Semi-analytical loss models are therefore derived for the most advanced modulation strategy, which are subsequently used to increase volumetric power density. The theoretical findings are experimentally validated using an ultra-compact, high-efficiency 3 kW three-phase CSI prototype operating at up to 100 kHz switching frequency. The experimental results confirm the efficiency of the proposed design and demonstrate its potential for high-power, compact drive applications.

1. Introduction

The adoption of wide-bandgap (WBG) semiconductor switches, such as silicon carbide (SiC) and gallium nitride (GaN), has enabled a substantial increase in the switching frequencies of power electronic converters used in electric drives. These advanced devices not only offer lower conduction losses but also demonstrate superior performance in high-temperature environments [1,2]. However, when WBG devices are used in voltage-source inverters (VSIs), e.g., the two-level six-switch inverter, very fast switching transients can be implemented resulting in high $\raisebox{1ex}{$\mathrm{d}v$}\!\left/ \!\raisebox{-1ex}{$\mathrm{d}t$}\right.$. These high switching transients introduce challenges such as elevated electromagnetic interference (EMI), overvoltages at motor terminals in the case of long motor cables, increased bearing currents, and additional losses in the electric machine [3]. A sinus motor filter connected to the inverter output terminals could help to mitigate the introduced transients, but adds extra volume, cost, and complexity and leads to increased losses and reduced power density.

A promising alternative to the conventional VSI with its limitation is the application of a current source inverter (CSI) topology, as discussed in [3,4,5]. The CSI inherently filters the output quantities, i.e., inverter output voltages and output currents, mitigating the negative effects of high switching frequencies. Comparisons of the pros and cons of the VSI and CSI topology have already been extensively covered in [6,7,8]. Figure 1 shows the basic structure of a three-phase CSI supplied by a buck-stage from a DC voltage source. The DC-link inductor, $L_{\mathrm{dc}}$, is split between the positive and negative DC-rails and serves as the primary energy storage element. By appropriately controlling the buck-stage, the DC-link current, $i_{\mathrm{dc}}$, is maintained at a nearly constant value. Using pulse-width modulation (PWM) in the inverter stage, this constant DC current is then shaped into arbitrary three-phase current waveforms, $i_{\mathrm{a}}$, $i_{\mathrm{b}}$, and $i_{\mathrm{c}}$, which are finally delivered to the load. The capacitors $C_{\mathrm{f}}$ are required for basic operation of the structure and filter the output voltage, thus eliminating the need for additional output filters.

A key advantage of the CSI is its inherent boost capability, allowing for a broader output voltage range compared to VSIs. Furthermore, the filter inductance of the single-phase buck-stage can be shared with the CSI, optimizing the system’s overall design, as shown in Figure 1 [3].

Several publications are already available dealing with the practical design of compact and efficient current source inverter prototypes for low-voltage applications. The authors of [9,10] presented a 2.5 kW three-phase back-to-back CSI prototype based on normally-on SiC JFETs for motor drives. The researchers of [11,12] introduced the design of a compact 5 kW CSI based on back-to-back SiC MOSFETs for the non-isolated grid connection of photovoltaic panels. With their 48 V current source inverter prototype based on back-to-back GaN switches, the authors of [13] showed that CSIs also offer advantages for lower-power applications in axial flux PMSM drives with low inductance. The group that presented [14,15,16], on the other hand, has been using the CSI topology to build a 3 kW grid-connected three-phase integrated modular motor drive (PMSM). Here, too, back-to-back SiC MOSFETs are used for both the rectifiers and the inverter stage. Most recently, the authors of [17,18,19] presented a grid-connected ultra-compact high-efficiency 10 kW back-to-back SiC MOSFET current source rectifier for electric vehicle charging. In addition to the rectifier stage, the prototype also includes the necessary line filter stage to fulfill the requirements of CISPR 11 class A. All the works listed show high-performance converters for their application, but they lack a comprehensive description of an overall design process—e.g., the practical design of individual elements such as filter capacitors, the DC-link inductor, and power semiconductor switches and the losses that occur therein.

Other works deal in more detail with partial aspects of CSIs, with publications [20,21,22,23,24,25,26,27] focusing on layout parasitics and modeling of the power semiconductor losses for CSIs. Additionally, refernece [28] introduces a detailed switching loss model for the later used modulation scheme. The works in [29,30,31,32], on the other hand, present design methods for DC-link inductors that are specifically tailored to CSIs, while [32,33] deal more specifically with the design and modeling of filter capacitor-related quantities. More general theoretical concepts for the design of CSIs are described in [2,34]; however, the aforementioned publications contain theoretical derivations as well.

In this paper, on the other hand, the design concepts of the individual aspects of the CSI are summarized, discussed in detail, and extended by analytical and numerical relationships. All required design steps including the sizing of passive components such as the filter capacitors and DC-link inductor are addressed. The proposed design incorporates a split DC-link inductor and filter capacitors in star (Y) connection to enhance the common-mode performance of the CSI.

A detailed loss analysis is conducted, focusing on the main contributors to system losses, namely, power semiconductor losses (conduction and switching losses) and DC-link inductor losses. Based on the design framework, a laboratory hardware prototype CSI with the specifications given in

Table 1. Prototype specifications.

Parameter	Symbol	Value
Nominal output power	$P_{\mathrm{ac}}$	3 kW
Nominal output voltage	$V_{\mathrm{ac}}$	200 V
Nominal output current	$I_{\mathrm{ac}}$	5 A
DC-link current	${\overline{i}}_{\mathrm{dc}}$	7 A
Design switching frequency	$f_{\mathrm{pwm}}$	100 kHz

is developed, built, and tested. The theoretical findings based on analytical models are then compared to the experimental results taken from the constructed hardware prototype.

As a modulation strategy, a symmetric pulse-width modulation (PWM) scheme with reduced common-mode voltage as described in [28,35,36] is used. For all computations and analyses, unity power factor is assumed. Please note that, although the converter prototype that is presented later contains a buck-stage at the input, only the inverter stage is considered in the presented design process.

2. Basic Operating Principle of CSI

The CSI structure requires power semiconductor switches with reverse voltage-blocking (RB) capability, while conducting current only in one direction, which prevents potentially destructive short- and open-circuit events during commutations. The RB capability can be implemented using different configurations. One approach is the combination of a reverse-conducting switch with a diode in series to implement the RB capability, as shown in Figure 2a for a Si or SiC MOSFET and Figure 2b for a GaN HEMT.

Another approach is the arrangement of two MOSFETs or GaN high-electron-mobility transistors (HEMT) in a back-to-back configuration, as illustrated in Figure 2c,d either in the common source or icommon drain configuration. All these approaches result in increased conduction losses compared to a single switch. Due to the limited voltage blocking capability of today’s commercially available GaN devices, a back-to-back configuration of SiC MOSFETs in common source arrangement is used in the presented prototype, which reduces conduction losses compared to the two diode-based approaches shown in Figure 2a,b.

The reverse blocking switches can also be implemented using IGBTs. Standard IGBTs do not show reverse-blocking capability and specially designed reverse-blocking IGBTs show an increased forward voltage drop and are not widespread. A combination of a conventional IGBT and a diode similar to Figure 2a,b would, of course, be possible; however, it would suffer from the forward voltage drop of two bipolar devices, and the limited switching frequency of a few tens of kHz of these devices would greatly increase the required DC-link inductance, compromising the power density of the prototype system.

The lateral structure of GaN HEMT, on the other hand, allows the implementation of dual-gate monolithic bidirectional switches (M-BDSs) with a shared drift region and two gates for blocking either voltage polarity [37,38,39]. However, for SiC-MOSFETs, a custom implementation as summarized in Figure 2 is required.

Like the VSI, space vector modulation (SVM) or carrier-based modulation (CBM) can be used to generate arbitrary three-phase inverter output currents. Both types of modulation provide similar results for the calculation of the output switching states, whereby SVM is mathematically more complex to execute but allows a more flexible implementation of different modulation schemes. In this work, SVM is used to describe the CSI operating principle, with [20,21] providing a comprehensive description of different optimized SVM techniques. An example of a CBM approach in CSIs can be found in [40].

Unlike the VSI topology with its three bridge-legs, the CSI structure comprises only two fundamental building blocks: the upper three-way switch, formed by ${\mathrm{S}}_{\mathrm{a}+}$, ${\mathrm{S}}_{\mathrm{b}+}$, and ${\mathrm{S}}_{\mathrm{c}+}$, and the lower three-way switch, consisting of ${\mathrm{S}}_{\mathrm{a}-}$, ${\mathrm{S}}_{\mathrm{b}-}$, and ${\mathrm{S}}_{\mathrm{c}-}$ (see Figure 1). The permissible states for these switches ensure that, except during commutations, only one upper and one lower switch is turned on at any given time to conduct the DC-link current.

This constraint results in nine possible switching states, with six active states, meaning that they produce a non-zero current flow for $i_{\mathrm{a}}^{*}$, $i_{\mathrm{b}}^{*}$, or $i_{\mathrm{c}}^{*}$ (e.g., when ${\mathrm{S}}_{\mathrm{a}+}$ and ${\mathrm{S}}_{\mathrm{b}-}$ are turned on). The remaining three states are zero (or freewheeling) states, where the upper and lower switch of the same phase are turned on, resulting in circulating current in the inverter stage but zero current in $i_{\mathrm{a}}^{*}$, $i_{\mathrm{b}}^{*}$, and $i_{\mathrm{c}}^{*}$ (e.g., when ${\mathrm{S}}_{\mathrm{a}+}$ and ${\mathrm{S}}_{\mathrm{a}-}$ are turned on). The respective three-phase currents of each state can then be transformed into the complex current phasor ${\underset{¯}{i}}^{*}$ using the complex Clarke transformation, given as follows [41,42]:

$${\underset{¯}{i}}^{*}=\frac{2}{3}\left[1{\mathrm{e}}^{\mathrm{j}\frac{-2\pi }{3}}{\mathrm{e}}^{\mathrm{j}\frac{2\pi }{3}}\right]·\left[\begin{array}{c}{i}_{\mathrm{a}}^{*}\\ i_{\mathrm{b}}^{*}\\ i_{\mathrm{c}}^{*}\end{array}\right].$$

(1)

The complex representations of the nine different states (${\underset{¯}{i}}_1^{*},\dots ,{\underset{¯}{i}}_9^{*}$) of the CSI are normalized by the average DC-link current ${\overline{i}}_{\mathrm{dc}}$, yielding nine space vectors ${\underset{¯}{\mathrm{I}}}_1,\dots ,{\underset{¯}{\mathrm{I}}}_9$ (e.g., ${\underset{¯}{\mathrm{I}}}_1=\raisebox{1ex}{${\underset{¯}{i}}_1^{*}$}\!\left/ \!\raisebox{-1ex}{${\overline{i}}_{\mathrm{dc}}$}\right.$). A graphical representation of these discrete space vectors in a complex plane representation is shown in Figure 3.

The six space vectors of the active states divide the complex plane into six sectors, $\overline{)\mathsf{Ⅰ}}$ to $\overline{)\mathsf{Ⅵ}}$, with each sector bounded by two space vectors denominated with ${\underset{¯}{\mathrm{I}}}_x$ for the vector in the counter-clockwise direction and ${\underset{¯}{\mathrm{I}}}_y$ in the clockwise direction (e.g., sector $\overline{)\mathsf{Ⅰ}}$ is bounded by ${\underset{¯}{\mathrm{I}}}_x={\underset{¯}{\mathrm{I}}}_6$ and ${\underset{¯}{\mathrm{I}}}_y={\underset{¯}{\mathrm{I}}}_1$). An arbitrary space vector $\underset{¯}{m}=M{\mathrm{e}}^{\mathrm{j}{\phi }_{\mathrm{m}}}$ can be synthesized as a linear combination of the surrounding vectors, i.e., the two vectors bounding the sector in which the desired space vector resides and one zero space vector. In this article, the term modulation index refers to M, the term angle of the modulation index denotes ${\phi }_{\mathrm{m}}$, and the term complex modulation index represents $\underset{¯}{m}$.

In the PWM scheme, within one switching period $T_{\mathrm{pwm}}$, the two states representing the bounding space vectors and one arbitrarily selectable zero space vector are applied for specific durations. These time intervals are denoted by $t_x$ for ${\underset{¯}{\mathrm{I}}}_x$, $t_y$ for ${\underset{¯}{\mathrm{I}}}_y$, and $t_0$ for the zero state, respectively, as illustrated in Figure 3. Please note that the sequence in which each vector is applied within a PWM period impacts switching losses, DC-link current ripple, output voltage ripple, and common-mode voltage, and therefore needs to be chosen wisely.

The resulting average switch node current can be analytically calculated by multiplying $\underset{¯}{m}$ by the DC-link current $\overline{{\underset{¯}{i}}^{*}}={\overline{i}}_{\mathrm{dc}}·\underset{¯}{m}$. A locally averaged three-phase sinusoidal output current is generated by rotating $\underset{¯}{m}$ at a specific angular velocity. As the high-frequency AC component of ${\underset{¯}{i}}^{*}$ is filtered by the filter capacitors, the averaged switch node currents correspond to the inverter’s output currents $(\mathrm{avg}\left({\underset{¯}{i}}^{*}\right)=\underset{¯}{i}$ where $\underset{¯}{i}$ is the complex representation of the output currents $i_{\mathrm{a}}$, $i_{\mathrm{b}}$, and $i_{\mathrm{c}})$ according to Equation (1).

3. Power Semiconductor Losses

This section provides an overview of the losses occurring in the power semiconductor devices used in the CSI. These losses can be separated into switching losses and conduction losses. Section 3.1 examines the switching loss mechanisms specific to the CSI and the proposed modulation scheme. It also presents measurement results obtained from a developed commutation cell prototype, which are then used to estimate the total switching losses of the inverter. The conduction losses of the CSI are addressed in Section 3.2, where a simple thermal model is also introduced to account for the heating effects on the power semiconductor switches.

3.1. Switching Losses

As previously discussed, the fundamental switching process in CSIs differs significantly from that in VSIs. In CSIs, the DC-link current commutates between two upper switches (e.g., from ${\mathrm{S}}_{\mathrm{a}+}$ to ${\mathrm{S}}_{\mathrm{b}+}$), while a single lower switch remains active. Similarly, commutation occurs between two lower switches while an upper switch remains on. Unlike VSIs, where the basic switching cell is a half-bridge, CSIs use a three-way switch as the fundamental building block. This three-way switch consists of either all upper or all lower switches, each enabling current flow in a specific direction. Figure 4 provides a simplified illustration of the current commutation process during a single switching event. In this process, the commutation current $i_{\mathrm{c}}$ represents the DC-link current, while the commutation voltage $v_{\mathrm{c}}$ corresponds to the line-to-line output voltage across the filter capacitors. The polarity of $i_{\mathrm{c}}$ and $v_{\mathrm{c}}$ determines whether the commutation results in a hard or soft switching event. As back-to-back connected MOSFETs are used to implement RB switches, a four-step commutation sequence is required to prevent a short-circuit of the commutation voltage [16]. In Figure 4a, a hard switching event is shown for the commutation between two upper switches when $v_{\mathrm{c}}$ has a positive polarity, and in Figure 4b, a soft-switching transition is given for positive $i_{\mathrm{c}}$ when the commutation voltage $v_{\mathrm{c}}$ is negative. For negative currents, the conditions for hard and soft switching are reversed, depending on the polarity of $v_{\mathrm{c}}$.

In the initial state of both commutation processes, the two switches, ${\mathrm{S}}_x$ and ${\mathrm{D}}_x$, are on, allowing $i_{\mathrm{c}}$ to flow through branch x. Depending on the polarity of $v_{\mathrm{c}}$, either ${\mathrm{S}}_y$ (see Figure 4a) or ${\mathrm{D}}_y$ (see Figure 4b) blocks the voltage in this state. To prevent a short circuit of $v_{\mathrm{c}}$, ${\mathrm{D}}_x$ is turned off in the first step, causing $i_x$ to transition from the MOSFET channel to its body diode. After the diode delay time $t_{\mathrm{dd}}$ elapses, ${\mathrm{S}}_y$ is activated in the second step for the overlap duration $t_{\mathrm{ol}}$, during which both active switches ${\mathrm{S}}_x$ and ${\mathrm{S}}_y$ are turned on simultaneously. In Figure 4a, where $v_{\mathrm{c}}$ is positive, $i_{\mathrm{c}}$ undergoes a hard commutation to branch y immediately. As the current in branch x decays, charge carriers in the ${\mathrm{D}}_x$ junction are cleared (forward recovery), momentarily resulting in negative current flow. Following this, ${\mathrm{D}}_x$ takes over the voltage $v_{\mathrm{c}}$, with its output capacitance oscillating against the inductance of the commutation loop $L_{\mathrm{c}}$. For simplicity, these parasitic elements are omitted from Figure 4. Finally, in the third step, ${\mathrm{S}}_x$ can be turned off losslessly.

In Figure 4b, with negative $v_{\mathrm{c}}$, no immediate action occurs during the overlap period, since ${\mathrm{S}}_y$ can be turned on losslessly and $i_{\mathrm{c}}$ continues to flow through branch x. Once $t_{\mathrm{ol}}$ elapses and ${\mathrm{S}}_x$ is turned off, the current commutates to branch y. During this, the output capacitance of ${\mathrm{S}}_x$ charges with approximately $\raisebox{1ex}{$i_{\mathrm{c}}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$, while the output capacitance of ${\mathrm{D}}_y$ discharges by the same amount. The duration of this process depends on the output capacitance values and the DC-link current. In the fourth step, ${\mathrm{D}}_y$ is turned on in both cases, allowing $i_y$ to transition from the body diode to the MOSFET channel, reducing on-state losses.

It is difficult to accurately model the switching losses of hard and soft switching commutations with data sheet values, and measurement of switching loss energies is essential to accurately model these switching losses.

A detailed description of the switching loss measurement and the resulting modeling of the switching losses can be found in [43]. However, as diodes are used in this publication to achieve the RVB capability of the switching elements and the loss modeling is carried out using a more simplified mathematical model, the switching loss measurement and the results are briefly described again in this paper.

As shown in [43], the simplified configuration displayed in Figure 5b can be used to measure the associated hard and soft switching losses without the need for a complete converter design. In this setup, only the two RB switching elements involved in the commutation process, denoted as ${\mathrm{S}}_x$, ${\mathrm{D}}_x$, ${\mathrm{S}}_y$, and ${\mathrm{D}}_y$, are implemented.

The commutation current $i_{\mathrm{c}}$, i.e., the DC-link current, is injected into the commutation inductor $L_{\mathrm{dc}}$, which emulates the DC-link of a full converter. Meanwhile, the commutation voltage $v_{\mathrm{c}}$, representing the line-to-line output voltage, is controlled via an external voltage source connected to the commutation cell filter capacitance $C_{\mathrm{f}}$. This configuration allows for independent control of $i_{\mathrm{c}}$ and $v_{\mathrm{c}}$, enabling precise characterization of switching losses as a function of these parameters. Unlike the half-bridge circuits commonly used in VSIs or other CSI switching-loss measurements discussed in the literature [24,25,44], this experimental setup requires only a single-pulse test rather than a double-pulse test as the commutation voltage can be directly adjusted by the external voltage source $C_{\mathrm{com}}$. These measurements are crucial, as the switching losses are highly dependent on the commutation loop inductance, which is influenced by the board layout and the physical placement of the switches and filter capacitors.

Therefore, the commutation cell has been designed to closely replicate the layout of the full converter. To achieve this, the filter capacitors were positioned as near as possible to the power semiconductor switches, minimizing the commutation loop inductance and thereby reducing switching losses. The power semiconductor switches used in the measurement (IMBG65R072M1H) were operated with a gate voltage of 18 V during turn-on and $-2$ V during turn-off. In Figure 5c, the total measured switching loss energies across all four involved SiC MOSFETs IMBG65R072M1H conducted on this commutation cell are given as a function of commutation voltage $v_{\mathrm{c}}$.

According to Figure 5c, neither the hard nor the soft switching losses vary significantly with changes in the commutation current $i_{\mathrm{c}}$. In the soft switching region, characterized by negative commutation voltages, the switching energy remains nearly constant and is largely unaffected by the commutation voltage. However, in the hard switching region with positive commutation voltages, the switching losses increase linearly with the commutation voltage. This leads to the development of the simplified analytic switching loss model

$$E_{\mathrm{s}}(v_{\mathrm{c}},i_{\mathrm{c}})=\left\{\begin{array}{cc}{E}_{\mathrm{soft}}=k_{\mathrm{soft}}\hfill & \forall \begin{array}{c}{v}_{\mathrm{c}}<0\&i_{\mathrm{c}}\ge 0\\ v_{\mathrm{c}}\ge 0\&i_{\mathrm{c}}<0\end{array}\hfill \\ E_{\mathrm{hard}}=k_{\mathrm{hard}}{v}_{\mathrm{c}}\hfill & \forall \begin{array}{c}{v}_{\mathrm{c}}\ge 0\&i_{\mathrm{c}}\ge 0\\ v_{\mathrm{c}}<\&i_{\mathrm{c}}<0\end{array}\hfill \end{array}\right.$$

(2)

modeling the dashed lines in Figure 5c.

Based on the presented switching loss measurements, the two parameters for hard and soft switching can be determined as $k_{\mathrm{hard}}=137\mathrm{nJ}{\mathrm{V}}^{-1}$ and $k_{\mathrm{soft}}=6.64$ μJ for the switching cell at hand. It is important to note that this switching loss model focuses exclusively on the two switching elements involved in a single commutation event and does not account for losses caused by the voltage change in the third switch, as discussed in [38]. In this simplified switching loss model, unified switching loss energies are used for all three branches, not considering the fact that commutation between the phases with increased commutation loop inductance may lead to higher switching loss energies.

The total switching losses depend on several factors such as the chosen modulation scheme, the number of switching transitions (which is influenced by the PWM frequency), and the associated commutation voltages and currents for each transition. The switching losses are furthermore affected by the applied commutation sequence. The objective of the modulation scheme is to minimize switching losses, to reduce DC-link current ripple, and to allow for the smallest possible DC-link inductor design, while also keeping the common-mode output voltage as low as possible. Previous studies have compared various modulation schemes with respect to these parameters [20,21,28,35,36,45] and found that the Reduced Voltage Modulation (RVM) strategy (naming scheme according to [28]) yields the lowest switching losses and DC-link current ripple, while also providing the lowest common-mode output voltage. Furthermore, RVM is a symmetric PWM scheme, which simplifies the measurement of DC-link current and output quantities (voltages and currents), as sampling in the middle of the PWM period automatically yields their average values.

Table 2. Switching cycles of the RB semiconductor switches during one PWM period for the RVM strategy in sectors $\overline{)\mathsf{Ⅰ}}$, $\overline{)\mathsf{Ⅱ}}$, and $\overline{)\mathsf{Ⅲ}}$ (cf. Figure 3). Soft switching transitions are indicated by a filled arrow, while hard switching transitions are indicated by an unfilled arrow.

Sector	Condition	Switching Cycle (● ${\mathit{v}}_{\mathbf{c}}>0$, ● ${\mathit{v}}_{\mathbf{c}}<0$)
$\overline{)\mathsf{Ⅰ}}$	$v_{\mathrm{bc}}<0$
	$v_{\mathrm{bc}}>0$
$\overline{)\mathsf{Ⅱ}}$	$v_{\mathrm{ab}}>0$
	$v_{\mathrm{ab}}<0$
$\overline{)\mathsf{Ⅲ}}$	$v_{\mathrm{ca}}<0$
	$v_{\mathrm{ca}}>0$

summarizes the turn-on and turn-off sequences of the inverter’s power semiconductor switches during one PWM period for each sector, based on the polarities of the line-to-line output voltages. The voltages indicated above and below the arrows represent the respective commutation voltage $v_{\mathrm{c}}$ as defined in Equation (2).

If the voltage symbol appears above an arrow, the commutation occurs between two upper switches with a positive commutation current. Conversely, if the voltage symbol is below the arrow, the commutation occurs between two lower switches with a negative commutation current. A positive commutation voltage is indicated by a red color, while a negative commutation voltage is shown in blue. Furthermore, the distinction between hard and soft switching transitions is indicated by filled and unfilled arrows, respectively. Filled arrows represent soft switching events and unfilled arrows represent hard switching events.

Figure 6 illustrates the expected line-to-line output voltage waveforms at unity power factor, with an emphasis on the corresponding voltages for hard and soft switching in sector $\overline{)\mathsf{Ⅱ}}$. At unity power factor, the voltage condition ($v_{\mathrm{ab}}>0$ or $v_{\mathrm{ab}}<0$) for selecting the switching sequence changes at the midpoint of the sector. As a result, the line-to-line voltage with the highest amplitude is never involved in a commutation event in the RVM strategy.

According to the switching scheme presented in Table 2, the commutation current in sector $\overline{)\mathsf{Ⅱ}}$, where $v_{\mathrm{ab}}>0$ (with ${\phi }_{\mathrm{m}}={\displaystyle \frac{\pi }{6}}\dots {\displaystyle \frac{2\pi }{6}}$ for unity power factor), remains positive throughout the sector as switching operations only occur between the three upper switches ${\mathrm{S}}_{\mathrm{a}+}$, ${\mathrm{S}}_{\mathrm{b}+}$, and ${\mathrm{S}}_{\mathrm{c}+}$. This results in two hard switching transitions involving $v_{\mathrm{ab}}$ and $-v_{\mathrm{bc}}$, and two soft switching commutations involving $-v_{\mathrm{ab}}$ and $v_{\mathrm{bc}}$. The switching losses for this commutation sequence averaged over half sector $\overline{)\mathsf{Ⅱ}}$ ($\frac{\pi }{6}\dots \frac{2\pi }{6}$) can therefore be calculated by

$$\begin{array}{cc}\hfill P_{\mathrm{s}}& ={\displaystyle \frac{f_{\mathrm{pwm}}}{\frac{\pi }{6}}}·\underset{\frac{\pi }{6}}{\overset{\frac{2\pi }{6}}{\int }}{E}_{\mathrm{soft}}\left(v_{\mathrm{bc}}\right)+E_{\mathrm{soft}}(-v_{\mathrm{ab}})+E_{\mathrm{hard}}\left(v_{\mathrm{ab}}\right)+E_{\mathrm{hard}}(-v_{\mathrm{bc}})\mathrm{d}\phi \hfill \\ \hfill & ={\displaystyle \frac{3\sqrt{3}{f}_{\mathrm{pwm}}}{\pi }}·\left(k_{\mathrm{soft}}+k_{\mathrm{hard}}·\sqrt{2}{V}_{\mathrm{ac}}\right)\hfill \end{array}$$

(3)

where $f_{\mathrm{pwm}}$ denotes the PWM switching frequency and $k_{\mathrm{hard}}$ and $k_{\mathrm{soft}}$ represent the constants for hard and soft switching, respectively, as defined in the proposed switching loss model in Equation (2). The current ${\overline{i}}_{\mathrm{dc}}$ is the maximum average DC-link current, and $V_{\mathrm{ac}}$ is the maximum RMS value of the output phase voltage. For a switching frequency of $f_{\mathrm{pwm}}=100$ kHz and a maximum RMS output voltage of $V_{\mathrm{ac}}=200\mathrm{V}$, the switching losses can be estimated to $P_{\mathrm{s}}=7.51\mathrm{W}$. If the output voltage is assumed to change linearly with the modulation index, e.g., for resistive loads, the switching losses over the entire output load range can also be estimated. A graphical representation of these losses is shown in Figure 7, where the switching losses are stacked on top of the later calculated conduction losses.

3.2. Conduction Losses

Conduction losses in the CSI are straightforward to calculate, as the DC-link current flows through four devices at any given time: one upper switch, one upper reverse-blocking element, one lower switch, and one lower reverse-blocking element. The average conduction losses per fundamental period T at the output can be estimated by

$$P_{\mathrm{c}}=4·R_{\mathrm{ds}\left(\mathrm{on}\right)}·{\displaystyle \frac{1}{T}}·{\int }_0^T{i}_{\mathrm{dc}}^2\mathrm{d}t$$

(4)

using the device on-resistance $R_{\mathrm{ds}\left(\mathrm{on}\right)}$, as provided in the datasheet. For a constant DC-link current, this simplifies to

$$P_{\mathrm{c}}=4·R_{\mathrm{ds}\left(\mathrm{on}\right)}·{\overline{i}}_{\mathrm{dc}}^2.$$

(5)

The used semiconductor switches are operated with a gate voltage of 18 $\mathrm{V}$ during turn-on and the corresponding on-state resistance at a junction temperature of $T_{\mathrm{j}}=25$ °C is 72 mΩ. For a junction temperature of $T_{\mathrm{j}}=150$ °C, the resistance increases to 101 mΩ. At $T_{\mathrm{j}}=25$ °C, the conduction losses are calculated as $P_{\mathrm{c}}=14.1\mathrm{W}$. In the later-developed prototype, the upper switch of the included buck stage is continuously turned-on and experiences conduction losses. These losses must be modeled as well. The conduction losses in the buck stage can be calculated using the same approach as for the main inverter. Specifically, the conduction losses in the upper switch of the buck stage are given by $P_{\mathrm{c}\mathrm{Shb}+}=R_{\mathrm{ds}\left(\mathrm{on}\right)}·{\overline{i}}_{\mathrm{dc}}^2=3.53\mathrm{W}$.

Considering the thermal management system (heat-sink and fans), the temperature rise—and consequently, the increase in $R_{\mathrm{ds}\left(\mathrm{on}\right)}$ and conduction losses can be estimated iteratively. The first step is to gather the thermal resistance data for each thermal interface. SMD-mounted, bottom-side-cooled MOSFET devices are used—i.e., the thermal resistances of the thermal vias as well as the thermal resistances of the interface material from the PCB to the heat sink have to be considered next to the thermal resistance of the MOSFET itself. According to the technical datasheet, each of the 13 semiconductor switches (12 switches in the inverter and the half-bridge top switch) has a thermal junction-to-case resistance of $R_{\mathrm{th},\mathrm{JC}}=1.07\mathrm{K}{\mathrm{W}}^{-1}$. Not only the thermal resistance of the MOSFETs has to be considered but also the thermal vias beneath the SMD-mounted devices. The thermal resistance of the vias beneath the TO-263-7 packages is estimated to $R_{\mathrm{th},\mathrm{via}}=0.08\mathrm{K}{\mathrm{W}}^{-1}$, and the thermal resistance of the interface pad between the heat sink and PCB is $R_{\mathrm{th},\mathrm{pad}}=0.7\mathrm{K}{\mathrm{W}}^{-1}$. The thermal resistance of the pure-copper heat sink to ambient air, based on its geometry and fan airflow rate of $9.4{\mathrm{m}}^3{\mathrm{h}}^{-1}$, is $R_{\mathrm{th},\mathrm{hs}}=0.27\mathrm{K}{\mathrm{W}}^{-1}$. A graphical representation of the thermal stackup including all thermal resistances is shown in Figure 8.

For simplicity, we assume that all semiconductor switches experience the same losses, regardless of whether the device is acting as an active switch or as a reverse-blocking device. The total thermal resistance $R_{\mathrm{th},\mathrm{tot}}$ from junction to ambient can then be estimated by

$$R_{\mathrm{th}\mathrm{tot}}={\displaystyle \frac{R_{\mathrm{th}\mathrm{JC}}+R_{\mathrm{th}\mathrm{via}}+R_{\mathrm{th}\mathrm{pad}}}{13}}+R_{\mathrm{th}\mathrm{hs}}=0.412\mathrm{K}{\mathrm{W}}^{-1}.$$

(6)

With this thermal resistance, the actual junction temperature can be calculated, which finally impacts conduction losses due to the thermal dependency of the $R_{\mathrm{ds}\left(\mathrm{on}\right)}$. The temperature rise is calculated iteratively using

$$T_{\mathrm{J}}^{\langle n\rangle }=T_{\mathrm{amb}}+\left(P_{\mathrm{s}}+P_{\mathrm{c}}\left(T_{\mathrm{J}}^{\langle n-1\rangle }\right)+P_{\mathrm{c}\mathrm{Shb}+}\left(T_{\mathrm{J}}^{\langle n-1\rangle }\right)\right)·R_{\mathrm{th}\mathrm{tot}}.$$

(7)

In this equation, the iteration starts with an initial junction and ambient temperature of $T_{\mathrm{J}}^{\langle 0\rangle }=T_{\mathrm{amb}}=25$ °C. The relationship between $R_{\mathrm{ds}\left(\mathrm{on}\right)}$ and junction temperature $T_{\mathrm{J}}$ is taken from the manufacturer’s datasheet. After 10 iterations, the change in the resulting increase in temperature converges, and the maximum conduction losses are calculated as $P_{\mathrm{c}}=14.18\mathrm{W}$ and $P_{\mathrm{c},\mathrm{Shb}+}=3.54\mathrm{W}$ at a junction temperature of $T_{\mathrm{J}}=35.4$ °C. This estimation represents the worst-case scenario at a modulation index of $M=1$ and a maximum RMS output voltage of $V_{\mathrm{ac}}=200\mathrm{V}$, where switching losses are the highest.

By assuming a linear resistive load where the output voltage decreases proportionally with the modulation index, the same iterative procedure can be applied across multiple operating points. The resulting power semiconductor losses, including the conduction losses from the previous section for the inverter structure, are displayed in Figure 7.

It can be observed that both the conduction losses of the inverter stage and the upper switch of the half-bridge remain constant across the entire range of modulation indices, despite an increase in switching losses towards higher modulation indices due to elevated switching losses. Conversely, the switching losses, as anticipated, exhibit a nearly linear increase with increasing modulation index. However, total semiconductor losses are predominantly influenced by conduction losses.

4. Design of the Passive Components

This section outlines the design process of the passive components of the CSI, namely, the DC-link inductor and filter capacitors, using the space vector modulation strategy discussed in Section 2. The key design parameters for the filter capacitors are the capacitance value $C_{\mathrm{f}}$, the peak-to-peak voltage ripple $\Delta v_{\max }$, the maximum RMS current $I_{\mathrm{C}\max }$, and the maximum voltage $v_{\max }$ across the capacitors. The design parameters for the DC-link inductor include the inductance value $L_{\mathrm{dc}}$, the peak-to-peak current ripple $\Delta i_{\mathrm{dc}\max }$, the maximum RMS current $I_{\mathrm{dc}\max }$, and the peak current ${\overline{i}}_{\mathrm{dc}\max }$.

The design process for both capacitors and inductors begins with determining the required time intervals for each space vector in the modulation process. Therefore, the sector that contains the desired space vector $\underset{¯}{m}$ must be identified. As already shown in Section 2, $\underset{¯}{m}$ is synthesized as a linear combination of the two adjacent active space vectors ${\underset{¯}{\mathrm{I}}}_x$ and ${\underset{¯}{\mathrm{I}}}_y$, along with a selected zero vector, as specified in Table 2. The time intervals $t_x$ and $t_y$ for the active vectors are calculated by solving

$$\left[\begin{array}{c}{t}_x\\ t_y\end{array}\right]=T_{\mathrm{pwm}}·{\left[\begin{array}{cc}\mathfrak{Re}\left({\underset{¯}{\mathrm{I}}}_x\right)& \mathfrak{Im}\left({\underset{¯}{\mathrm{I}}}_x\right)\\ \mathfrak{Re}\left({\underset{¯}{\mathrm{I}}}_y\right)& \mathfrak{Im}\left({\underset{¯}{\mathrm{I}}}_y\right)\end{array}\right]}^{-1}·\left[\begin{array}{c}\mathfrak{Re}\left(\underset{¯}{m}\right)\\ \mathfrak{Im}\left(\underset{¯}{m}\right)\end{array}\right].$$

(8)

The time interval for the zero space vector $t_0$ can be easily computed via the relationship $T_{\mathrm{pwm}}=t_x+t_y+t_0$. In sector $\overline{)\mathsf{Ⅰ}}$, the three time intervals

$$\left[\begin{array}{c}{t}_{x\mathrm{I}}\\ t_{y\mathrm{I}}\\ t_{0\mathrm{I}}\end{array}\right]=T_{\mathrm{pwm}}·\left[\begin{array}{c}mcos\left({\phi }_{\mathrm{m}}+\frac{\pi }{3}\right)\\ mcos\left({\phi }_{\mathrm{m}}+\frac{5\pi }{3}\right)\\ 1+mcos\left({\phi }_{\mathrm{m}}+\pi \right)\end{array}\right]$$

(9)

can be obtained using Equation (8). Due to the symmetric nature of the presented PWM scheme, the sequence within one PWM period begins with the application of the zero vector ${\underset{¯}{\mathrm{I}}}_0$ for the time interval $\frac{t_0}{2}$. This is followed by ${\underset{\mathrm{¯}}{I}}_x$ or ${\underset{\mathrm{¯}}{I}}_y$ for $\frac{t_x}{2}$ or $\frac{t_y}{2}$, depending on the applied sequence detailed in Table 2 for each sector and a certain line-to-line. The remaining space vector ($t_x$ or $t_y$) is then applied for its full duration, after which the process reverses with ${\underset{¯}{\mathrm{I}}}_x$ or ${\underset{¯}{\mathrm{I}}}_y$ and ends with ${\underset{¯}{\mathrm{I}}}_0$.

4.1. Design of the Filter Capacitors

During a PWM period, the output currents $i_{\mathrm{a}}$, $i_{\mathrm{b}}$, and $i_{\mathrm{c}}$, represented by the complex vector $\underset{¯}{i}$, are assumed to be constant. The complex switch node current ${\underset{¯}{i}}^{*}$ is determined by the applied space vector $\underset{¯}{m}$, which represents the switch state, and the constant DC-link current ${\overline{i}}_{\mathrm{dc}}$. Consequently, the complex current vector flowing into the filter capacitors, ${\underset{¯}{i}}_{\mathrm{C}}$, can be derived using Kirchhoff’s Current Law (KCL) for each time interval. For instance, in Sector $\overline{)\mathsf{Ⅰ}}$ during the interval $t_x$, the capacitor current is expressed as

$${\underset{¯}{i}}_{\mathrm{C}}={\underset{¯}{i}}_{\mathrm{S}}-\underset{¯}{i}={\overline{i}}_{\mathrm{dc}}·{\overline{\mathrm{I}}}_6-{\overline{i}}_{\mathrm{dc}}M{\mathrm{e}}^{\mathrm{j}{\phi }_{\mathrm{m}}}.$$

(10)

This current remains constant over each separate time interval. During active states, the capacitors are charged by $i_{\mathrm{dc}}$, while during zero states, the load current is supplied by the capacitors. The voltage change across the capacitors for each full time interval $t_x$, $t_y$, or $t_0$ can be calculated using the linearized capacitor equation

$$\left[\begin{array}{c}\Delta {\underset{¯}{v}}_x\\ \Delta {\underset{¯}{v}}_y\\ \Delta {\underset{¯}{v}}_0\end{array}\right]={\displaystyle \frac{{\overline{i}}_{\mathrm{dc}}}{C_{\mathrm{f}}}}·\left[\begin{array}{c}({\underset{¯}{\mathrm{I}}}_x-\underset{¯}{m})·t_x\\ ({\underset{¯}{\mathrm{I}}}_y-\underset{¯}{m})·t_y\\ -\underset{¯}{m}·t_0\end{array}\right].$$

(11)

This expression can be evaluated for each sector and transformed back into phase quantities to calculate the phase voltage changes. For Sector $\overline{)\mathsf{Ⅰ}}$, the voltage change in phase a during each full PWM interval is therefore given by

$$\left[\begin{array}{c}\Delta v_{x\mathrm{I}\mathrm{a}}\\ \Delta v_{y\mathrm{I}\mathrm{a}}\\ \Delta v_{0\mathrm{I}\mathrm{a}}\end{array}\right]={\displaystyle \frac{{\overline{i}}_{\mathrm{dc}}{T}_{\mathrm{pwm}}M}{C_{\mathrm{f}}}}·\left(1-mcos\left({\phi }_{\mathrm{m}}\right)\right)·\left[\begin{array}{c}cos\left({\phi }_{\mathrm{m}}+\frac{\pi }{3}\right)\\ cos\left({\phi }_{\mathrm{m}}-\frac{\pi }{3}\right)\\ -cos\left({\phi }_{\mathrm{m}}\right)\end{array}\right].$$

(12)

In Figure 9, the voltage change per time interval in phase a across all sectors is shown for three different modulation indices, $M=1$, $M=\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$3$}\right.$, and $M=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$3$}\right.$. Please note that the waveforms presented illustrate the theoretical voltage changes over complete time intervals when the individual vectors are applied in a sequence. For the modulation scheme outlined in Table 2, certain time intervals are split, such as in sector $\overline{)\mathsf{Ⅰ}}$ when $v_{\mathrm{bc}}>0$, where the interval $t_x$ is halved and the voltage ripple will be smaller than the voltage ripple curves given in Figure 9. To determine the overall voltage ripple envelope, a detailed analysis of the vector sequence is therefore required. The ripple components in phases b and c have the same basic shape but are shifted by $\frac{4\pi }{3}$ and $\frac{2\pi }{3}$, respectively. To compute the peak-to-peak output voltage ripple $\Delta v_{\mathrm{a}}$ in phase a, the modulation scheme and resulting waveforms must be analyzed.

In sectors $\overline{)\mathsf{Ⅰ}}$ and $\overline{)\mathsf{Ⅵ}}$, $\Delta v_{0\mathrm{a}}$ dominates the voltage ripple, as interval $t_0$ is never split in the applied symmetric PWM scheme, resulting in identical maximum ripple values for these sectors. In the other sectors, the calculation is more complex as $\Delta v_{x\mathrm{a}}$ or $\Delta v_{y\mathrm{a}}$ dominate the voltage ripple. For sector $\overline{)\mathsf{Ⅱ}}$ $v_{\mathrm{ab}}<0$, the x-interval splits into two parts, resulting in the application of the sequence $|{\underset{¯}{\mathrm{I}}}_0\to {\underset{¯}{\mathrm{I}}}_x\to {\underset{¯}{\mathrm{I}}}_y\to {\underset{¯}{\mathrm{I}}}_x\to {\underset{¯}{I}}_0|$ according to Table 2. Here, ${\underset{¯}{\mathrm{I}}}_0$ is applied twice for $\raisebox{1ex}{$t_0$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$, resulting in a total application time interval of $t_0$, taking into account the previous and subsequent PWM intervals. The intervals’ center space vector ${\underset{¯}{\mathrm{I}}}_y$ is also applied for its full duration $t_y$, but ${\underset{¯}{\mathrm{I}}}_x$ is applied twice for $\raisebox{1ex}{$t_x$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$, resulting in only half the voltage change $\raisebox{1ex}{$\Delta v_{x\mathrm{a}}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$. This requires the maximum ripple to be determined as $\Delta v_{\mathrm{a}}=\max \left(\left|\raisebox{1ex}{$\Delta v_{x\mathrm{a}}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.\right|,|\Delta v_{y\mathrm{a}}|,|\Delta v_{0\mathrm{a}}|\right)$.

The different cases as well as the cases for the other relevant sectors are summarized in Equation (13), with the filled hexagon areas indicating the applicable equations for unity load power factor. Please note that these areas rotate accordingly for different power factors.

(13)

The mathematical expressions defining the different regions, independent of the load power factor, are provided by

(14)

A graphical representation of the normalized ripple for different modulation indices is given in Figure 10 for the applied modulation strategy also highlighted in Table 2. Note that the steps in the curves at ${\phi }_{\mathrm{m}}=\raisebox{1ex}{$2\pi $}\!\left/ \!\raisebox{-1ex}{$6$}\right.$, $\raisebox{1ex}{$4\pi $}\!\left/ \!\raisebox{-1ex}{$6$}\right.$, $\raisebox{1ex}{$8\pi $}\!\left/ \!\raisebox{-1ex}{$6$}\right.$, and $\raisebox{1ex}{$10\pi $}\!\left/ \!\raisebox{-1ex}{$6$}\right.$ are caused by the transitions of the modulation scheme according to Equation (14).

The maximum output voltage ripple $\Delta v_{\max }=\raisebox{1ex}{${\overline{i}}_{\mathrm{dc}}{T}_{\mathrm{pwm}}$}\!\left/ \!\raisebox{-1ex}{$4C_{\mathrm{f}}$}\right.$ can now be used to select the filter capacitor size. The allowable output voltage ripple $\Delta v_{\max }$ is evaluated using Equation (13) and finally leads to

$$C_{\mathrm{f}}={\displaystyle \frac{{\overline{i}}_{\mathrm{dc}}{T}_{\mathrm{pwm}}}{4\Delta v_{\max }}}.$$

(15)

It should be noted that $\Delta v_{\max }$ for $M\ge \raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$ is independent of the load’s power factor. Furthermore, the maximum voltage $v_{\max }$ across the capacitors can be estimated using the presented derivations. This maximum occurs when the peak voltage ripple coincides with the peak of the fundamental wave due to a non-unity load power factor and can be calculated using

$$v_{\max }=\sqrt{2}{V}_{\mathrm{ac}}+{\displaystyle \frac{\Delta v_{\max }}{2}}.$$

(16)

The instantaneous RMS current through the capacitor in phase a can be computed for any reference space vector $\underset{¯}{m}$ based on the previous derivations and also using Equation (17).

$$I^{*}\left(\underset{¯}{m}\right)={\overline{i}}_{\mathrm{dc}}·\sqrt{{\displaystyle \frac{1}{T_{\mathrm{pwm}}}}·\left[\mathfrak{Re}{\left({\underset{¯}{\mathrm{I}}}_x\right)}^2·t_x+\mathfrak{Re}{\left({\underset{¯}{\mathrm{I}}}_y\right)}^2·t_y\right]}.$$

(17)

The instantaneous RMS value of the output current in phase a can be similarly calculated via the mean value of the output current

$$I\left(\underset{¯}{m}\right)={\displaystyle \frac{{\overline{i}}_{\mathrm{dc}}}{T_{\mathrm{pwm}}}}·\left[\mathfrak{Re}\left({\underset{¯}{\mathrm{I}}}_x\right)t_x+\mathfrak{Re}\left({\underset{¯}{\mathrm{I}}}_y\right)t_y\right].$$

(18)

Consequently, due to the orthogonality of the two signals, the RMS current flowing into the capacitor of phase a

$$I_{\mathrm{C}}\left(\underset{¯}{m}\right)=\sqrt{{\left(I^{*}\right)}^2-{\left(I\right)}^2}$$

(19)

is the geometric difference of the two. For sinusoidal signals, i.e., a rotating space vector, the global RMS values of the currents can be computed as well resulting in the switch node current

$$I^{*}\left(M\right)=\sqrt{{\displaystyle \frac{3{\overline{i}}_{\mathrm{dc}}}{2\pi }}·\underset{0}{\overset{2\pi }{\int }}\mathfrak{Re}{\left({\underset{¯}{\mathrm{I}}}_x\right)}^2·t_x+\mathfrak{Re}{\left({\underset{¯}{\mathrm{I}}}_y\right)}^2·t_y\mathrm{d}{\phi }_{\mathrm{m}}}={\overline{i}}_{\mathrm{dc}}·\sqrt{\frac{2M}{\pi }}.$$

(20)

The RMS value of the output currents can be computed by

$$I\left(M\right)=\sqrt{{\left(M·{\displaystyle \frac{{\overline{i}}_{\mathrm{dc}}}{\sqrt{2}}}\right)}^2-{\left(C_{\mathrm{f}}·2\pi f·V_{\mathrm{ac}}\right)}^2}$$

(21)

where the second part of the geometric difference describes the fundamental frequency current flow through the capacitor at f lowering the maximum achievable output current amplitude at higher frequencies. Consequently, the RMS capacitor current

$$I_{\mathrm{C}}\left(M\right)=\sqrt{{\overline{i}}_{\mathrm{dc}}^2·\left({\displaystyle \frac{2M}{\pi }}-{\displaystyle \frac{M^2}{2}}\right)+{\left(C_{\mathrm{f}}·2\pi f·V_{\mathrm{ac}}\right)}^2}.$$

(22)

is again the geometric difference between the two. Independent of the second term, the maximum RMS capacitor current appears at $M=\frac{2}{\pi }$ and can be calculated by

$$I_{\mathrm{C}\max }=\sqrt{{\left({\overline{i}}_{\mathrm{dc}}·{\displaystyle \frac{\sqrt{2}}{\pi }}\right)}^2+{\left(C_{\mathrm{f}}·2\pi f·V_{\mathrm{ac}}\right)}^2}.$$

(23)

Note that the second term in Equation (23) considering the fundamental component of the capacitor current is typically smaller than the first term if the converter is properly designed. Furthermore, $V_{\mathrm{ac}}$ varies with M and Equation (23) represents a worst-case scenario for the RMS current. The maximum capacitor current $I_{\mathrm{C}\max }$ can be calculated as $3.3\mathrm{A}$ for the converter at hand with $f_{\max }=1$ kHz and $C_{\mathrm{f}}=800$ μF).

Based on Equations (15), (16) and (23), a suitable capacitor array is selected. Due to the challenging AC current requirement of these capacitors, film-type capacitors or C0G/NP0-based ceramic capacitors are required. If the output voltage ripple is limited to <10% of the maximum AC voltage, i.e., $\Delta v_{\max }<28.3\mathrm{V}$ for ${\widehat{V}}_{\mathrm{ac}}=\sqrt{2},V_{\mathrm{ac}}$, the minimum filter capacitance can be calculated to $C_{\mathrm{f}}=619\mathrm{nF}$. To further reduce the output voltage ripple, however, a capacitor with $C_{\mathrm{f}}=800\mathrm{nF}$ has been selected.

The output capacitance finally implemented in the prototype using a parallel arrangement of 8 × 100 nF C0G MLCC capacitors (C5750NP02W104J280KA) in 2220 packages rated for 450 V. The maximum RMS current is 3.31 A at 100 kHz, which is well below the 8.675 A current rating per capacitor at 100 kHz.

4.2. DC-Link Current Ripple—Design of DC-Link Inductor

The decisive parameters for the DC-link inductor are the inductance value $L_{\mathrm{dc}}$, the maximum tolerable peak-to-peak current ripple $\Delta i_{\mathrm{dc}\max }$, the maximum inductor RMS current $I_{\mathrm{dc}\max }$, and the maximum inductor peak current ${\widehat{i}}_{\mathrm{dc}\max }$. Evaluation of the DC-link current ripple is more complex than the output voltage ripple due to the dependence on the rectifier stage configuration (AC-DC or DC-DC) and the characteristics of the load. The current ripple also varies with the shape and phase shift of the output voltages. The subsequent derivations are based on the following simplifications:

• The inverter is supplied by a controlled DC voltage $v_{\mathrm{dc}}$ that maintains a constant average DC-link current (excluding the buck stage in the analysis).
• The load is symmetric and the filter capacitors are large enough to minimize voltage ripple, resulting in a purely three-phase sinusoidal output voltage system. This system can be phase-shifted to represent non-unity power factors.

Neglecting converter losses,

$$v_{\mathrm{dc}}·{\overline{i}}_{\mathrm{dc}}=3·V_{\mathrm{ac}}·I_{\mathrm{ac}}·cos\left(\phi \right)$$

(24)

applies where the left side represents the power from the rectifier to the DC-link and the right side represents the average three-phase AC power provided by the inverter stage. Here, $v_{\mathrm{dc}}$ represents the ideal (constant) rectifier stage voltage, ${\overline{i}}_{\mathrm{dc}}$ the ideal constant DC-link current, $V_{\mathrm{ac}}$ the RMS value of the three-phase sinusoidal output voltages, $I_{\mathrm{ac}}$ the RMS three-phase sinusoidal output current, and $cos\left(\phi \right)$ the load power factor. Leveraging the previously established current source inverter operation principle ($I_{\mathrm{ac}}=M·{\overline{i}}_{\mathrm{dc}}·\sqrt{2}$ and $\phi ={\phi }_{\mathrm{v}}-{\phi }_{\mathrm{m}}$), the DC-link voltage required to maintain a constant average DC-link current can be derived by

$$v_{\mathrm{dc}}={\displaystyle \frac{3}{\sqrt{2}}}·M·V_{\mathrm{ac}}·cos\left(\phi \right).$$

(25)

To compute the DC-link current ripple, the actual switch states for each applied space vector during a PWM period must be considered—e.g., when vector ${\underset{¯}{\mathrm{I}}}_6$ is applied, the voltage across $L_{\mathrm{dc}}$ becomes $v_{\mathrm{Ldc}}=V_{\mathrm{DC}}-v_{\mathrm{ab}}$. Each space vector is therefore linked to a line-to-line voltage, such as $V_{\mathrm{V}6}=v_{\mathrm{ab}}$ or $V_{\mathrm{V}1}=-v_{\mathrm{ca}}$. The change in the current during each time interval ($t_x$, $t_y$, $t_0$) of the PWM period can then be calculated for each sector and variant using the relationship

$$\left[\begin{array}{c}\Delta i_{\mathrm{dc}x}\\ \Delta i_{\mathrm{dc}y}\\ \Delta i_{\mathrm{dc}0}\end{array}\right]={\displaystyle \frac{1}{L_{\mathrm{dc}}}}·\left[\begin{array}{c}(V_{\mathrm{DC}}-V_{\mathrm{V}x})·t_x\\ (V_{\mathrm{DC}}-V_{\mathrm{V}y})·t_y\\ (V_{\mathrm{DC}}-V_{\mathrm{V}z})·t_0\end{array}\right].$$

(26)

This results in, e.g.,

$$\left[\begin{array}{c}\Delta i_{\mathrm{dc}x}\\ \Delta i_{\mathrm{dc}y}\\ \Delta i_{\mathrm{dc}0}\end{array}\right]={\displaystyle \frac{T_{\mathrm{pwm}}{V}_{\mathrm{ac}}}{L_{\mathrm{dc}}}}\left[\begin{array}{c}\left({\displaystyle \frac{3}{\sqrt{2}}}m-\sqrt{6}cos\left({\phi }_{\mathrm{m}}+\frac{\pi }{6}\right)\right)·mcos\left({\phi }_{\mathrm{m}}+\frac{\pi }{3}\right)\\ \left({\displaystyle \frac{3}{\sqrt{2}}}m+\sqrt{6}cos\left({\phi }_{\mathrm{m}}-\frac{3\pi }{6}\right)\right)·mcos\left({\phi }_{\mathrm{m}}+\frac{5\pi }{3}\right)\\ {\displaystyle \frac{3}{\sqrt{2}}}m·\left(1+mcos\left({\phi }_{\mathrm{m}}+\pi \right)\right)\end{array}\right]$$

(27)

for sector $\overline{)\mathsf{Ⅰ}}$ with unity power factor ($cos\left(\phi \right)=1$). The DC-link current ripple remains the same in all sectors, but is shifted to the sector’s center accordingly. The resulting current ripples for modulation indices $M=1$, $M=\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$3$}\right.$, and $M=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$3$}\right.$ are shown in Figure 11. It is important to note that the DC-link current ripple is independent of the selection of the applied zero space vector. If a symmetric PWM with symmetrical distribution of the applied space vectors is applied, the DC-link current ripple amplitude (peak-to-peak) $\Delta i_{\mathrm{dc}}$ can be obtained by analyzing the PWM sequence for only half of the interval. Similar to the computation of the output voltage ripple, the maximum current ripple for sector $\overline{)\mathsf{Ⅰ}}$ with $v_{\mathrm{bc}}>0$, according to Table 2, can be calculated using

$$\Delta i_{\mathrm{dc}}=\max \left(\frac{\Delta i_{\mathrm{dc}x}}{2},\Delta i_{\mathrm{dc}y},\Delta i_{\mathrm{dc}0}\right).$$

(28)

The ripple amplitude for the PWM scheme summarized in Table 2 is shown in Figure 12 for various modulation indices. Note that only the normalized ripple is presented, and as $V_{\mathrm{ac}}$ generally depends on M, the modulation index M affects the amplitudes of the ripple components. The maximum value of the current ripple $\Delta i_{\mathrm{dc}\max }$ for $cos\left(\phi \right)=1$ can be calculated by carefully analyzing Equation (26) and results in

$$\Delta i_{\mathrm{dc}\max }\left(M\right)={\displaystyle \frac{V_{\mathrm{ac}}{T}_{\mathrm{pwm}}}{L_{\mathrm{dc}}}}\left({\displaystyle \frac{3\sqrt{2}}{2}}M-{\displaystyle \frac{3\sqrt{6}}{4}}{M}^2\right).$$

(29)

The maximum ripple occurs at $M={\displaystyle \frac{1}{\sqrt{3}}}$ finally resulting in

$$L_{\mathrm{dc}}={\displaystyle \frac{V_{\mathrm{ac}}{T}_{\mathrm{pwm}}}{\Delta i_{\mathrm{dc}\max }}}·{\displaystyle \frac{\sqrt{6}}{4}}$$

(30)

to estimate the required inductance value $L_{\mathrm{dc}}$ of the DC-link inductor. The derived calculation method corresponds to the methods often found in the literature [2,29]. Please note that the current ripple $\Delta i_{\mathrm{dc}}$ can become larger than the value given in Equation (30) for $cos\left(\phi \right)<0.83$.

To prevent saturation of the DC-link inductance, the maximum DC-link current ${\overline{i}}_{\mathrm{dc}\max }$ is required for the design of the inductor and can be calculated by

$${\overline{i}}_{\mathrm{dc}\max }={\overline{i}}_{\mathrm{dc}}+{\displaystyle \frac{\Delta i_{\mathrm{dc}\max }}{2}}$$

(31)

where ${\overline{i}}_{\mathrm{dc}}$ is the mean value of the DC-link current and $\Delta i_{\mathrm{dc}\max }$ is the maximal current ripple given by Equation (30). To estimate winding losses, the RMS value of the DC-link current $I_{\mathrm{dc}}$ is required. However, this value cannot be computed analytically anymore, and numerical algorithms are used instead, which are discussed in the following section for the inductor optimization process.

Design of the Inductor

As shown in Figure 1, the DC-link inductor is split into two physical chokes, each with an inductance of ${\displaystyle \frac{L_{\mathrm{dc}}}{2}}$, to enhance the common mode performance of the circuit. The design method for the DC-link inductors is based on the approach outlined in [32], but has been further improved to better consider the complex DC-link current waveforms appearing in current source inverters.

The design method for the DC-link inductors is based on the approach outlined in [32], which already provides a comprehensive design process and loss modeling method for DC-link inductors based on the worst-case operating points of the CSI for a space vector at one position during standstill. It also greatly simplifies the core loss determination approach by using the standard Steinmetz equation provided in [46,47]. This paper, on the other hand, extends the findings of [32] via a piecewise analysis of the DC-link current waveforms and by using the improved Generalized Steinmetz Equation (iGSE) approach for non-sinusoidal inductor current waveforms in [48,49,50] and a more realistic consideration of a rotating space vector that yields average inductor core and copper losses. The approach for finding an appropriate winding geometry is also improved in this publication.

The optimization process uses commercially available toroidal core geometries and their specifications. Key geometrical parameters such as the mean magnetic path length $l_{\mathrm{m}}$ and the cross-sectional area of the toroid $A_{\mathrm{c}}$ are provided by the manufacturer, as well as the differential relative permeability ${\mu }_{\mathrm{r}}\left(H\right)$. The optimization goal of the design process is to minimize both volume and total losses, which include core losses and winding losses.

In this work, high-performance toroidal powder cores from the manufacturer Magnetics (Materials MPP and Edge) are considered. This manufacturer offers analytically fitted equations for the differential relative permeability curve ${\mu }_{\mathrm{r}}\left(H\right)$, as well as the Steinmetz parameters k, $\alpha$, and $\beta$ for the different materials and cores. The core geometries include the outer diameter $D_{\mathrm{c}}$, inner diameter $d_{\mathrm{c}}$, height $h_{\mathrm{c}}$, core volume $V_{\mathrm{c}}$, cross-sectional area of the core $A_{\mathrm{c}}$, and mean magnetic path length $l_{\mathrm{m}}$. The design process is carried out numerically for each available core geometry, with outer diameters ranging from 4.19 mm to 167.21 mm, and materials with nominal relative permeability between 14 and 550 are considered.

The initial parameters for the optimization procedure include the PWM frequency $f_{\mathrm{pwm}}$, the average DC-link current ${\overline{i}}_{\mathrm{dc}}$, the maximum tolerable DC-link current ripple $\Delta i_{\mathrm{dc}}$, and the maximum RMS output voltage $V_{\mathrm{ac}}$ (all from Table 1). The optimization also incorporates copper and core loss estimation, using the analytically derived DC-link current ripple from Figure 12 at different modulation indices, which allows estimating losses at various operating points next to the worst-case operating point regarding inductor losses. As discussed earlier, the current ripple amplitude changes with the output voltage $V_{\mathrm{ac}}$ and therefore also with the characteristic of the load. In this work, a linear resistive load is assumed where $V_{\mathrm{ac}}=M·V_{\mathrm{ac}\max }$, and therefore, the design process depends on the modulation index M. A flow chart of the proposed design process is shown in Figure 13.

At the beginning of the design process, the relevant input parameters of the converter are collected, including the PWM switching frequency $f_{\mathrm{pwm}}$, the average DC-link current ${\overline{i}}_{\mathrm{dc}}$, the maximum tolerable DC-link current ripple $\Delta i_{\mathrm{dc}\max }$, and the maximum RMS output voltage $V_{\mathrm{ac}}$, and the required DC-link inductance can be calculated using Equation (30). Next, a core with specific permeability and geometry is selected from the core database provided by the manufacturer. With the chosen core and the desired inductance value, the number of turns N is determined, accounting for saturation at the given DC-link current. The inductance value of an inductor based on a toroidal power core is given by

$$L=N^2·{\mu }_{\mathrm{r}}\left(H\right)·{\mu }_0·{\displaystyle \frac{A_{\mathrm{c}}}{l_{\mathrm{m}}}}$$

(32)

where $A_{\mathrm{c}}$ is the core cross-sectional area and $l_{\mathrm{m}}$ is the mean magnetic path length of the toroidal core. The relative permeability ${\mu }_{\mathrm{r}}$ depends on the applied DC-field strength, which is caused by the DC-link current in the core, and can be computed using the empirical analytic relationship

$${\mu }_{\mathrm{r}}\left(H\right)={\displaystyle \frac{0.01·{\mu }_{\mathrm{r}}(H=0)}{a+b·{\left(\frac{H}{79.5775\mathrm{A}/\mathrm{m}/\mathrm{Oe}}\right)}^c}}$$

(33)

as provided by the manufacturer. Here, c and a are empirical parameters and H is the magnetic field strength in $\mathrm{A}{\mathrm{m}}^{-1}$. Note that the actual equation provided has been modified to use SI units. Using the relationship $H\left(N\right)={\overline{i}}_{\mathrm{dc}}·{\displaystyle \frac{N}{l_{\mathrm{m}}}}$ in Equation (33) results in

$$1+\left[100·b·{\left({\displaystyle \frac{{\overline{i}}_{\mathrm{dc}}}{79.5775\mathrm{A}/\mathrm{m}/\mathrm{Oe}·l_{\mathrm{m}}}}\right)}^c\right]·N^c-\left[{\displaystyle \frac{A_{\mathrm{c}}·{\mu }_0·{\mu }_{\mathrm{r}}(H=0)}{L·l_{\mathrm{m}}}}\right]·N^2=0,$$

(34)

which can now be solved for N. As there is no closed-form analytic solution for N, the number of turns must be determined numerically for each core. After calculating the number of turns, the core losses of the inductor can be estimated. To estimate these losses, the manufacturer provides empirical parameters similar to the Steinmetz parameters

$$P_{\mathrm{mW}/\mathrm{c}\mathrm{m}3}=a·{\widehat{B}}^b·f_{\mathrm{pwm}\mathrm{kHz}}^c,$$

(35)

where $P_{\mathrm{mW}/\mathrm{cm}}$ represents the core losses in $\mathrm{mW}{\mathrm{cm}}^{-3}$, $\widehat{B}$ is the peak value of the flux density in the core, $f_{\mathrm{pwm},\mathrm{kHz}}$ is the PWM frequency in kHz, and a, b, and c are empirical parameters. This equation can then be converted to the standard Steinmetz equation [46,47]

$$P_{\mathrm{fe}}=k·f_{\mathrm{pwm}}^{\alpha }·{\widehat{B}}^{\beta }$$

(36)

with parameters $k={\displaystyle \frac{1000·a}{{1000}^c}}$, $\beta =b$, and $\alpha =c$.

As the standard Steinmetz equation is only valid for sinusoidal waveforms, several research groups have developed methods to estimate core losses using the same Steinmetz parameters for non-sinusoidal waveforms [48,49,50], while [51] showed that the DC-bias has only negligible influence on the losses of the used powder cores. The result of these efforts is the improved Generalized Steinmetz Equation (iGSE):

$$P_{\mathrm{fe}}={\displaystyle \frac{1}{T}}·{\int }_0^T{k}_{\mathrm{i}}·{\left|{\displaystyle \frac{\mathrm{d}B}{\mathrm{d}t}}\right|}^{\alpha }·{(\Delta B)}^{\beta -\alpha }\mathrm{d}t.$$

(37)

In this context, $P_{\mathrm{fe}}$ represents the core losses per period T, ${\displaystyle \frac{\mathrm{d}B}{\mathrm{d}t}}$ is the rate of change of the flux density during one magnetization period, and $\Delta B$ is the peak change in flux density during a cycle. The parameters $\alpha$ and $\beta$ are the standard Steinmetz parameters. The new parameter $k_{\mathrm{i}}$ in the improved Generalized Steinmetz Equation (iGSE) can be computed using

$$k_{\mathrm{i}}={\displaystyle \frac{k}{{\left(2\pi \right)}^{\alpha -1}{\int }_0^{2\pi }{|cos\theta |}^{\alpha }{2}^{\beta -\alpha }\mathrm{d}\theta }}.$$

(38)

In a current source inverter, the DC-link current ripple curve changes three times during each PWM interval given by $\Delta i_{\mathrm{dc}x}$, $\Delta i_{\mathrm{dc}y}$, and $\Delta i_{\mathrm{dc}0}$, as shown in Equation (26). These changes depend on the modulation index angle ${\phi }_{\mathrm{m}}$ and the modulation index M. The amplitude of the resulting current ripple waveform is then the maximum of the absolute values of the three current changes. Note that for $V_{\mathrm{ac}}$ in Equation (26), a linear (resistive) load is assumed, with $V_{\mathrm{ac}}=M·V_{\mathrm{ac},\max }$. Each current ripple component, as well as the total current ripple amplitude, can be converted to corresponding flux density ripples using

$$B={\mu }_0·{\mu }_{\mathrm{r}}(N,i)·{\displaystyle \frac{i·N}{l_{\mathrm{m}}}}.$$

(39)

To compute the core losses based on the DC-link current waveform of the CSI, the components $\Delta B$ and $B\left(t\right)$ need to be calculated using the relationship $\mu ={\mu }_0·{\mu }_r$:

$$\Delta B={\displaystyle \frac{\mu N}{l_{\mathrm{m}}}}·\Delta i_{\mathrm{dc}}\mathrm{and}B\left(t\right)={\displaystyle \frac{\mu N}{l_{\mathrm{m}}}}·i_{\mathrm{dc}}\left(t\right).$$

(40)

The results can now be used with the iGSE to compute the core losses for one PWM period:

$$\begin{array}{cc}\hfill P_{\mathrm{fe}}\left(\underset{¯}{m}\right)& ={\displaystyle \frac{k_{\mathrm{i}}}{T_{\mathrm{pwm}}}}·{\left({\displaystyle \frac{\mu N}{l_{\mathrm{m}}}}·\Delta i_{\mathrm{dc}}\right)}^{\beta -\alpha }·{\int }_0^{T_{\mathrm{pwm}}}{\left|{\displaystyle \frac{\mu N}{l_{\mathrm{m}}}}·{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{dc}}}{\mathrm{d}t}}\right|}^{\alpha }\mathrm{d}t\hfill \\ \hfill & ={\displaystyle \frac{k_{\mathrm{i}}·{\left(\frac{\mu N}{l_{\mathrm{m}}}\right)}^{\beta }}{T_{\mathrm{pwm}}}}·\Delta i_{\mathrm{dc}}^{\beta -\alpha }·\left[{\left|{\displaystyle \frac{\Delta i_{\mathrm{dc}0}}{t_0}}\right|}^{\alpha }·t_0+{\left|{\displaystyle \frac{\Delta i_{\mathrm{dc}x}}{t_x}}\right|}^{\alpha }·t_x+{\left|{\displaystyle \frac{\Delta i_{\mathrm{dc}y}}{t_y}}\right|}^{\alpha }·t_y\right].\hfill \end{array}$$

(41)

Considering the known symmetry and $\frac{\pi }{3}$-periodicity of the DC-link current ripple at unity power factor, the calculated ripple components from Equation (26) and the time intervals from Equation (8) can be evaluated using Equation (41). The average core loss over a complete electrical period can then be computed through numerical averaging from ${\phi }_{\mathrm{m}}=0$ to ${\phi }_{\mathrm{m}}=\frac{\pi }{6}$ for different modulation indices M:

$$P_{\mathrm{fe}}\left(M\right)={\displaystyle \frac{6}{\pi }}{\int }_0^{\frac{\pi }{6}}{P}_{\mathrm{fe}}\left(\underset{¯}{m}\right)\mathrm{d}{\phi }_{\mathrm{m}}.$$

(42)

The maximum occurring core losses for each core are then used as the worst case for the following computations. A loss distribution of inductor losses including core losses is given in Figure 14 as a function of modulation index M for the later designed core based on the design input parameters from Table 1. All acquired parameters of the inductor design process are later summarized in

Table 3. Inductor specifications used in this work.

Parameter	Symbol	Value
DC-link current	${\overline{i}}_{\mathrm{dc}}$	7 A
Nominal output voltage	$V_{\mathrm{ac}}$	200 V
Max. DC-link current ripple	$\Delta i_{\mathrm{dc}\max }$	1.05 A (15% ${\overline{i}}_{\mathrm{dc}}$)
PWM switching frequency	$f_{\mathrm{pwm}}$	100 kHz
DC-link inductance	$L_{\mathrm{dc}}$	$2\times 583$ μH
Core	-	59894A2 Edge ${\mu }_r=60$
Number of stacked cores	$N_{\mathrm{c}}$	$2\times 3$ cores
Number of turns	N	$2\times 51$ turns
Wire length	$l_{\mathrm{w}}$	$2\times 4.59$ m
Wire diameter	$d_{\mathrm{w}}$	1 mm
Max. core losses	$P_{\mathrm{fe}\max }$	$2\times 88.8$ mW @ $M=0.72$
Max. AC copper losses	$P_{\mathrm{cu}\mathrm{ac}\max }$	$2\times 53.3$ mW @ $M=0.72$
Max. DC copper losses	$P_{\mathrm{cu}\mathrm{dc}\max }$	$2\times 5.94$ W @ $M=0.72$
Max. temperature rise	$T_{\mathrm{rise}\max }$	45.6 °C @ $M=0.72$

. Here, the core losses are the averaged core losses over one electrical period. Please note that these are the estimated losses for one of the two designed split inductors.

The next step in the inductor design process is the selection of the winding arrangement and geometry. A winding arrangement of several layers is used where the number of layers in the inner side of the core and outer side of the core may differ (cf., Figure 15). In this context, $k_{\mathrm{i}}$ is the number of layers on the inner side of the core and and $k_{\mathrm{o}}$ is the number of layers at the outer side of the core. Also, the number of turns per the inner layer $N_{k,\mathrm{i}}$ may differ from the number of turns at the outer layer $N_{k,\mathrm{o}}$. Please note that the total number of turns on the inner and outer side of the core are equal. To begin this process, a specific wire diameter $d_{\mathrm{w}}$ (with the wire radius designated as $r_{\mathrm{w}}$) is selected from a wire diameter database, along with its associated specific resistance $R_{\mathrm{spez}}$. The process is initiated using the largest possible wire diameter.

This wire diameter is iteratively applied in layers to the inner core section, as shown in Figure 15. The maximum possible inner layer count is $k_{\mathrm{i},\max }=\mathrm{floor}\left({\displaystyle \frac{r}{2r_{\mathrm{w}}}}\right)$, where r is the inner radius of the core, while the number of applicable turns per inner layer, starting from the innermost layer, is given by $N_{k,\mathrm{i}}=\mathrm{floor}\left(\raisebox{1ex}{$\pi $}\!\left/ \!\raisebox{-1ex}{$arcsin\left(\frac{r_{\mathrm{w}}}{r-(2,k_{\mathrm{i}}-1)r_{\mathrm{w}}}\right)$}\right.\right)$. Therefore, the total number of turns applicable in this way is

$$N_{\mathrm{i}\max }=\sum _{k=1}^{k_{\mathrm{i}\max }}=\mathrm{floor}\left({\displaystyle \frac{\pi }{arcsin\left(\frac{r_{\mathrm{w}}}{r-(2k_{\mathrm{i}}-1)r_{\mathrm{w}}}\right)}}\right).$$

(43)

If the calculated number of turns exceeds $N_{\mathrm{i},\max }$, the design cannot be implemented with the chosen wire diameter, and the process is restarted with the next smaller wire diameter. On the other hand, if $N\le N_{\mathrm{i},\max }$, the required turns are distributed onto the layers starting from the innermost one. The last layer can then be fractionally occupied. A similar winding arrangement strategy is applied at the outer side of the core. Due to the larger outer radius R of the core, the number of turns per outer layer $k_o$ can be calculated as $N_{k\mathrm{o}}=\mathrm{floor}\left(\raisebox{1ex}{$\pi $}\!\left/ \!\raisebox{-1ex}{$arcsin(\frac{r_{\mathrm{w}}}{R+(2k_{\mathrm{o}}-1)r_{\mathrm{w}}}$}\right.\right))$. The total length $l_{\mathrm{w}}$ of the wire

$$\begin{array}{cc}\hfill l_{\mathrm{w}}& =\phantom{+}\sum _{k_{\mathrm{i}}=1}^{K_{\mathrm{i}}}{N}_{k\mathrm{i}}·\left(R-r+h+4(2k_{\mathrm{i}}-1)r_{\mathrm{w}}\right)\hfill \\ & \phantom{=}+\sum _{k_{\mathrm{o}}=1}^{K_{\mathrm{o}}}{N}_{k\mathrm{o}}·\left(R-r+h+4(2k_{\mathrm{o}}-1)r_{\mathrm{w}}\right).\hfill \end{array}$$

(44)

increases per wound inner layer $k_i$ and outer layer $k_o$ by the number of windings applied, i.e., $N_k=N_{k,\max }$ for a full layer and potentially less in the last layer.

The inductor volume $V_{\mathrm{L}}$ and the surface area $A_{\mathrm{L},\mathrm{surf}}$ can then be calculated using the core’s outer dimensions, increased by the winding

$$\begin{array}{cc}\hfill V_{\mathrm{L}}& =D_{\mathrm{o}}^2·{\displaystyle \frac{\pi }{4}}·h_{\mathrm{o}}\hfill \\ \hfill A_{\mathrm{L}\mathrm{surf}}& ={\displaystyle \frac{\pi }{2}}·\left(D_{\mathrm{o}}^2-d_{\mathrm{i}}^2\right)+\pi h_{\mathrm{o}}·(D_{\mathrm{o}}+d_{\mathrm{i}})\hfill \end{array}$$

(45)

with the outer diameter $D_{\mathrm{o}}=2,R+k_o·4,r_{\mathrm{w}}$, the inner diameter $d_{\mathrm{i}}=2,r-k_i·4,r_{\mathrm{w}}$, and the outer height $h_{\mathrm{o}}=h+k_i·4,r_{\mathrm{w}}$.

The DC resistance of the wire can be determined via $R_{\mathrm{dc}}=l_{\mathrm{w}}·R_{\mathrm{spez}}$, using the calculated length, where $R_{\mathrm{spez}}$ is the specific resistance of the chosen wire per unit length. The DC copper losses can then be calculated by

$$P_{\mathrm{cu}\mathrm{dc}}={\overline{i}}_{\mathrm{dc}}^2·R_{\mathrm{dc}}.$$

(46)

Due to the skin and proximity effects, the AC resistance $R_{\mathrm{ac}}$ is increased and needs to be estimated. Therefore, the method proposed in [52,53] is applied as described in [30]. An individual AC resistance can be calculated for each harmonic order n of the non-sinusoidal AC current

$$\begin{array}{c}\hfill R_{\mathrm{ac}}^{\langle n\rangle }=R_{\mathrm{dc}}{\displaystyle \frac{\gamma }{2}}\left[{\displaystyle \frac{\mathrm{ber}\gamma {\mathrm{bei}}^{\prime }\gamma -\mathrm{bei}\gamma {\mathrm{ber}}^{\prime }\gamma }{{\mathrm{ber}}^{\prime 2}\gamma +{\mathrm{bei}}^{\prime 2}\gamma }}-2\pi {\eta }^2{\displaystyle \frac{4K-1}{3}}{\displaystyle \frac{{\mathrm{ber}}_2\gamma {\mathrm{ber}}^{\prime }\gamma +{\mathrm{bei}}_2\gamma {\mathrm{bei}}^{\prime }\gamma }{{\mathrm{ber}}^2\gamma +{\mathrm{bei}}^2\gamma }}\right].\end{array}$$

(47)

where

$$\begin{array}{cc}\hfill \delta =& {\displaystyle \frac{1}{\sqrt{\pi n{f}_{\mathrm{pwm}}{\mu }_0\frac{1}{{\rho }_{\mathrm{cu}}}}}}\hfill \\ \hfill \eta =& {\displaystyle \frac{d_{\mathrm{w}}}{t}}\sqrt{{\displaystyle \frac{\pi }{4}}}\hfill \\ \hfill \gamma =& {\displaystyle \frac{d_{\mathrm{w}}}{\delta \sqrt{2}}}\hfill \end{array}$$

(48)

with the following parameters:

• $\delta$…skin depth
• $\eta$…porosity factor
• $d_{\mathrm{w}}$…wire diameter
• n…harmonic order
• $f_{\mathrm{pwm}}$…PWM frequency (fundamental frequency of waveform)
• ${\rho }_{\mathrm{cu}}$…relative conductivity of copper (0.01786 $\Omega {\mathrm{mm}}^2{\mathrm{m}}^{-1}$)
• t…distance between two adjacent conductors (here, $t=d_{\mathrm{w}}$ was assumed)

The functions “ber” and “bei” represent the Kelvin functions based on the Bessel function of the first kind and order $\nu$, $J_{\nu }\left(z\right)$, where

$$\begin{array}{c}\hfill {\mathrm{ber}}_{\nu }x=\mathfrak{Re}\left\{J_{\nu }\left(x{\mathrm{e}}^{\frac{3\pi i}{4}}\right)\right\}\\ \hfill {\mathrm{bei}}_{\nu }x=\mathfrak{Im}\left\{J_{\nu }\left(x{\mathrm{e}}^{\frac{3\pi i}{4}}\right)\right\}.\end{array}$$

(49)

For the zero-order Bessel and Kelvin functions $\nu =0$, the subscript is not written. The required derivative of the zero-order Kelvin functions can be solved analytically using

$$\begin{array}{c}\hfill {\mathrm{ber}}^{\prime }x={\displaystyle \frac{{\mathrm{bei}}_{1}x+{\mathrm{ber}}_{1}x}{\sqrt{2}}}\\ \hfill {\mathrm{bei}}^{\prime }x={\displaystyle \frac{{\mathrm{bei}}_{1}x-{\mathrm{ber}}_{1}x}{\sqrt{2}}}.\end{array}$$

(50)

The harmonic components of the DC-link current (ripple) are computed using a Fourier series analysis, as its shape can be analytically defined by the time intervals $t_x$, $t_y$, and $t_0$ and the corresponding current changes $\Delta i_{\mathrm{dcx}}$, $\Delta i_{\mathrm{dcy}}$, and $\Delta i_{\mathrm{dcz}}$. The general equation for the Fourier series of a periodic signal $x\left(t\right)$ is

$$x\left(t\right)=a_0+\sum _{n=1}^{\infty }{a}_n·cos\left(n\omega t\right)+b_n·sin\left(n\omega t\right),$$

(51)

where $a_0$, $a_n$, and $b_n$ are the Fourier coefficients representing the amplitude of the respective harmonics, and $\omega ={\displaystyle \frac{2\pi }{T}}$ is the angular frequency corresponding to the fundamental period T. The Fourier coefficients can be computed as follows:

$$\begin{array}{c}{a}_0={\displaystyle \frac{1}{T}}·{\int }_{-\frac{T}{2}}^{\frac{T}{2}}x\left(t\right)\mathrm{d}t\hfill \\ a_n={\displaystyle \frac{2}{T}}·{\int }_{-\frac{T}{2}}^{\frac{T}{2}}x\left(t\right)·cos\left(n\omega t\right)\mathrm{d}t\hfill \\ b_n={\displaystyle \frac{2}{T}}·{\int }_{-\frac{T}{2}}^{\frac{T}{2}}x\left(t\right)·sin\left(n\omega t\right)\mathrm{d}t.\hfill \end{array}$$

(52)

As $i_{\mathrm{dc}}$ is a symmetric and periodic function with a period of ${\displaystyle \frac{\pi }{3}}$, the Fourier analysis only needs to consider the interval ${\phi }_{\mathrm{m}}=0\dots {\displaystyle \frac{\pi }{6}}$ for the modulation approach discussed in Table 2 for sector $\overline{)\mathsf{Ⅰ}}$. Due to the nature of the current source inverter, the average value of the DC-link current is given by $a_0={\overline{i}}_{\mathrm{dc}}$. The function also exhibits point symmetry around the center of each PWM period, which implies that $a_n=0$ and only the $b_n$ coefficients are non-zero. The coefficients $b_n$ therefore correspond to the AC current amplitudes at different harmonic orders n. The respective harmonic RMS values concerning Equation (53), given by

$$I_{\mathrm{dc}}^{\langle n\rangle }\left(\underset{¯}{m}\right)={\displaystyle \frac{\sqrt{2}}{T_{\mathrm{pwm}}}}·{\int }_0^{\frac{T_{\mathrm{pwm}}}{2}}{i}_{\mathrm{dc}}(t,\underset{¯}{m})·sin\left(n\omega t\right)\mathrm{d}t,$$

(53)

can then be computed by dividing the peak values by $\sqrt{2}$.

The current waveforms can then be defined piecewise

$$i_{\mathrm{dc}}(t,\underset{¯}{m})=\left\{\begin{array}{cc}{\displaystyle \frac{\Delta i_{\mathrm{dc}0}}{t_0}}·t\hfill & \forall 0<t<{\displaystyle \frac{t_0}{2}}\hfill \\ {\displaystyle \frac{\Delta i_{\mathrm{dc}x}}{t_x}}·\left(t-{\displaystyle \frac{t_0}{2}}\right)+{\displaystyle \frac{\Delta i_{\mathrm{dc}0}}{2}}\hfill & \forall {\displaystyle \frac{t_0}{2}}<t<{\displaystyle \frac{t_0+t_x}{2}}\hfill \\ {\displaystyle \frac{\Delta i_{\mathrm{dc}y}}{t_y}}·\left(t-{\displaystyle \frac{t_0+t_x}{2}}\right)+{\displaystyle \frac{\Delta i_{\mathrm{dc}0}+\Delta i_{\mathrm{dc}x}}{2}}\hfill & \forall {\displaystyle \frac{t_0+t_x}{2}}<t<{\displaystyle \frac{T_{\mathrm{pwm}}}{2}}\hfill \end{array}\right.$$

(54)

for the different time frames. Please note again that, similar to the derivation of the core losses, $V_{\mathrm{ac}}$ in Equation (26) is assumed to change linearly with M!

As analytical solutions for $I_{\mathrm{dc}}^{\langle n\rangle }$ are quite unhandy, especially when considering the functions for the changes in currents and time intervals, they have been solved numerically for a discrete set of modulation indices M and angles ${\phi }_{\mathrm{m}}$ during the design process. The corresponding AC copper losses can then be calculated using

$$P_{\mathrm{cu}\mathrm{ac}}\left(\underset{¯}{m}\right)=\sqrt{\sum _{n=1}^{\infty }{\left(I_{\mathrm{dc}}^{\langle n\rangle }\right)}^2·R_{\mathrm{ac}}^{\langle n\rangle }}.$$

(55)

To obtain the average losses over one fundamental period, the AC copper losses must be averaged, similar to the core losses. Due to the previously mentioned periodicity and symmetry, this averaging can be performed over a reduced interval.

$$P_{\mathrm{cu}\mathrm{ac}}\left(M\right)={\displaystyle \frac{6}{\pi }}{\int }_0^{\frac{\pi }{6}}{P}_{\mathrm{cu}\mathrm{ac}}\left(\underset{¯}{m}\right)\mathrm{d}{\phi }_{\mathrm{m}}$$

(56)

Once the copper and core losses are determined, the temperature rise $T_{\mathrm{rise}}$ can be calculated according to [30] using

$$T_{\mathrm{rise}}={\left({\displaystyle \frac{P_{\mathrm{fe}}+P_{\mathrm{cu}\mathrm{ac}}+P_{\mathrm{cu}\mathrm{dc}}}{10A_{\mathrm{L}\mathrm{surf}}}}\right)}^{0.833}$$

(57)

where the power variables are given in Watt and surface area is in m².

As the increase in the inductor temperature T from its initial value $T_0$ affects the specific resistivity of the copper ${\rho }_{\mathrm{cu}}$, both the AC and DC copper resistances are adjusted to the elevated temperature

$$\begin{array}{c}\hfill R_{\mathrm{dc}}(T=T_0+T_{\mathrm{rise}})=R_{\mathrm{dc}}(T=T_0)·(1+\alpha T_{\mathrm{rise}})\end{array}$$

(58)

considering the specific temperature coefficient of copper of $\alpha$ = 0.00404 °C⁻¹. Based on the updated DC resistance at elevated temperature, the corresponding AC and DC copper losses are recalculated using Equations (47) and (56). The resulting temperature rise is then determined using Equation (57). This iterative process continues until the inductor temperature reaches a steady state, i.e., a temperature change below 1% (cf. [30]).

Once an acceptable temperature rise is achieved, the inductor design is complete. Based on the evaluated parameters and the maximum inductor losses, a figure of merit can be calculated for each analyzed core and winding configuration. This figure of merit is essential for optimizing the design. The figure of merit for volume optimization, ${\mathrm{FOM}}_{\mathrm{V}}$, is given by

$$\begin{array}{c}\hfill {\mathrm{FOM}}_{\mathrm{V}}=V_{\mathrm{L}}·(P_{\mathrm{c}}+P_{\mathrm{cu}\mathrm{ac}}+P_{\mathrm{cu}\mathrm{dc}}).\end{array}$$

(59)

The inductor with the lowest figure of merit is finally chosen from the set of generated designs.

On the basis of the presented optimization process, two optimized split-design inductors have been designed and implemented. The corresponding design input parameters and the specifications of the selected inductor are summarized in Table 3. The loss distribution for the designed inductors at different modulation indices, assuming that $V_{\mathrm{ac}}$ varies linearly with M, is presented in Figure 14 as well.

5. Total Converter Losses

The total losses of the inverter at different load operation points can be determined using the semiconductor switching and conduction losses and the inductor loss distribution. For the following computation, a linear resistive load at the output is assumed.

Using the description of the conduction losses given in Equation (5), the switching losses given in Equation (3) and the DC-link inductor loss components given in Equations (41), (56), and (46) the total converter losses

$$P_{\mathrm{tot}}=P_{\mathrm{c}}+P_{\mathrm{s}}+P_{\mathrm{fe}}+P_{\mathrm{cu}\mathrm{dc}}+P_{\mathrm{cu}\mathrm{ac}}$$

(60)

can be estimated. A total loss summary at different operating points is shown in Figure 16 reassembling the results of Figure 7 and Figure 14 stacked on top of each other.

It can be observed that the conduction losses, consisting of power semiconductor conduction losses and AC and DC copper losses in the DC-link inductors of the presented current source inverter design, dominate the estimated total losses. Due to the constant DC-link current, these losses, neglecting the heating of the current-carrying components, are approximately constant over the entire load range of a resistive load. As expected, the switching losses increase linearly with increasing modulation index and therefore with increasing output voltage. However, even at nominal load, these only make up a small proportion of the total losses. In this case, the circuit would benefit from the selection of optimized semiconductor switches with lower on-resistance, which could reduce the conduction losses at the expense of higher switching losses. Furthermore, as shown in [54], the performance of the inverter could be greatly improved in the partial load operation by reducing the DC-link current at lower modulation indices.

6. Experimental Verification

Based on the proposed design process and loss modeling method, a laboratory CSI prototype has been designed and manufactured which is used to experimentally verify the theoretical findings. It consists of a three-phase CSI output stage for motor drives and includes a buck input stage for operation from a DC voltage source, such as a battery or a fuel cell. The constructed circuit is derived from the schematic representation provided in Figure 1. The included buck stage was, however, not within the scope of this investigation and has been deactivated during the experiments by turning on $S_{\mathrm{HB}+}$ constantly, and the required input voltage $V_{\mathrm{dc}}$ was generated directly using a laboratory power supply. Figure 17 presents an image of the developed CSI hardware laboratory prototype, which features a compact, stacked two-board design with two split inductors, an integrated heat sink, and fans.

The top board of the prototype accommodates an FPGA-based control platform running a custom control scheme and computing the space vector modulation algorithm, with ADCs for output along with DC-link current and voltage measurement, and includes the driver circuits and isolated gate drive power supply for the SiC MOSFETs. The bottom board contains the power circuit with the SiC MOSFETs along with the filter capacitors, optimized for thermal and electrical performance. An integrated thermal management system for the power semiconductor switches consisting of a copper heat sink and three axial fans, as already mentioned in Section 3.2, is located underneath the bottom board. The total volume of the converter including buck stage (not in operation) with a length of 145 mm, width of 115 mm, and height of 40 mm is 0.667 L, resulting in a volumetric converter power density of 4.5 kW/L. The reverse voltage blocking capability of the main switching elements was achieved using a common source back-to-back configuration of two SiC-based MOSFETs (IMBG65R072M1H) in a small-footprint SMD package (TO-263-7). For the DC-link inductor $L_{\mathrm{dc}}$, a split toroidal inductor was prototyped according to the design results in Section 4.2 and implemented as shown in Figure 1. The filter capacitors are ceramic capacitors based on C0G material that are placed as close as possible to the semiconductor switches, further minimizing the area of the commutation loop and decreasing switching losses.

The nominal AC output power of the converter is $P_{\mathrm{ac}}=3$ kW, with a maximum RMS output voltage of $V_{\mathrm{ac}}=200\mathrm{V}$, resulting in an average DC-link current of ${\overline{i}}_{\mathrm{dc}}=7\mathrm{A}$. The maximum DC input voltage of the system is $V_{\mathrm{dc}}=500\mathrm{V}$. The initial PWM carrier frequency was chosen to be $f_{\mathrm{pwm}}=100\mathrm{kHz}$ for the CSI.

Table 4. Summary of the prototype specifications.

Parameter	Symbol	Value
Nominal output power	$P_{\mathrm{ac}}$	3 kW
Nominal output voltage	$V_{\mathrm{ac}}$	200 V
Nominal output current	$I_{\mathrm{ac}}$	5 A
DC-link current	${\overline{i}}_{\mathrm{dc}}$	7 A
Maximum DC-link voltage	$V_{\mathrm{dc}}$	500 V
PWM switching frequency	$f_{\mathrm{pwm}}$	100 kHz
DC-link inductance	$L_{\mathrm{dc}}$	$2\times 583$ μH (51 turns on 3 cores, ${\mu }_r=60$)
Filter capacitance	$C_{\mathrm{f}}$	$8\times 100\mathrm{nF}$ (C0G in 2220 package)
Power semiconductor	-	IMBG65R072M1H
CSI overlap time	$t_{\mathrm{ol}}$	30 ns
Converter dimensions	-	$145\mathrm{mm}\times 115\mathrm{mm}\times 40\mathrm{mm}$
Converter volume	$V_{\mathrm{CSI}}$	0.667 L
Volumetric power density	${\rho }_{\mathrm{V}}\mathrm{CSI}$	4.5 kW/L

provides a detailed summary of the prototype specifications. Please note that for all experiments, the inverter stage was operated in open-loop control.

Experimental Results

The theoretical results for the AC voltage waveforms of Section 4.1, the DC-link current waveform of Section 4.2, and the converter loss modeling from Section 5 were experimentally verified using the implemented prototype. The converter efficiency was measured over the entire rated load range of the converter and the inverter output voltages and DC-link voltages and currents were recorded accordingly.

The following procedure was applied for this measurement:

• The inverter was loaded with three resistors of $R_{\mathrm{l}}=40\Omega$, which behaves like the linear load as assumed during the design process, ensuring the rated output voltage of $V_{\mathrm{ac}}=200\mathrm{V}$ at $M=1$ and ${\overline{i}}_{\mathrm{dc}}=7\mathrm{A}$.
• The average DC-link current was maintained constant at 7 A with an appropriate DC power supply in constant current mode at the input.
• The PWM frequency was set to 100 kHz, the AC output frequency to 100 Hz (period 10 ms), and the modulation index was decreased in steps from $M=1$ to $M=0.1$ to reduce the output power from the nominal operating point.
• The DC-link current $i_{\mathrm{dc}}$, the input voltage $V_{\mathrm{dc}}$, the three output currents $i_{\mathrm{a}}$, $i_{\mathrm{b}}$, and $i_{\mathrm{c}}$, as well as the line-to-line output voltages $v_{\mathrm{ab}}$, $v_{\mathrm{bc}}$, and $v_{\mathrm{ca}}$ were measured using an oscilloscope (Tektronix 5 Series) with appropriate current clamps and differential voltage probes, resulting in a total measurement bandwidth of 50 MHz. The phase voltage quantities $v_{\mathrm{a}}$, $v_{\mathrm{b}}$, and $v_{\mathrm{c}}$ were subsequently calculated from the measured line-to-line voltages via $v_{\mathrm{a}}=\frac{v_{\mathrm{ab}}-v_{\mathrm{ca}}}{3}$, $v_{\mathrm{b}}=\frac{v_{\mathrm{bc}}-v_{\mathrm{ab}}}{3}$, and $v_{\mathrm{c}}=\frac{v_{\mathrm{ca}}-v_{\mathrm{bc}}}{3}$ to be able to compare the measurement results with the analytical derivations for the phase voltage ripple.
• The converter efficiency was measured using a HIOKI PW8001 power analyzer employing HIOKI U7005 current transducers.

The measured current and voltage waveforms for an output power of $P_{\mathrm{ac}}=2\mathrm{kW}$ ($\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$3$}\right.$ of the nominal load) are shown in Figure 18 for a modulation index of $M=0.817$. Please note that the phase voltages were calculated from the measured line-to-line voltages.

Figure 19 additionally shows the output voltage ripple in phase a and the DC-link current ripple for the same operating point at an output power of $P_{\mathrm{ac}}=2\mathrm{kW}$. The output voltage ripple was obtained by appropriate high-pass filtering of the measured $v_{\mathrm{a}}$ and the ripple of the DC-link current was obtained by subtracting the average DC-link current. Both Figure 19a,b additionally show zoomed subplots of the respective waveforms to highlight the individual voltage and current slopes at sector $\overline{)\mathsf{Ⅵ}}$ (at $-2$ ms) and sector $\overline{)\mathsf{Ⅲ}}$ (at 4 ms).

The output voltage ripple for sector $\overline{)\mathsf{Ⅵ}}$ (left zoomed plot) shows that $v_{\mathrm{a}}$ increases during time intervals $\raisebox{1ex}{$t_y$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$ and decreases in intervals $\raisebox{1ex}{$t_0$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$ and $t_x$, which corresponds to the signs of the curves displayed in Figure 9. The corresponding sequencing $\raisebox{1ex}{$t_0$}\!\left/ \!\raisebox{-1ex}{$2$}\right.\to \raisebox{1ex}{$t_y$}\!\left/ \!\raisebox{-1ex}{$2$}\right.\to t_x\to \raisebox{1ex}{$t_y$}\!\left/ \!\raisebox{-1ex}{$2$}\right.\to \raisebox{1ex}{$t_0$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$ then results in a reduced amplitude for the output voltage ripple. In contrast, the sequence for sector $\overline{)\mathsf{Ⅲ}}$ (right zoomed plot) is selected in such a way that the two intervals $t_x$ and $t_y$ in which the voltage increases are directly adjacent in the center of the interval. This results in a higher ripple amplitude over the entire PWM period. The total measured envelope of the voltage ripple is in good agreement with the theoretical curves of Figure 10.

As illustrated previously in Figure 12, the sequencing of separate sub-intervals does not result in a decrease in DC-link current ripple amplitude. As anticipated, the observed ripple envelope shows periodicity with the sectors; however, there are slight differences in shape between even and odd sectors. The overshoots observed in the current result from the parasitic winding capacitance associated with the DC-link inductors. The measured current ripple amplitudes again agree well with the theoretical values in Figure 12.

Figure 20 presents the efficiency of the converter ${\eta }_{\mathrm{meas}}$ as measured by the power analyzer across seven distinct operating points and corresponding modulation indices. Throughout the entirety of the measurement process, the DC-link current was maintained at 7 A by utilizing a DC power supply. The measurement points are denoted by black dots and interpolated using a dashed line to emphasize the converter efficiency curve across various operating points for a constant load.

In addition to the measured results, the theoretically calculated efficiencies for each loss component analyzed in the preceding sections are displayed as colored areas. The efficiency areas are calculated by taking the semiconductor switching losses $P_{\mathrm{s}}$, conduction losses $P_{\mathrm{c}}$ and $P_{\mathrm{c}\mathrm{Shbp}}$, inductor core losses $P_{\mathrm{fe}}$, and inductor DC and AC copper losses $P_{\mathrm{cu}\mathrm{dc}}$ and $P_{\mathrm{cu}\mathrm{ac}}$ from Figure 16 and converting them into the respective efficiency curves via $\eta =\frac{P_{\mathrm{ac}}}{P_{\mathrm{ac}}+P}$. Here, the modulation index dependent converter AC output power corresponds to $P_{\mathrm{ac}}=3\mathrm{kW}·{\mathrm{M}}^2$. The efficiency of the converter reaches its maximum at approximately 98.8% at the nominal operating point of $P_{\mathrm{ac}}=3\mathrm{kW}$. As the output power decreases, the efficiency decreases, but maintains a value of 97.9% at 1.5 kW.

Additionally, the efficiency calculated using the loss separation method from the preceding sections is in excellent agreement with the efficiency measured by the power analyzer, which provides strong evidence that the proposed design approach for CSIs is viable.

7. Conclusions

This paper presents a comprehensive framework for the design and analysis of silicon-carbide semiconductor-based current source inverters (CSIs) for high-performance motor drive applications. The proposed methodology integrates analytic and numerical techniques to optimize passive component design, including filter capacitors and the DC-link inductor, and provides comprehensive efficiency estimation for semiconductor switching losses and conduction losses, as well as for losses occurring in the DC-link inductor. A laboratory hardware prototype CSI with the specifications given in Table 1 is developed, built, and tested. The theoretical findings based on analytical models are then compared to the experimental results taken from the constructed hardware prototype. The efficiency calculated using the loss separation method from the preceding sections, as well as the analytically derived current and voltage ripple waveforms, is in excellent agreement with measured results, providing strong evidence that the presented design approach for CSIs is viable.