Analysis of Nanoscale Short Channel Effects in Cylindrical Gate-All-Around Junctionless FETs and Performance Enhancement with GaAs and III–V Materials for Low-Power, High Frequency Applications

Abstract

With the advancement of the semiconductor industry into the sub-10 nm regime, high-performance, low-energy transistors have become important, and gate-all-around junctionless field-effect transistors (GAA-JLFETs) have been developed to meet the demands. Silicon (Si) is still the dominant semiconductor material, but other potential alternatives, such as gallium arsenide (GaAs), provide much higher electron mobility, improving the drive current and switching speed. In this study, our contributions include a comparative analysis of Si and GaAs-based cylindrical GAA-JLFETs, using threshold voltage behavior, electrostatic control, short channel effects, subthreshold slope, drain-induced barrier lowering, and leakage current as the metrics for performance evaluation. A comprehensive analytical modeling approach is employed, solving Poisson’s equation and utilizing numerical simulations to assess device characteristics using the ATLAS SILVACO tool under varying channel lengths and gate biases. Comparisons between Si and GaAs-based devices show what trade-offs exist and what the material engineering strategies are to use the advantages of GaAs while minimizing some disadvantages. The results of the study are a valuable contribution to the design and optimization of next-generation FET architectures, pointing the direction for enabling next-generation beyond CMOS technology.

1. Introduction

The ability to scale intermittent semiconductor devices has continued to be a driving force in realizing integrated circuits that are smaller, faster, and more power-efficient in modern electronics. As technology advances into the sub-nanometer regime, traditional transistor technology such as planar MOSFETs and FinFETs faces critical challenges such as short-channel effects (SCEs), problems with gate control, and higher power dissipation. These limitations preclude scaling transistors further, and alternative transistor architectures that yield better electrostatic control, improved performance, and scalability must be pursued [1]. A gate-all-around (GAA) transistor is one promising solution to all these challenges. A GAA transistor has a gate surrounding the channel, providing more electrostatic control than conventional transistor structures such as FinFETs, where the gate is controlled from three sides. As the dimensions are scaled down even further, this enhanced control plays a crucial role in overcoming SCEs and device performance [2]. The gate-all-around junctionless field-effect transistors (GAA-JLFETs) are among the most promising candidates for different GAA transistor configurations. In a conventional MOSFET, the current flows according to control by a well-defined p-n junction; conversely, junctionless transistors control current flow based on a continuous doping profile within the channel. The absence of a sharp junction boundary means that fabrication is simpler, and there is no need for complex high-temperature processing and junction formation. Junctionless devices are less sensitive to the SCEs and are easily scalable with smaller dimensions. One strong cornerstone has been the material silicon, primarily used in fabrication, and the processing has matured and become highly cost-effective. The silicon-based GAA-JLFETs present an interesting case worth pursuing further since they may enable the reduction of the scaling limits and lead to better performance within the silicon CMOS ecosystem. In this paper, we explore the idea of GAA-JLFETs concerning silicon material and evaluate the advantages and disadvantages of applying this approach to next-generation semiconductor devices. In this paper, we take a step back from that and aim to provide a comprehensive review of the basic GAA-JLFET principles, their performance, and how they overcome the limits of conventional transistor design [3].

As much as the scaling of transistor dimensions has continued unmoved, ad infinitum, according to Moore’s Law [4], this scaling has created fundamental difficulties with SCEs, leakage currents, and power dissipation in conventional MOSFETs. To overcome these problems, various multi-gate architectures, including so-called’ Gate All Around’ (GAA) transistors, are superior for the control of electrostatics and, thus, improve channel scaling. One of these is the JLFET, a novel device concept that eliminates the traditional pn junctions, is easy to fabricate, and improves manufacturability [5]. Unlike conventional MOSFETs, which conduct current through a surface channel, JLFETs use bulk conduction, leading to mobility degradation and better carrier transport properties. Moreover, Cylindrical GAA JLFETs (CGAA-JLFETs) possess even better gate-to-channel control, thus effectively suppressing drain-induced barrier lowering (DIBL) and leakage currents, making them especially suitable for ultra-low power and high frequency applications [6].

Compound III–V semiconductor gallium arsenide (GaAs) has several advantages over silicon (Si) for electronic purposes, especially in high frequency and optoelectronic devices. Since the electron mobility for GaAs is higher (~8500 cm²/V·s) than that of Si (~1400 cm²/V·s), transistor performance in drive current and switching speed is better for GaAs than for Si. Furthermore, GaAs possesses a direct bandgap (1.42 eV at 300 K) and is very attractive for optoelectronic applications such as laser diodes and high-efficiency solar cells. However, due to its lower dielectric constant (ε = 12.9) compared to Si (ε = 11.7), weaker electrostatic control is obtained, leading to enhanced leakage current and SCEs in scaled devices. However, heterostructure engineering is a primary means of overcoming some of the shortcomings of GaAs-based transistors in low-power applications, as well as their widespread exploration for high-speed, high frequency, and RF applications. Recent research on GaAs-based GAA JLFETs has been related to utilizing superior transport properties of GaAs-based materials while optimizing the electrostatics using advanced doping techniques and high-k gate dielectrics [7].

Due to its enclosed gate configuration, a CGAA-JLFET structure provides advanced electrostatic control over planar and FinFET structures. A cylindrical gate structure provides a complete gate enclosure that is not found in FinFETs, as they receive gate control only from three sides. Consequently, the potential distribution remains consistent throughout the channels. The cylindrical bounds provide superior electrostatic control by minimizing two crucial SCE problems: DIBL and threshold voltage roll-off. The increased connection between the gate and channel in this structure establishes controlled electric fields that minimize leakage through channels while improving I_ON/I_OFF ratios. CGAA-JLFETs provide excellent potential for next-generation semiconductor applications in low-power and high frequency circuits due to their numerous beneficial characteristics. The researcher analyzes the performance-influencing effects of cylindrical structures through an extensive study while investigating material-specific effects, particularly in GaAs and Si.

This work adopts new characteristics that distinguish it from previously published studies on GAA-JLFETs. The research compares silicon-based and gallium arsenide-based CGAA-JLFETs to analyze their effects on SCEs, subthreshold behavior, and high frequency performance. The work uses advanced electrostatic modeling to show greater electrostatic stability by solving Poisson’s equation in cylindrical coordinates. The SILVACO ATLAS software (Device Simulator version: atlas 5.22.1.R) performs complete 3D numerical analyses of device properties to examine leakage current with DIBL and SS products while demonstrating superior performances of GaAs versus Si for future transistor designs. The expertise generated by this research helps improve material choice decisions, electrostatic control systems, and scalable device designs for future beyond-CMOS semiconductors.

2. Theoretical and Simulation Framework

With a continued push toward smaller transistor sizes and enhanced device performance, semiconductors have been evolving rapidly in this field. Traditional MOSFETs face significant challenges at the sub-10 nm scaling regime, and alternative transistor architectures have been proposed. The class of junctionless transistors (JLTs) proposed by researchers eliminates a conventional p-n junction in the channel, instead relying on a continuous doping profile. Simultaneously, this design promises reduced fabrication complexity and augmented electrostatic control in scaled devices. In parallel, GAA transistor architecture has emerged as a promising candidate for overcoming some of the limitations of FinFETs that are mainly limited by a lack of gate control on the channel. In the GAA structure, the gate not only encloses the channel on the top, but all the exposed sides are covered with gates, making it easier to control electrostatically. Junctionless GAA transistors benefit from both junctionless and GAA transistor designs, namely that junctionless transistors have fewer SCEs and better scalability [8,9].

Because of the improved electrostatic control over all corners of junctionless transistors, electrostatic GAA is one of the primary motivations for adopting this architecture. In traditional planar MOSFETs, the gate only controls part of the channel, resulting in poor electrostatic control as the devices scale down. A three-dimensional structure with FinFETs was introduced to overcome this issue; however, as the channel length continues to scale, SCEs and DIBL remain of concern. Junctionless GAA transistors have their gate surrounding the channel, providing superior electrostatic control and eliminating SCEs. According to research from Hossain et al., this superior control causes a reduced threshold voltage variation and steeper subthreshold slope (SS), which are standard for better-switching characteristics. A significant reduction in subthreshold leakage currents and a higher on/off ratio than traditional and GAA junctionless transistors have been demonstrated [10].

The simplified fabrication process can also be another significant advantage of GAA-JLFET. Conventional devices create p-n junctions in the channel, but GAA-JLFET devices have uniform doping profiles in the channel. As a result, the fabrication complexity is significantly reduced in junction formation, high-temperature processing, and doping profile control. Ghosh et al. have shown that GAA-JLFET devices could be fabricated using relatively simpler process flows on silicon-on-insulator (SOI) wafers, which provide better electrostatic isolation and easier control of the channel conductivity. The continuing low cost, well-understood manufacturing processes, and superior mechanical properties of silicon continue to make it the most frequently used semiconductor fabrication material for submicron devices. Silicon has relatively high carrier mobility and is a well-known bandgap regarding electrical properties. It is an ideal candidate for most semiconductor devices. Nevertheless, with the ongoing scaling of the transistor size, the performance of silicon-based devices is limited due to SCEs and carrier mobility [11].

In recent years, the potential of silicon concerning junctionless GAA devices has been investigated in works by Srivastava et al. Silicon-based junctionless GAA transistors have significant advantages over conventional planar MOSFETs and FinFETs regarding reduced SCEs, saturation current, and better scalability. Although silicon is a well-accepted material, its use in junctionless GAA transistors is limited by carrier mobility limitations [12]. Compared to materials such as germanium, III–V compounds (e.g., InGaAs), and graphene, silicon has lower electron mobility and smaller current drive capabilities of devices. To tackle this issue, A. Kumari et al. presented strained silicon or silicon-germanium alloy as carriers of carrier mobility improvement. Improvements in velocity and, thus, drive current can be achieved with strained silicon created by introducing tensile or compressive strain in the material. Yet, applying strain to silicon devices often results in additional complexity and challenges, including strain-mediated mechanical stress management during fabrication and strain-sensitive interface defects [13].

Junctionless GAA devices are widely regarded as excellent candidates for commercialization and ideal for SOI wafer fabrication. Insulation of the channel from the substrate enables better control over the channel and reduces parasitic capacitance, enabling better device performance. In addition, the insulating layer supplies better electrostatic isolation, which is essential for shrinking GAA-JLFET devices without degrading performance. Dixit et al. have shown that using SOI wafers also allows for higher performance of junctionless GAA devices by preventing current leakage through the substrate and providing a cleaner current path [14]. However, precise patterning of the gate and channel affects the performance of scaled-down junctionless GAA devices. As device dimensions approach the nanometer scale, traditional photolithography techniques operate near their resolution limits. As a result, researchers have been investigating higher-resolution lithography techniques, such as extreme ultraviolet (EUV) lithography and nanoimprint lithography (NIL). For example, results have demonstrated the use of NIL to fabricate high-quality nanowire structures in GAA-JLFET. As a result, NIL offers excellent advantages over conventional photolithography; NIL produces smaller feature sizes and is, thus, a promising candidate for the future fabrication of GAA-JLFET [15].

The performance of junctionless GAA devices is heavily dependent on the channel doping profile. These devices require the doping to be uniform across the channel to ensure continuous bandwidth and avoid separate p-n junctions. Uniform doping profiles have been attempted using ion implantation and in situ doping techniques. Nevertheless, doping concentration gradients and the diffusion of dopants during high-temperature processing impeded the precision of the doping profile. It has recently been proven that atomic layer doping (ALD) techniques can improve the doping uniformity in GAA-JLFET. Numerous research studies have been conducted to compare junctionless GAA transistors with conventional FinFETs and planar MOSFETs to demonstrate the electrostatic control, scalability, and reduction of the SCEs of junctionless GAA transistors [16]. For instance, they showed that junctionless GAA transistors exhibit better threshold voltage stability, given improved electrostatic control, reduced SCEs resulting in lower leakage currents and better on/off current ratios, and successful scaling down to the 5 nm node with little performance degradation. Other studies, for example, reported that junctionless GAA transistors are scaled further and may confront impediments to high leakage currents and power efficiency, particularly with silicon-based devices. Though significant advancements have been achieved in exploring the application perspective of GAA-JLFET, certain issues are still largely unaddressed, namely material constraints, technological issues, and scaling problems [17].

3. Methodology and Device Structure of CGAA-JLFET

For efficient prediction of the device’s performance in nanoscale regimes, the cylindrical GAA-JLFET (CGAA-JLFET) also requires analysis. Poisson’s equation in cylindrical coordinates describes the electrostatic behavior of these transistors, that is, the potential distribution within the channel. Next, the threshold voltage is derived from solving the 2D Laplace equation with the proper boundary conditions, including the doping concentration effect, oxide thickness, and channel radius. The analysis of SCEs such as DIBL and subthreshold slope (SS) degradation is presented by the potential to explore the weaker electrostatic integrity in the case of GaAs’s lower dielectric constant-based transistors. In addition, the drain current characteristics are modeled using the drift-diffusion transport equation, and the higher carrier mobility of GaAs leads to higher drive currents, although they suffer from greater off-state leakage. An assessment of combining different channel lengths and optimized doping profiles to alleviate SCEs, improve the subthreshold performance, and decrease the leakage currents in GaAs-based CGAA-JLFETs is presented. Prior to this work, theories and experiments regarding Si and GaAs-based JLFETs were developed. This mathematical framework incorporates this prior work, fully compares Si and GaAs-based JLFETs, and provides key insights into the application space of these devices for low-power and high frequency applications [18,19,20]. The mathematical solutions for drain current under various bias conditions are shown in

Table 1. Drain Current Equations for CGAA-JLFET with Different Bias Conditions [21].

Bias	Drain Current
$V_{GS }>V_{po}$ $V_{GS }<V_{FB}$ $V_{DS }<V_{DSat1}$	$I_{\begin{array}{c}D \\ \end{array}}={\displaystyle \frac{q{\mu }_{b{N}_D }}{L_{effb}}}\left({\displaystyle \frac{1}{n+1 }}{\displaystyle \frac{S_{max}-S_{min} }{{(V_{FB}-V_{po })}^n}} \left({\left(V_{GS }-V_{po}\right)}^{n+1}-{(V_{GS}-V_{DS }-V_{po})}^{n+1}\right)+S_{min}{V}_{DS}\right)$
$V_{GS }>V_{po}$ $V_{GS }<V_{FB}$ $V_{DS }>V_{DSat1}$	$I_{\begin{array}{c}D \\ \end{array}}={\displaystyle \frac{q{\mu }_{b{N}_D }}{L_{effb}}}\left({\displaystyle \frac{1}{n+1 }}{\displaystyle \frac{S_{max}-S_{min} }{{(V_{FB}-V_{po })}^n}} \left({\left(V_{GS }-V_{po}\right)}^{n+1} \right)+S_{min}{V}_{DS}\right)$
$V_{GS }>V_{FB}$ $V_{DS }<V_{DSat2}$	$I_{\begin{array}{c}D \\ \end{array}}={\displaystyle \frac{q{\mu }_{b{N}_D }}{L_{effb}}} S_{max}{C}_{ox}+{\displaystyle \frac{{\mu }_{acc }{C}_{ox }{W}_{eff}}{L_{effacc}}}\left(V_{DS }\left(V_{GS }-V_{FB}\right)-{\displaystyle \frac{1}{2}} {V_{DS}}^2\right)$

and

Table 2. The description of the symbol used in Table 1 [21].

Symbol	Value
$V_{po0}$	Linear pinch-off voltage at $V_D=0V$
$V_{po}$	Pinch-off voltage $V_{po}$$=V_{po0}-\eta V_{Ds}$
$\eta$	DIBL coefficient
$W_{eff}$	Channel Perimeter
$S$	Neutral (non-depleted) cross-section of the channel: $S=S_{min}$ When the surface is inverted and ${S=S}_{max}$ When the surface is accumulated.
$V_{DSat1}$	Drain Saturation Voltage for the neutral bulk channel $V_{DSat1}={\displaystyle \frac{V_{GS }-V_{p0o}}{1-\eta }}$
$V_{DSat2}$	Drain Saturation Voltage for the accumulation channel $V_{DSat2}$ = $V_{GS}-V_{FB}$
$L_{effb}$	The effective length of the neutral bulk channel
$L_{effacc}$	The effective length of the accumulation channel
${\mu }_{acc }$	Accumulation mobilities
${\mu }_{b }$	Bulk mobilities

.

In our work, we have performed a detailed analysis of a silicon-based three-dimensional JLFET with cylindrical gate-all-around architecture. As shown in Figure 1, this proposed architecture has been comparatively studied with varying gate lengths of 10, 20, 30, 40, 50, and 60 nm with a constant radius of 10 nm. The ITRS roadmap has guided the geometrical settings and mesh design, and finally, this crucial task has been provided with proper technology nodes and feature sizes as needed. With the help of extensive 3D simulations conducted using SILVACO TCAD (ATLAS Device Simulator version: atlas 5.22.1.R) tools, it is shown that the presented device exhibits better performance than the conventional MOSFETs. The 3D cylindrical design has a radius mesh (R in µm), angle mesh (A in degrees), and length mesh (Z in µm). This 3D cylindrical design consists of five regions with different materials, i.e., 1: silicon used as a semiconductor/channel material, 2: SiO₂ as an insulator, 3: P+ polysilicon is used as the gate electrode (metal gate), P+ polysilicon is used as a source contact (metal source), and P+ polysilicon is also used as a drain contact (metal drain). The coordinates for the cylindrical structure involve three electrodes: drain, source, and gate. The device parameters of the proposed device are noted in

Table 3. Device parameters of the CGAA-JLFET.

Parameters	For Cylindrical Gate-All-Around JLFET
Channel material	Silicon
Channel region with doping concentration	N-type–1019 cm−3
Source region with doping concentration	N-type–1019 cm−3
Drain region with doping concentration	N-type–1019 cm−3
Gate material	P+ polysilicon
Gate workfunction	5.4 eV
Oxide permittivity	3.9
Channel length	20 nm
Oxide thickness	2 nm
Semiconductor (Si-substrate) thickness	10 nm (radius)
Device length	60 nm

.

The Shockley-Read-Hall and AUGER recombination models were used to analyze recombination effects for high current densities. NEWTON and GUMMEL models were incorporated into equations with coupled and decoupled forms. This paper describes the simulation of the electrical characteristics of novel transistor JLFET with gate-all-around architecture using the ATLAS 3-D device simulator at different channel lengths.

The verification of simulation results depended on executing multiple runs with identical simulation parameters, under which results proved consistent across different simulations. Mesh refinement techniques reached numerical convergence by applying Newton-Gummel iterative methods, which used strict convergence criteria. The simulation results were validated by validating them against existing theoretical models alongside literature findings. The strong electrostatic properties of CGAA-JLFETs continue to improve device operational efficiency when operating at small dimensional scales despite SCE limitations. The cylindrical gate structure eliminates gate leakage asymmetry and provides enhanced control over the channel potential, leading to reduced DIBL effects and better SS.

4. Results and Discussions

4.1. Electrostatic Modeling of Si-Based CGAA-JLFET

Nanotransistors utilize the Poisson equation to evaluate the electrostatic potential inside the device because this information determines the distribution of charges and carrier mobility. The analysis of gate control, along with threshold voltage and subthreshold leakage, requires a Poisson equation solution in nanotransistors to evaluate performance while maintaining energy efficiency properly. The accurate modeling of quantum effects and SCEs requires the Poisson equation because FinFETs and tunnel FETs use this advanced device architecture. Preventing the degradation of nanoscale electronic devices so scientists can develop enhanced versions of future technology relies on the Poisson equation working together with the drift-diffusion model or Schrödinger quantum transport equations. The sharing of electric charge between drain and source terminals remains a critical issue in advanced device platforms because it harms threshold voltage consistency. The cylindrical gate surrounds the channel in a complete system, decreasing charge-sharing effects and maintaining a consistent threshold voltage throughout diverse channel regions. The strong electrostatic control enabled by increased gate-to-channel capacitance leads to improved steepness in SS characteristics while lowering off-state leakage. The properties of GaAs-based CGAA-JLFETs become more pronounced due to their superior electron mobility and power dissipation characteristics compared to standard Si-based devices.

The research analyzes performance metrics and material assessments between cylindrical GAA-JLFETs. Figure 2a presents the simulated transfer characteristics of CGAA-JLFET for different channel lengths ranging from 10 nm to 60 nm, and P+ polysilicon has been used to fulfill the requirement of a high gate work function to achieve an appropriate Vth value. The threshold voltage value decreased as the channel length decreased, as shown in Figure 3. These I_D-V_GS characteristics of the CGAA-JLFET have been plotted at V_DS = 0.01 V, spanning a range of V_GS from −0.4 to 1.2 V. The threshold voltages for different channel lengths have been observed to be V_th = −0.21461 V (at 10 nm), 0.216574 V (at 20 nm), 0.37356 V (at 30 nm), 0.511143 V (at 40 nm), 0.622054 V (at 50 nm), and 0.671832 V (at 60 nm).

The actual off-state operation displays substantial nonlinear behavior in actual electronic devices. These currents appear in the subthreshold region, among other leakage currents. The transition between I_D-V_GS occurs gradually due to subthreshold slope behavior. The off-state leakage is affected by DIBL. Enhanced nonlinear patterns in both leakage currents and subthreshold characteristics of the off-state region can be seen in Figure 2b.

The characteristics and results of a silicon-based CGAA-JLFET show the behavior of the drain current as a function of the gate-to-source voltage (V_GS). The transfer curve of a JLFET often rises sharply above when V_GS crosses the threshold voltage (V_th) and then saturates in the on state. This device has a steep subthreshold slope, showing that switching is efficient. As we decrease the channel length, SCEs arise, which force the threshold voltage (V_th) to drop; hence, it is more sensitive to a change in V_DS. As a result, leakage current increases, and the I_ON/I_OFF ratio decreases, leading to compromised device switching efficiency [22]. Compared to other inversion devices, SCEs are less common in JLFETs. Equation (1) explains how the space charge area connected to the junctions (designated as SCE in Equation (1)) and the expansion of the drain space charge region with drain voltage (designated as DIBL in Equation (1)) cause the threshold voltage to decrease in the junction or other conventional devices.

$${\mathrm{V}}_{\mathrm{t}\mathrm{h}}={\mathrm{V}}_{\mathrm{t}\mathrm{h}\mathrm{o}}-\mathrm{S}\mathrm{C}\mathrm{E}-\mathrm{D}\mathrm{I}\mathrm{B}\mathrm{L},$$

(1)

Figure 4 shows the plot of the electric field distribution versus the distance from the gate electrode along the nanowire for 10 nm and 40 nm CGAA-JLFET, respectively. Scaling and SCEs significantly differ in electric field distribution for a 10 nm and 40 nm CGAA-JLFET. When scaled to a 10 nm channel length, the electric field across the channel is highly concentrated near the source and drain regions, where the variations are sharp due to the strong DIBL and punch-through effects. Because of this scale, however, the gate electrostatic control becomes weak, resulting in a non-uniform electric field at the channel ends where the field is higher. However, for the case of the 40 nm channel length, the electric field distribution is uniform over the channel compared to that of the 10 nm channel, with smaller SCEs. The gate-to-channel electrostatic coupling is stronger, allowing better channel control. In both cases, the CGAA-JLFET structure helps overcome some of the SCEs by providing better gate control on the channel, but as the channel length reduces, the field becomes localized, and device performance becomes more dependent on higher leakage currents and switching efficiency [23].

Figure 5 and Figure 6 show the energy band diagrams of 10 nm and 40 nm CGAA-JLFETs, respectively. The energy band diagram consists of a conduction band and a valence band. An energy band diagram for 10 nm and 40 nm CGAA-JLFETs illustrates the effects of gate voltage, channel length, and SCEs on the conduction and valence bands. The band bending in CGAA-JLFETs shapes carrier transport, threshold voltage stability, and SCEs, as Figure 5 and Figure 6 demonstrate. The conduction band in the 10 nm CGAA-JLFET forms a steep bend because of extensive DIBL, which reduces the effective barrier height and increases leakage currents. Such characteristics lead to easier device turn-on at reduced gate voltages, producing higher subthreshold leakage and lower threshold voltages. The device switches faster because of its extreme energy fluctuations, although this speed boost produces increased power losses. The energy band profile of the 40 nm CGAA-JLFET demonstrates maximum electrostatic control because of its progressive band bending characteristics, which reduce SCEs. Stable differences between drain and source potentials improve threshold voltage stability and create lower leakage in the device. Gate efficiency in the 40 nm device improves because of its lowered DIBL effect, resulting in a superior SS with better ON/OFF current ratio performance. The steep band bending characteristics of the 10 nm CGAA-JLFET lead to increased leakage and threshold voltage drift, making the 40 nm CGAA-JLFET superior in low-power high frequency settings due to improved electrostatic control. Band bending optimization is vital for establishing the next-generation semiconductor devices that must achieve ideal performance alongside energy efficiency [24].

Figure 7 shows the electric potential distribution of 10 nm and 40 nm CGAA-JLFETs. The variation of potential distribution in a 10 nm and 40 nm CGAA-JLFET is significant because of the difference in channel length, which subsequently leads to short channel effects. Since the DIBL and the reduced electrostatic control of the gate peak at the source and drain regions, the potential profile exhibits a steep voltage gradient for the 10 nm channel. Due to the reduced size of the channel, control over the channel becomes difficult, reflected through the potential near the channel center attempting to flatten. However, the device retains stronger gate electrostatic control at 40 nm, and potential distribution is more uniform across the channel with smoother variation from source to drain. The longer channel improves device performance and reduces SCEs by facilitating a more gradual change in potential. In both cases, the CGAA-JLFET structure yields better control on the channel than conventional planar transistors, but the 10 nm device is plagued by increased leakage currents and more severe potential fluctuations at higher drain voltages [25].

Figure 8 illustrates the I_D-V_DS characteristics of the CGAA-JLFET at V_GS = 1.2 V, with V_DS ranging from 0 to 1 V for different channel lengths. This device demonstrates a high ON-state current and a low OFF-state current, showcasing excellent electrostatic control, with a maximum drain current of 3.74606 × 10⁻⁵ A (at 10 nm), 3.23924 × 10⁻⁵ A (at 20 nm), 2.95 × 10⁻⁵ A (at 30 nm), 2.76015 × 10⁻⁵ A (at 40 nm), 2.720923 × 10⁻⁵ A (at 50 nm) and 2.698054 × 10⁻⁵ A (at 60 nm). The saturation slope is about to 6.43265 × 10⁻⁶ A (at 10 nm), 4.07531 × 10⁻⁶ A (at 20 nm), 3.1868 × 10⁻⁶ A (at 30 nm), 3.15754 × 10⁻⁶ A (at 40 nm), 3.10029 × 10⁻⁶ A (50 nm), and 3.05913 × 10⁻⁶ A (at 60 nm). It can be understood here that the maximum drain current and saturation slope increase as channel length decreases. As the technology scales down during different nodes (10, 20, 30, 40, 50, and 60 nm), the output characteristics of the silicon-based CGAA-JLFET follow key trends. With smaller nodes (10–30 nm), electrostatic control improves, SCEs are reduced, and the SS steepens, leading to higher current drivability and lower leakage. On the other hand, larger nodes (40–60 nm) suffer from more severe SCEs, such as threshold voltage roll-off and higher leakage currents, resulting in reduced performance efficiency. The drain current is proportional to the gate voltage, and the devices have typical saturation behavior, with smaller nodes controlling these effects better.

4.2. Short-Channel Effects and Scalability Considerations

The cylindrical gate architecture delivers better electrostatic performance than planar and FinFET structures, thus making it highly successful in reducing SCEs. Full gate enclosure in CGAA-JLFETs allows for uniform electric fields that minimize DIBL and enhance SS, as they overcome the charge-sharing restrictions experienced in FinFETs. The elevated gate-to-channel capacitance enables better charge confinement, stopping threshold voltage from degrading too extensively at small device dimensions. This section provides a quantitative evaluation of the SCE reduction capability of the cylindrical structure across different channel lengths and materials. Figure 9 illustrates the on-current and off-current variations of Si-based CGAA-JLFET with different channel lengths [26]. Mathematical expressions for SS and DIBL are explained in Equation (2) and Equation (3), respectively:

$$\mathrm{S}\mathrm{u}\mathrm{b}\mathrm{t}\mathrm{h}\mathrm{r}\mathrm{e}\mathrm{s}\mathrm{h}\mathrm{o}\mathrm{l}\mathrm{d} \mathrm{S}\mathrm{l}\mathrm{o}\mathrm{p}\mathrm{e}={\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{G}}}{\mathrm{d}\mathrm{l}\mathrm{o}\mathrm{g}{\mathrm{I}}_{\mathrm{D}}}}$$

(2)

$$\mathrm{D}\mathrm{I}\mathrm{B}\mathrm{L}={\mathrm{V}}_{\mathrm{t}\mathrm{h}@\mathrm{V}\mathrm{d}\mathrm{s}=50\mathrm{m}\mathrm{V}}-{\mathrm{V}}_{\mathrm{t}\mathrm{h}@\mathrm{V}\mathrm{d}\mathrm{s}=1\mathrm{V}}$$

(3)

The simulated results for DIBL and SS versus different channel lengths are plotted in Figure 10. We present distinct trends in the SS and DIBL as the technology node shrinks for silicon-based CGAA-JLFET. Due to the improved electrostatic control, the SS becomes steeper, typically close to the ideal 60 mV/dec for larger nodes (40∼60 nm), while DIBL decreases, resulting in milder SCEs. However, smaller nodes (10∼30 nm) suffer from larger DIBL and shallower SS due to greater SCEs, resulting in more threshold voltage shifts and lower gate control. As a result, larger nodes (40 to 60 nm) provide better subthreshold performance and DIBL, resulting in less electric loss. When channels have extensive lengths, gate electrostatic control effectively seals leakage currents. When channels become shorter, the gate loses its capacity to fully regulate current, resulting in greater leakage in off-state mode [27].

Figure 11 illustrates the channel length dependency of the Si-based CGAA-JLFET transconductance for different channel lengths ranging from 10 nm to 60 nm. As the technology node scales down, the transconductance of silicon-based CGAA-JLFET has been improved. For larger nodes (40–60 nm), higher transconductance is achieved because of enhanced electrostatic control and reduced SCEs, thereby enabling better current modulation as a function of gate voltage. However, smaller nodes (10–30 nm) exhibit more pronounced SCEs, resulting in lower transconductance and less efficient control over the channel current. Larger nodes exhibit higher transconductance because of better gate control and less leakage, making them suitable for high-end applications [28].

4.3. Performance Analysis of Si-Based CGAA-JLFET with Different Channel Lengths

The analysis of CGAA-JLFET studies with varying channel lengths is presented in this study.

Table 4. Performance comparison of the proposed CGAA-JLFET with different channel lengths.

Lg (nm)	Vth (V)	Saturation Slope (A)	Max. Drain Current (A)	SS (mV/dec)	DIBL (mV/V)	ION (µA)	IOFF (µA)	ION/IOFF
10	−0.21461	6.43265 × 10−6	3.74606 × 10−5	85.882	120	31.91620	7.30376	4.36983
20	0.216574	4.07531 × 10−6	3.23924 × 10−5	80.164	70.1652	24.0208	0.107591	223.2615
30	0.37356	3.1868 × 10−6	2.95 × 10−5	73.25	56.9015	20.0967	3.05421 × 10−4	6.5800 × 104
40	0.511143	3.15754 × 10−6	2.76015 × 10−5	66.1718	46.4723	17.7135	1.31798 × 10−5	1.343985 × 106
50	0.622054	3.10029 × 10−6	2.720923 × 10−5	64.9612	44.8533	16.8105	4.95607 × 10−6	3.391905 × 106
60	0.671832	3.05913 × 10−6	2.698054 × 10−5	63.2760	42.8955	16.7533	3.9426 × 10−6	4.249305 × 106

compares the proposed architectures with gate lengths between 10 and 60 nm in terms of DIBL, on and off current, saturation slope, SS, maximum drain current, threshold voltage, and gate length. This study demonstrates that the SS of CGAA-JLFETs with channel lengths of 40, 50, and 60 nm is remarkably close to the ideal value of 60 mV/dec, at approximately 66 mV/dec, 64 mV/dec, and 63 mV/dec, respectively. Finally, we have compared the performance of Si-based CGAA-JLFETs with those accessible architectures in the literature in

Table 5. Performance comparison of the proposed CGAA-JLFET with other device architectures.

Device Architectures	Sources	Lg (nm)	SS (mV/dec)	DIBL (mV/V)	ION (µA)	IOFF (µA)	ION/IOFF
CGAA-JLFET	Present Study	60	63.2760	42.8955	16.7533	3.9426 × 10−6	4.249305 × 106
FinFET	Published Study [29]	60	85.41	120	-	-	1.61 × 107
UTBB MOS43	Published Study [30]	60	90	130	-	-	-
LDMOS	Published Study [31]	60	70.061	116.853	-	-	-
SDMOS	Published Study [31]	60	70.811	119.609	-	-	-
CGAA-JLFET	Present Study	40	66.1718	46.4723	17.7135	1.31798 × 10−5	1.343985 × 106
JL FinFET PMOS	Published Study [32]	40	90	-	15.4	-	105
JL FinFET NMOS	Published Study [32]	40	92	-	52.3	-	107

. The complete evaluation of CGAA-JLFETs’ SCE recovery depends on performing quantitative checks between planar MOSFETs and CGAA FETs. The data in Table 5 present the main performance characteristics of CGAA-JLFETs along with planar MOSFETs and FinFETs, which establish the superior capabilities of cylindrical electrostatics. To further illustrate the advantages of CGAA-JLFETs over traditional transistor architectures, Table 5 provides a direct numerical comparison with planar MOSFETs and FinFETs. A performance comparison shows that CGAA-JLFETs deliver superior results because they have I_ON/I_OFF ratios at ~10⁶ while planar MOSFETs reach only ~10³ along with SS at ~63 mV/dec versus planar MOSFETs at ~80–100 mV/dec and reduced DIBL at ~42 mV/V below planar devices at ~100+ mV/V. Threshold voltage roll-off and leakage current decrease significantly because the fully enclosed gate structure ensures superior electrostatic control. The CGAA design prevents channel transits from depleting while providing enhanced gate coupling to deliver better drive current performance than flat MOSFET structures. Table 5 demonstrates the superior characteristics of CGAA-JLFETs by comparing them directly with classic MOSFETs and FinFETs through numerical data.

4.4. High Frequency Characteristics and Circuit Relevance of Si-Based CGAA-JLFET with Different Channel Lengths

As for semiconductor devices, the channel length of a CGAA-JLFET greatly affects its performance. Since high-speed, low-power devices are in high demand, their behavior as channel lengths changes should be studied. In this study, the AC analysis is conducted on a CGAA-JLFET with channel lengths variation from 10 nm to 60 nm. The main purpose is to analyze the changes in transconductance, output conductance, the unity gain cut-off frequency, and capacitance as the channel length changes. We explore these relationships to obtain deeper insights into the trade-offs between high frequency performance, power efficiency, and device scalability. This analysis of the scaling-based enhancement of the characteristics of CGAA-JLFET aids in the design of CGAA-JLFET for applications ranging from high-speed devices to low-power devices, and essentially, a more thorough understanding of the effects of scaling in nanoelectronics can be achieved. Figure 12 presents the simulated transfer characteristics of CGAA-JLFET for AC analysis at different channel lengths ranging from 10 nm to 60 nm. These I_D-V_GS characteristics of the CGAA-JLFET have been plotted at V_DS = 1.0 V, spanning a range of V_GS from 0 to 1.5 V with a 10⁹ Hz frequency. Figure 13 shows transconductance variation against gate voltage with different channel lengths of CGAA-JLFET. The combined results of Figure 12 and Figure 13 have been compiled in

Table 6. High-frequency characteristics-based performance comparison of the proposed CGAA-JLFET with different channel lengths.

Lg (nm)	Max. Drain Current (A)	Max. Transconductance (Siemens)	Max Oscillation Frequency (GHz)
10	4.37285 × 10−5	2.92304 × 10−5	1969.02945
20	4.28113 × 10−5	4.20951 × 10−5	1460.14232
30	4.2689 × 10−5	4.8144 × 10−5	1044.51938
40	4.23783 × 10−5	5.43787 × 10−5	761.921066
50	4.20062 × 10−5	7.06235 × 10−5	477.220384

.

Table 6 shows the maximum drain current, maximum transconductance, and maximum oscillation frequency of a CGAA-JLFET with different channel lengths (10 nm, 20 nm, 30 nm, 40 nm, and 50 nm). Further data on how the channel length affects the transistor performance, conducting current, switching efficiency, and operating at high frequency are needed. It is obvious from Table 6 that the maximum drain current slightly decreases as the channel length increases from Table 6. For example, at 10 nm, the maximum drain current is 4.37285 × 10⁻⁵ A, and at 50 nm, it reduces to 4.20062 × 10⁻⁵ A. It aligns with FETs’ well-known behavior, as longer channels result in a less efficient current passage because of increased resistance and parasitic effects. When the channel length increases, the effective gate control of the channel is less, making it difficult to drive current through the device. The trend in the maximum transconductance is also similar. The transconductance obtained is 2.92304 × 10⁻⁵ Siemens at 10 nm; however, the channel length harms the transconductance. At maximum, for 50 nm, it provides the transconductance value in the order of 7.06235 × 10⁻⁵ Siemens. Since the gate voltage controls the drain current less effectively, the device’s transconductance decreases as the channel length increases. Furthermore, the channel length also decreases the maximum oscillation frequency. Finally, we obtained the maximum oscillation frequency of 1969.02945 GHz at 10 nm, which decreases as we move down to 50 nm, where the frequency becomes 477.220384 GHz.

Therefore, based on the above discussion, it has again been shown that higher channel lengths lead to poorer device switching speeds, which further reduces the maximum oscillation frequency of the device, while lower channel lengths result in higher cut-off frequencies, allowing it to be operated at higher speeds. From the data in Table 6, we can conclude that this data agrees with the findings of the plot and previous analysis that shorter channel lengths (e.g., 10 nm) exhibit better high frequency performance, higher transconductance, and larger drain currents, which is why these are good for switching speeds. On the other hand, the longer channel lengths (e.g., 50 nm) are more stable and have lower leakage and parasitic effects than shorter lengths, but they also run at lower frequencies and have reduced current driving capabilities. They show the importance of choosing an appropriate channel length and the trade-off between speed, power, and stability for the specific application.

Figure 14 illustrates how the unity gain cut-off frequency depends on the gate-to-source voltage of a CGAA-JLFET with different channel lengths of 10 nm, 30 nm, and 40 nm. It shows that the cut-off frequency as a function of gate-to-source voltage reveals the effect of channel length on the device’s high frequency performance. The cut-off frequency, f_T, can be expressed in Equation (4), where g_m is transconductance, and C_gg is output capacitance:

$${\mathrm{f}}_{\mathrm{T}}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}}}{2\mathsf{\pi }{\mathrm{C}}_{\mathrm{g}\mathrm{g}}}},$$

(4)

As such, from Figure 14, it is clear that the 10 nm channel length exhibits the highest unity gain cut-off frequency of all gate voltages, with the voltage rising from 0 to approximately 1.5 V. This implies that the switch time is faster with reduced SCEs of transistors, and the shorter channel length provides better gate control due to enhanced field penetration with an effective change in work function. At smaller dimensions, the influence of the gate controls the channel’s conductivity and improves its operating frequencies. Although a shorter channel length improves performance faster, it may also bring extra leakage currents and probably threshold voltage roll-off that may affect long-term operating transistors in its practical applications. However, the unity gain cut-off frequency decreases as the channel length increases to 30 and 40 nm. This is likely due to increased parasitic capacitances from the larger physical dimensions of the channel. Furthermore, longer channel lengths result in stronger SCEs that result in less gate control over the channel, lowering the device’s capability of switching at high frequencies. While the 10 nm transistor has a reduced cut-off frequency, the 30 nm and 40 nm transistors have a reduced cut-off frequency as well. These devices are less prone to leakage and provide closer to comparable dynamic stability as the 10 nm transistor, especially at higher gate voltages.

Experimental results show that the CGAA-JLFET for 10 nm, 30 nm, and 40 nm follows the same voltage dependency curve, and the unity gain cut-off frequency increases as the gate-to-source voltage increases. The channel conductivity is improved as the gate voltage increases, giving the device the potential to function at higher frequencies. However, the cut-off frequency increases, but only up to a certain gate voltage threshold, after which it becomes saturated, indicating a transition into saturation mode where the variation in drain current concerning gate voltage is not substantial. Figure 14, overall, shows the trade-offs between channel length and high frequency performance. However, shorter channels such as the 10 nm device have better performance concerning speed and frequency response but come with problems such as leakage current and problems of SCEs. The 30 nm and 40 nm channels appear to scale better to longer channels, where slower switching speeds, as compared to the 10 nm and 20 nm channels, may be acceptable because of the greater power efficiency and stability [33,34,35].

Figure 15 illustrates gate capacitive variation against gate voltage for 40 nm CGAA-JLFET. In CGAA-JLFET, gate capacitance (C_gg) or gate-to-channel capacitance is one of the important parameters. The capacitance between the transistor’s gate and channel region is important in determining the device frequency response, switching speed, and other parameters. In CGAA-JLFET, C_gg depends on the 2D gate geometry, and the cylindrical gate enables stronger channel electrostatic control than in the planar devices. As channel length decreases, the gate capacitance increases since the gap between the gate and channel can be decreased. That makes the device better at controlling the current flow. While this increase in gate capacitance can cause higher parasitic delays, the resulting higher parasitic delays can be an issue for the transistor’s high frequency performance. Since C_gg directly affects transistor transconductance, cut-off frequency, and dynamic behavior in AC analysis, it is important to understand C_gg in AC analysis and to become as small as possible, which helps in having a minimum capacitive delay in high-speed applications.

5. Performance Analysis—Si vs. GaAs-Based CGAA-JLFETs

Materials that contain group III elements (such as aluminum, gallium, and indium) and group V elements (such as nitrogen, phosphorus, arsenic, and antimony) of the periodic table are referred to as group III–V materials. This combination of materials has a direct energy band gap and unique electrical and optoelectronic characteristics. A comprehensive investigation of a three-dimensional JLFET with a cylindrical gate-all-around architecture has also been performed using GaAs, III–V material. The channel material used to construct the device construction shown in Figure 16 is GaAs. The device gate length is 40 nm, and the radius is 10 nm. The Silvaco ATLAS tool is utilized in this simulation. The Shockley-Read-Hall and AUGER recombination models analyzed the recombination effects at high current densities. Equations with linked and decoupled forms were modified to integrate the NEWTON and GUMMEL models. The electrical properties of a novel transistor CGAA-JLFET with an all-around gate layout are simulated in this paper. The recommended device parameters are listed in

Table 7. Device parameters of the GaAs-based CGAA-JLFET.

Parameters	GaAs-Based CGAA-JLFET
Channel material	Gallium Arsenide (GaAs)
Mesh length, angle, radius	$\mathrm{In} \mu$m
Region	Semiconductor, Silicon Oxide, Conductor for Source, Channel, and Gate
Channel region with doping concentration	N-type–1019 cm−3
Source region with doping concentration	N-type–1019 cm−3
Drain region with doping concentration	N-type–1019 cm−3
Gate material	P+ polysilicon
Gate work function	5.4 eV
Oxide permittivity	3.9
Channel length	40 nm
Oxide thickness	2 nm
Semiconductor (GaAs-Substrate) thickness	10 nm (radius)
Device length	60 nm

, and the different properties of silicon and GaAs are discussed in

Table 8. Properties of silicon and GaAs material.

Property	Value for GaAs	Comparison with Silicon
Electron mobility	8500 cm2/V·s	Higher than silicon, enabling high-speed devices
Band gap	1.42 eV (Direct Band Gap)	Efficient for optoelectronics such as LEDs and laser diodes
Saturation velocity	1 × 107 cm/s	Higher than silicon, it contributes to faster switching speeds
Breakdown voltage	higher than silicon	Suitable for high-power and high-voltage applications
Crystal structure	Zinc-blende	Similar to diamond, but with Ga and As in tetrahedral configuration
Lattice constant	5.653 Å	It affects material properties and device performance
Thermal conductivity	46 W/m·K	Lower than silicon, which can be a disadvantage in high-power applications
Thermal expansion	5.8 × 10−6/°C	Different from silicon, which may cause thermal stress
Young’s modulus	85–90 GPa	Relatively lower than silicon, making it more flexible
Hardness	Higher than Silicon	It makes GaAs more durable and resistant to scratching
Photoluminescence	Excellent	Used in optoelectronics such as LEDs and laser diodes
Absorption spectrum	High in infrared	Useful for solar cells and photodetectors in the infrared range
Applications	High frequency devices, optoelectronics, power electronics	Widely used in communications, high-speed electronics, and photonics
Cost	Higher than Silicon	Manufacturing GaAs is more expensive than silicon

.

Modern semiconductor technology values CGAA-JLFET for its simple structural design that eliminates p-n junctions, thus making them optimal for low-power and high frequency applications. A simple device structure reduces costs while improving reliability and optimizing current transmission in CGAA-JLFET. High-speed and high frequency applications demonstrate better performance from GaAs-based CGAA-JLFET over Si-based CGAA-JLFET because GaAs offers superior electron mobility, higher drift velocity, and reduced leakage currents. Figure 17 illustrates the 40 nm different III–V materials-based (GaAs, InP, AlGaAsP, GaN, InGaAsP, GaP) CGAA-JLFETs output characteristics at various V_GS = 1.0 V with V_DS ranges from 0 to 1 V. The output curve of the GaAs part shows significant saturation at a higher current level than the corresponding curve being developed here but at higher drain voltages. In GaAs-based CGAA-JLFET, GaAs’s higher electron mobility leads to a much sharper increase in current with increasing drain voltage. It improves current drive and switching behavior. Due to GaAs’s superior material properties, the output curve has generally higher saturation currents at a given drain voltage, particularly at smaller channel lengths. However, for the silicon-based CGAA-JLFET, the output characteristics generally show that the output current gradually increases as the drain voltage increases. Due to slower electron mobility in silicon, the current drive capability is usually lower.

Figure 18 presents the simulated transfer characteristics of 40 nm different III–V material-based (GaAs, InP, AlGaAsP, GaN, InGaAsP, GaP) CGAA-JLFET and P+ polysilicon, which have been used to fulfill the high gate work function requirement to achieve an appropriate V_th value. The transfer characteristics of GaAs-based CGAA-JLFET yield faster on-to-off-state transitions because GaAs exhibits higher electron mobility than silicon-based CGAA-JLFET. GaAs devices demonstrate lower subthreshold swing characteristics and rapid switching processes; thus, they can operate effectively with reduced gate voltage requirements. However, silicon-based CGAA-JLFET demonstrates slower behavior between on and off states because of the decreased mobility of carriers.

The current flow lines of a 40 nm CGAA-JLFET made of silicon and a 40 nm CGAA-JLFET made of GaAs are depicted in Figure 19. The current flow lines of 0.45 for silicon and 0.53 for GaAs-based JLFETs are shown in Figure 18. Both drift and diffusion phenomena affect current in silicon-based CGAA-JLFETs, and because of the indirect energy bandgap, current flow lines are directly driven by the voltages. Similar to silicon, drift and diffusion phenomena affect current in GaAs-based JLFET. However, GaAs has a direct energy band gap, meaning current flow lines are more concentrated and less dispersed than in silicon.

The electron concentration of a 40 nm CGAA-JLFET made of silicon and a 40 nm CGAA-JLFET made of GaAs is displayed in Figure 20. Understanding the carrier density or electron concentration is essential to comprehending any device’s electrical operation. Temperature, inherent properties, and doping can also have an impact. The highest electron concentration, up to 10¹⁹ cm⁻³, for both silicon and GaAs-based CGAA-JLFETs is displayed in Figure 20. Compared to silicon CGAA-JLFET, GaAs-based CGAA-JLFET has deeper and greater electron concentrations [36,37,38].

Figure 21 shows the electric fields of 40 nm silicon and GaAs-based JLFETs. A key element in evaluating the performance of any device is the electric field distribution, which is impacted by the material properties, doping profiles, and device structure. However, increased current mobility in GaAs-based JLFETs results in more concentrated and distinct electric field lines. The GaAs JLFET’s electric field distribution is less diffused and more concentrated around the gate region, allowing it to control the conduction process more precisely. Due to the wide bandgaps and high mobility of GaAs, GaAs-based devices use better electrostatic control, higher drive currents, and quicker electron transport than silicon devices [39,40]. Figure 22 demonstrates transconductance for different III–V materials-based (GaAs, InP, AlGaAsP, GaN, InGaAsP, GaP) channel materials.

Table 9. Performance comparison of 40 nm GaAs and silicon-based CGAA-JLFET according to this work.

Si and III–V Material	Vth (V)	Saturation Slope (A)	Max. Drain Current (A)	SS (mV/dec)	DIBL (mV/V)	ION (µA)	IOFF (µA)	ION/IOFF	Sources
GaAs	0.819608	6.41239 × 10−7	2.31345 × 10−5	64.47608	30.5962	12.7614	1.125467 × 10−9	1.133861 × 1010	Present Work
Si	0.511143	3.15754 × 10−6	2.76015 × 10−5	66.1718	46.4723	17.7135	1.31798 × 10−5	1.343985 × 106	Present Work

shows the performance comparison of 40 nm GaAs and silicon-based CGAA-JLFETs with different parameters. For the most part, GaAs-based CGAA-JLFET has better output and transfer characteristics, SS and DIBL, than silicon-based CGAA-JLFET owing to the higher electron mobility and improved material properties of GaAs. GaAs-based devices are faster-switching devices, have a smaller subthreshold swing, and lower leakage currents, and consequently, they are suitable for high-speed and low-power applications. However, performance limiting issues such as higher leakage currents, slower switching characteristics, and higher DIBL, result in limited performance in some advanced, miniaturized applications for the silicon-based CGAA-JLFET, which, although cost-effective, is easy to integrate with the existing CMOS technologies.

The current research collected for different materials within the group III-V semiconductors sets SS, and DIBL parameters for analysis as shown in

Table 10. Numerical data for SS and DiBL.

Various III–V Materials	SS (mV/dec)	DIBL (mV/V)	Sources
GaAs	64.47608	30.5962	Present Work
InP	66.8384	39.4156	Present Work
AlGaAsP	64.44775	40.81138	Present Work
GaN	68.34655	40.35768	Present Work
InGaAsP	66.83845	39.41564	Present Work
GaP	67.84844	22.50066	Present Work

. The efficiency with which a transistor switches on and off is measured and represented by SS in mV/dec, and the lower this value gets the better the performance. A lower value of DIBL, which is expressed in mV/V and measures the extent to which drain voltage affects threshold voltage, indicates better control of SCEs. Out of this set of materials, both GaAs and AlGaAsP had the lowest SS values of approximately 64.4 mV/dec, indicating they have the best efficiency from this cut of sample GaP concedes the lowest DIBL value at 22.50 mV/V also signifying weak SCEs. On the opposite side, GaN has the highest SS and DIBL values which are both suggestively indicative of inactive control over switching and SCEs. This offers a glimpse into the variety of performances present in the group III-V materials, showing how advanced they can be used in transistors and their performance.

The CGAA-JLFET exhibits important advantages such as low power and high frequency operation, and channel length is one of the key parameters to enhance performance. GaAs-based CGAA-JLFET outperforms silicon-based CGAA-JLFET consistently as the channel length reduces from 60 nm to 10 nm, owing to the higher electron mobility, lower leakage currents, and higher speed of switching of the former, making GaAs-based CGAA-JLFET favorable for high frequency and low power operation. However, GaAs has the highest power efficiency and speed at channel lengths (10 nm to 30 nm) compared to Si-based JLTs because of leakage and slow switching in the latter. Increasing the channel length (40 nm to 60 nm) to Si-based CGAA-JLFET makes better sense in low-cost and low-power devices, while GaAs continues to lead on high-speed and high frequency operations. Therefore, GaAs is used for high-performance, low-power devices because of their inherently small electron mobility, while silicon is used for general-purpose devices.

The detailed output and transfer characteristics measurement of the 40 nm GaAs-based CGAA-JLFET represents only part of the research, while a complete comparative analysis requires multiple channel length testing to examine Si-based CGAA-JLFETs. The following research will pursue a study of GaAs-based devices starting from a 10 nm channel up to 60 nm to assess their scalability potential along with their short-channel behavior. This research extensively evaluates Si- and GaAs-based CGAA-JLFETs to study how material selection affects performance results. The research utilizes an improved electrostatic computational method based on cylindrical coordinate Poisson’s equation analysis, which previous works have only superficially examined. SILVACO ATLAS runs extensive 3D numerical simulations to assess performance metrics, including leakage current, SS, and DIBL. The GaAs-based CGAA-JLFETs deliver better high-speed, low-power performance results supported by unity gain cut-off frequency measurements and transconductance and output conductance variation metrics. GaAs-based transistors demonstrate superior electrostatic control with better switching performance and lower leakage current behavior, which qualifies them as leading materials for advanced ultra-scaled transistor designs.

6. Conclusions

Therefore, in summary, CGAA-JLFET is a major step forward in semiconductor technology due to the elimination of the conventional p-n junctions, which helps to reduce the number of device layers and improve the device performance. The reduced complexity of CGAA-JLFET is the key advantage because it results in lower fabrication costs and higher reliability. GaAs-based CGAA-JLFETs are advantageous over silicon-based CGAA-JLFETs due to their higher electron mobility, higher drift velocity, and lower leakage currents, facilitating higher speed, higher frequency, and low power requirements. Si-based CGAA-JLFET has become more cost-attractive and more easily integrated into existing manufacturing processes, but GaAs-based CGAA-JLFET has greater performance requirements for niche applications where higher efficiency and faster switching are required. Finally, choosing between silicon and GaAs junctionless transistors depends on the application, cost, speed, or power consumption. The characteristics of the two materials make them suited to different purposes, but GaAs holds the most potential concerning future high-performance devices.

Research results show that using a cylindrical gate-all-around junctionless transistor (CGAA-JLFET) structure effectively reduces short-channel effects while increasing device performance standards. A cylindrical gate provides a full channel enclosure, allowing improved electrostatic control, DIBL suppression, and threshold voltage stability under state-of-the-art device dimensions. With its planar and FinFET-free configuration, this device architecture maintains even potential distribution, thus minimizing the performance-deteriorating effects of charge sharing. The improved gate-to-channel capacitance potential of CGAA-JLFETs enables enhanced on/off current ratio performance with decreased leakage currents, so the devices work exceptionally well in low-power and high frequency applications. The comparative research on Si-based and GaAs-based CGAA-JLFETs demonstrates that III–V materials enable rapid carrier movement and high-speed operation. The obtained research results bolster beyond-CMOS semiconductor technology enhancement while validating the prospective usage of CGAA-JLFETs in next-generation nanoelectronics development.

The research introduces the original analysis of cylindrical GAA-JLFETs and essential breakthroughs that boost operational effectiveness and scalability properties. This research compares conventional silicon junctionless transistors by evaluating Si- and GaAs-based CGAA-JLFETs concerning SCEs, subthreshold behavior, and high frequency performance. The study demonstrates GaAs’ high-speed and low-power operation potential through refined electrostatic modeling and three-dimensional numerical simulations. The results enable researchers to enhance their selection of materials, electrostatic control methods, and device scale-up approaches for beyond-CMOS technology development. The current research will continue with experimental testing and III–V material analysis to develop optimal performance levels for upcoming technology applications.

7. Limitations, Future Work, and Experimental Validation

Further research must investigate temperature-dependent effects alongside doping non-uniformities because this study provides extensive material analysis and SCE evaluations of CGAA-JLFETs. Temperature changes might affect power efficiency since they modify threshold voltage, carrier mobility, and leakage currents. Different types of doping profiles throughout the device can create more unpredictable changes to fundamental device properties. The proposed design will receive future research attention regarding temperature-dependent modeling and changes to doping control through atomic layer doping (ALD) and ion implantation optimization to boost overall design reliability.

Research into GaAs-based CGAA-JLFETs needs experimental verification to determine practical implementation feasibility. Laboratory fabrication of prototype devices and their characterization will evaluate simulation outcomes. A parameter tuning process based on III–V semiconductor transistors experimental data sets will be performed to improve model accuracy levels.

Manufacturing at scale becomes complicated due to the high fabrication difficulty and production costs of CGAA-JLFETs as they surpass both planar MOSFETs and FinFETs in terms of performance attributes. Making nanowires, controlling uniform doping levels, and integrating with CMOS technologies present the main barriers to overcome. EUV lithography and NIL represent advanced top-down fabrication methods demonstrating capacity for CMOS-quality manufacturing at high production yields of CGAA transistor chips. Process variability became manageable through platform advancements that combined atomic layer doping (ALD) and self-aligned gate fabrication schemes.

The present study centers on material selection and short-channel effects in CGAA-JLFETs, yet other variables, including oxide thickness, doping profile, and gate material, play important roles in modifying device characteristics. The thickness of oxide controls electrostatic responses and leakage conductance, and doping determines carrier movement, modifying threshold voltages. Any gate material work function modification leads to changes in device-switching protocols. Future development of CGAA-JLFET performance requires a comprehensive quantitative assessment of these influencing factors and their optimal selection.

Besides assessing the electrical properties of GaAs- and Si-based CGAA-JLFETs, thermal management and long-term reliability are key factors determining device performance for real-world applications. Thermal effects are an important factor in device performance, affecting parameters such as carrier mobility, threshold voltage stability, leakage currents, and total device lifetime. Likewise, transistors’ long-term reliability relies on self-heating phenomena, material aging, and bias-induced instability under prolonged operating periods. GaAs-based CGAA-JLFETs have lower thermal conductivity (~46 W/m·K) compared to their silicon counterparts (~150 W/m·K) and, therefore, may show higher self-heating effects, resulting in higher junction temperatures, degradation in carrier mobility, and reliability issues such as threshold voltage shifts and changes in leakage currents over time. In addition, self-heating can enhance short-channel effects, which affect subthreshold slope and drain-induced barrier lowering (DIBL). Although our work does not involve direct thermal simulations, previous studies indicate that using high-thermal-conductivity substrates, optimizing gate dielectric materials for them, and using efficient heat dissipation methods can reduce thermal issues. Likewise, long-term reliability issues such as bias temperature instability (BTI), hot carrier effects (HCE), and material degradation need to be investigated to further improve the performance of CGAA-JLFET for high frequency and low-power applications. Subsequent work will integrate thermal simulations with experimental verification to yield a more complete evaluation of these factors.

Scalability-wise, silicon-based CGAA-JLFETs meet the International Roadmap for Devices and Systems (IRDS) requirements for sub-10 nm technology nodes, enabling their long-term use in future semiconductor production. GaAs has higher performance features, but their scalability is limited by high manufacturing costs, the inability to reach ultra-small feature sizes, and specific processing procedures. Due to their cheaper production costs, CMOS compatibility, and greater scalability, silicon-based CGAA-JLFETs are still the best choice for mass semiconductor applications. However, GaAs-based devices offer potential in high-performance computing, RF technologies, and high-speed optoelectronics. Future work needs to aim to create low-cost integration methods that allow GaAs transistors to be effectively integrated into silicon-based ICs, trading off the benefits of high-speed performance against cost feasibility. With the aid of heterogeneous integration and 3D monolithic integration developments, GaAs transistors might complement silicon-based CGAA-JLFETs in situations where ultra-high-speed and low-power operations are necessary.

CGAA-JLFETs are promising for low-power, high-speed logic applications, especially subthreshold and RF circuits. Their strong electrostatic control reduced SCEs, and scalability make them ideal for memory arrays, logic circuits, and analog/RF front-end systems. Future studies will examine the effects of CGAA-JLFETs in complementary logic modes, such as junctionless CMOS (JL-CMOS) circuits, on power consumption, switching time, and signal integrity in large-scale circuits. This research could be enhanced by system-level comparisons of CGAA-JLFETs to neuromorphic computing, energy-efficient processors, and future mobile and Internet of Things devices. System-level performance, including temperature stability, process variability, and reliability in complex circuit topologies, determines CGAA-JLFETs’ commercial feasibility. To determine their practicality, CGAA-JLFET circuits can be compared against FinFET-based and classic CMOS circuits based on power-delay-product (PDP), energy efficiency, and circuit complexity. Future research will examine compact circuit models, SPICE-based simulation, and CGAA-JLFET integration in digital and analog/mixed-signal circuit design. To make CGAA-JLFET circuits practical, interconnect effects, parasitic capacitances, and system-level signal integrity must be investigated.

In real fabrication, parameter variations such as gate length, oxide thickness, channel doping, and junction depths can introduce threshold voltage shifts, elevated leakage currents, and subthreshold slope variations. These non-idealities can degrade electrostatic control, affecting short-channel effects (SCEs), drain-induced barrier lowering (DIBL), and device reliability. Though this research emphasizes the simulation-driven study of CGAA-JLFETs, practical manufacturing introduces unavoidable process variability, i.e., gate length fluctuations, oxide thickness, doping concentration, and lithographic patterning errors, which can profoundly affect device behavior. These discrepancies can cause threshold voltage shifts, increased leakage current, deteriorated subthreshold slope, and increased SCEs, affecting the overall reliability and scalability of CGAA-JLFETs. Even though process variability was not explicitly accounted for in our present simulations, future studies need to include statistical variation modeling, Monte Carlo simulations, and experimental verification to quantify the influence of fabrication-induced deviations on CGAA-JLFET properties. Additionally, material-dependent variation sensitivity analysis, especially in GaAs-based devices, would yield a better understanding of manufacturability issues and integration viability within standard semiconductor technology. Knowledge of these process-induced variations is important for determining the robustness and large-scale production feasibility of CGAA-JLFETs and making them useful in next-generation electronic systems.