Radiation-Hardened Design and Experimental Validation Using a Mixed-Stage Model for Reliability Assessment of Integrated Circuits in Radiation Environments

Abstract

With advances in space, nuclear, and defense industries, the susceptibility of semiconductor integrated circuits (ICs) to radiation has increased. Radiation-induced degradation and malfunctioning of IC performance can lead to system failure, leading to significant damage. To address this limitation, this study employed mixed-stage modeling and simulation (M&S) techniques to evaluate the reliability of complementary metal-oxide semiconductor application-specific ICs (ASICs) in radiation environments. Radiation-hardened IC chips were designed and fabricated using layout modification techniques based on M&S. The ASIC, which includes the D-latch and Operational Amplifier (Op-Amp) circuits, was validated for resistance up to a total ionizing dose of 20 kGy(Si). The proposed radiation-hardened ICs demonstrated stable performance even in radiation-exposed environments, ensuring reliable operation under such conditions. The findings provide insights into overcoming radiation-induced degradation and malfunction in semiconductor integrated circuits, which is particularly relevant for advancing space, nuclear, and defense industries.

1. Introduction

With the Fourth Industrial Revolution emergence, the demand for specialized-purpose semiconductors in advanced aerospace, nuclear power, and defense industries has increased. Electronic devices used in various fields, including nuclear power plants, space exploration, defense, healthcare, unmanned aerial vehicles, and autonomous driving, are exposed to total ionizing dose (TID) effects caused by radiation.

Integrated circuits (ICs) comprising complementary metal-oxide semiconductors (CMOSs) are vulnerable to radiation-induced issues causing performance degradation and malfunction. Ensuring system safety where failure could result in loss of life requires radiation-hardening designs for the electronic chips in these systems.

Radiation accidents may occur in the healthcare sector due to errors in radiation source calculations for therapy or malfunctions of X-ray machines and accelerators. Data errors in unmanned aerial vehicles and autonomous systems can lead to critical failures, such as incorrect obstacle detection during navigation [1,2,3,4].

To mitigate these risks, various efforts have been made to enhance the radiation hardness of semiconductors. Recently, research has focused on applying non-silicon technologies, such as ferroelectric devices, to achieve higher radiation resistance compared to CMOS [5]. However, issues such as increased leakage current, threshold voltage shifts, and changes in ferroelectric properties due to radiation exposure still persist. Furthermore, these technologies have primarily been utilized in device and memory applications, limiting their implementation in integrated circuits (ICs).

Therefore, research on radiation-hardened CMOS technology, which is universally used in IC fabrication, has been actively conducted. In particular, layout modification techniques have been applied to enhance the radiation tolerance of n-MOSFETs, which are vulnerable to total ionizing dose (TID) effects. This approach maintains the standard CMOS process while adding or modifying specific layers, thereby extending the radiation hardness of vulnerable devices to the IC level. Additionally, it provides the advantage of improving radiation resistance without requiring extra circuits or logic (which can lead to slower speeds and increased chip size) or additional process masks (which can be costly) [6,7].

The existing ELT (Enclosed Layout Transistor) [8], which applies radiation-hardened techniques, provides excellent resistance up to a total ionizing dose (TID) of 300 kGy(Si). However, due to its structural characteristics, it imposes several limitations in semiconductor circuit design, including restrictions on the channel width-to-length (W/L) ratio, high gate capacitance, and asymmetric characteristics between the source and drain. The DGA (Dummy Gate-Assisted) n-MOSFET [9] was developed to address these issues in ELT. However, this structure introduces an additional P-active and p+ layer compared to a conventional n-MOSFET, which results in an increase in the channel size beyond the original W/L ratio. Consequently, remodeling of the channel W/L ratio is required. Additionally, the H-gate n-MOSFET in Ref. [10] extends the N-active region from a standard n-MOSFET to block leakage current between the source and drain. However, since this extended N-active region alters the channel size (W/L), it poses challenges in applying to analog circuit designs that require fine-tuned W/L ratio adjustments.

In this study, we designed a RT-nMOS (radiation-tolerant n-MOSFET) that overcomes the drawbacks of these existing devices. To implement radiation-hardened technology for ICs based on the designed n-MOSFET, we applied a mixed-stage modeling and simulation (M&S) approach, which enables the prediction of radiation effects on ICs in advance. Using this method, we analyzed radiation-induced damage in n-MOSFETs and designed an optimized RT layout structure. The optimized RT-nMOS was applied to a D-Latch and a two-stage Op-Amp IC to verify its radiation tolerance at the circuit level before being fabricated into a chip using a 0.18 μm CMOS process. The fabricated chip underwent radiation testing at the high-dose gamma-ray irradiation facility of the Jeongeup Advanced Radiation Technology Institute. The results confirmed successful radiation tolerance up to a total ionizing dose of 20 kGy(Si).

The mixed-stage M&S approach, which combines device- and circuit-level analysis, improves the inefficiency of traditional radiation-hardened technology development, which relies on repeated chip fabrication and radiation testing. Additionally, it provides a radiation tolerance evaluation solution by addressing the complex radiation effects in semiconductors.

2. Optimization of Radiation-Hardened Layouts for CMOS Devices

2.1. Total Ionizing Dose Effects in CMOS Devices

The TID effect refers to the gradual degradation and malfunction of CMOS-based electronic devices caused by prolonged exposure to ionizing radiation. The thick insulating oxide layer is the most sensitive to TID effects, where radiation-induced trapped charges accumulate. A strong correlation exists between the oxide thickness and threshold voltage shifts in devices. Thicker oxide layers trap more charge, shifting threshold voltage and disrupting normal device operation.

In older micron-scale CMOS processes, the gate oxide thickness was several hundred nanometers, making charge trapping in the gate oxide due to radiation a cause of performance degradation. Modern submicron processes have gate oxide thicknesses below 10 nm, rendering them nearly immune to the radiation effects on the gate oxide. Therefore, current concerns focus on the fixed charges induced by the TID effects in insulating oxide layers with thicknesses of several hundred nanometers [11].

The process of TID (total ionizing dose) effect in a MOS structure occurs as follows. Radiation possesses energy exceeding the bandgap of SiO₂, generating electron-hole pairs (EHPs) within the SiO₂ layer. The generated electrons and holes moved due to the bias applied to the gate. For an n-MOSFET, when a positive bias is applied to the gate, electrons move toward the gate electrode, whereas holes migrate toward the bulk silicon.

Electrons with high mobility exit the SiO₂ layer. However, the lower-mobility holes undergo the SiO₂ layer via localized hopping states. Once the holes reach the Si/SiO₂ interface, they become trapped and form fixed charges. These fixed positive charges invert the channel in an n-MOSFET, influencing the conduction path between the source and drain. In the case of p-MOSFETs, the majority carriers in the channel are holes, so the positive fixed charges induced by the TID effect have little to no negative impact on p-MOSFETs [12,13]. Therefore, TID effect tolerance studies in the CMOS are primarily conducted on n-MOSFETs. Consequently, the fixed charges induce threshold voltage shifts, negatively affecting n-MOSFET parameters, including increased leakage current, reduced carrier mobility, and decreased transconductance. This radiation-induced phenomenon constitutes the TID effect, where damage progressively accumulates as the semiconductor is exposed to radiation [14].

Damage can propagate and accumulate in CMOS ICs owing to the cumulative radiation effects on n-MOSFETs. Electronic circuits, comprising combinations of dozens to hundreds of n-MOSFETs and p-MOSFETs, perform various functions, such as biasing, clock generation, reference voltage generation, amplification, data storage, filtering, and current/voltage conversion.

These circuits are combined to form electronic modules that handle control, measurement, communication, and power management functions. The integration density and complexity of circuits have been increasing to meet high-performance demands such as high speed, compact size, low power consumption, and high resolution. However, the circuits have become vulnerable to radiation exposure.

Moreover, by adding software-based digital signal processing technologies to electronic modules, the role of IC has become critical. Thus, analyzing the effect of radiation-induced leakage currents in n-MOSFETs, the fundamental units of electronic circuits, is essential. Leakage current can degrade the circuit performance and cause functional errors, leading to severe problems, including speed limitations, increased power consumption, and malfunctions in electronic modules.

2.2. Radiation-Hardened Structure Design for CMOS Devices

In this study, we established a mixed-stage M&S technique for designing radiation-hardened ICs that enhances the efficiency of electronic-chip development by enabling the damage propagation and accumulation prediction from n-MOSFETs to electronic circuits. We first developed ionizing radiation tolerance technologies for a transistor (Tr.) comprising ICs and assembled tens of radiation-hardened transistors to design radiation-tolerant ICs.

To protect radiation-sensitive n-MOSFETs in CMOS-ICs, we applied a layout-modification technique (LMT) that internally shields n-MOSFETs from radiation-induced fixed charges within standard CMOS processes. LMT enhances the radiation tolerance by altering n-MOSFETs structure. However, these modifications may affect the intrinsic channel area, varying the operating current and device characteristics [8,9,10].

Compensating these changes requires modeling approaches replacing conventional rectangular channel-size models. However, this resizing process introduces constraints regarding performance verification during IC design. Therefore, as illustrated in Figure 1, we propose a radiation-tolerant n-MOSFET (RT n-MOS) using an LMT. The proposed RT n-MOS was designed with a flexible structure for IC applications, ensuring stable performance in radiation environments.

The RT n-MOS incorporates an RT-layer module added and extended to the edges of the N-active region of the original n-MOSFET. This design effectively suppresses the formation of fixed charges in the insulating oxide layer, the primary source of radiation-induced damage, while maintaining the N-active region unchanged, ensuring no variation in the channel size (W/L).

Moreover, the thick insulating oxide layer, adjacent to the source and drain in conventional channel formation paths, was relocated to the outer boundary of the RT-layer module. Consequently, even if hole trapping occurs, no leakage current path forms between the source and drain, mitigating the radiation-induced damage. Additionally, the body (p-active, p+ layers, and via) of the RT-layer module is connected to ground, which expels trapped holes externally and increases the device threshold voltage to prevent channel inversion in the off state.

The polysilicon in the RT-layer module physically separates the p+ body from the n+ drain and source regions, preventing short-circuiting due to the silicide processes used in modern CMOS fabrication, eliminating the need for additional silicide-blocking layer process steps and improving manufacturing efficiency.

In conclusion, the RT n-MOS design effectively blocks fixed charge-induced leakage current, enhances the device’s operational stability, and improves the overall process efficiency. The polysilicon layer of the RT-layer module is adjustable within the contact range of the original gate region, allowing flexible configurations based on the relative position or orientation of the transistors during the circuit design. The folding layout technique, used in IC layouts, partitions the drain and source regions into smaller sections based on the number of transistor fingers, reducing the diffusion-to-well capacitance of the source and drain and minimizing electrical characteristic degradation. Additionally, it enhances circuit integration density.

The proposed RT n-MOS can efficiently incorporate the finger-layout technique (Figure 2), enabling selective signal-path adjustments as required. Therefore, RT n-MOSs are effective for designing radiation-tolerant ICs with high complexity and stringent performance requirements.

To ensure the radiation tolerance of CMOS ICs, M&S technology based on Silvaco TCAD Victory Device was applied to verify the robustness of stage-1 n-MOSFETs incorporating the Layout Modification Technique (LMT). Initially, a 3D model of the RT n-MOS was designed to extend into the logic or circuit stage-2. The dimensions were identical to those of standard structures susceptible to radiation damage, specifically 5/1 μm/μm, with doping concentrations aligned with the commercial 0.18 μm CMOS STI process conditions. The body thickness was 3 μm, with a substrate concentration of 2 × 10¹⁶/cm³, channel concentration of 1 × 10¹⁸/cm³, and source, drain, and body doping concentrations of 3 × 10¹⁸/cm³, matching those of standard transistors.

Current–voltage characteristics were simulated to examine the electrical impact of the RT-layer module added through the LMT structure. The simulations confirmed that the threshold voltage characteristic was approximately 0.75 V, and the saturation current reached 2.5 mA at a gate voltage of 3.3 V, identical to the performance of standard n-MOS transistors.

Radiation-induced charge-injection models were designed for the standard and RT MOS structures to predict the cumulative radiation tolerance of the RT n-MOS for integration into radiation-tolerant circuits (Figure 3). In this design, a ‘graded’ mesh was applied to the 3D semiconductor region to accommodate gradual variations in charge density and electric field, while a ‘fixed’ mesh was used for the insulator, metal, and other regions to maintain a uniform and constant grid size.

This model simulates the increase in charge generation at the Si/SiO₂ interface as radiation dose increases. The radiation-induced holes in SiO₂ migrate toward the Si side, forming positive fixed charges at the Si/SiO₂ interface. As the radiation dose increases, the fixed charge density also increases, causing electrons in the Si to migrate toward these fixed charges, unintentionally forming a conductive channel, which is referred to as a leakage current path. In this process, the interface charge (Q_IC), which contributes to channel formation, was introduced through donor doping. Based on experimental data, a donor doping concentration of up to 2 × 10¹⁸ cm⁻³ was applied to simulate a radiation dose of 12 kGy(Si). Figure 4 shows the simulation of the gate voltage switching characteristics with increasing charge injection. The results demonstrate that the RT n-MOSFET structure effectively resolved the leakage current issue in the off-state of standard MOSFETs under radiation-induced damage.

3. Radiation-Tolerant IC M&S and Implementation

The cumulative radiation effects on n-MOSFETs, comprising tens of thousands of components in an IC, require the modeling and simulation of radiation propagation and cumulative damage at the circuit level.

Among the simulation methods, Full-TCAD enables precise analysis of the physical characteristics of devices but has modeling limitations and high computational costs as the circuit complexity increases, making circuit-level simulation challenging. On the other hand, SPICE allows for fast circuit-level simulations but struggles to model physical damage effects such as radiation-induced degradation, leading to lower accuracy in the results.

Mixed-stage M&S, which combines these two approaches, enables realistic circuit operation predictions while incorporating radiation effects. This method offers advantages in terms of reduced computation time and improved accuracy. However, the initial modeling process for linking TCAD and SPICE parameters can be complex. A comparison of simulation methods for evaluating radiation effects in circuits with increasing integration density is summarized in

Table 1. Comparison of simulation methods for evaluating radiation effects with increasing circuit integration density.

Comparison Criteria	M&S Methods for Radiation Effects on ICs
	Full-TCAD	Full-SPICE	Mixed-Stage (This Work)
Computation Time	Very Long	Short	Moderate
Accuracy	Very High	Low	Medium to High
Modeling Precision	Device-Level	Circuit-Level	Device + Circuit-Level
Scalability with Complexity Increase	Low	High	Moderate
Applicability to Large Circuits	Small-Scale Transistor	Large-Scale System Analysis	Mid-Scale IC Analysis

. As integration density increases, the differences in each evaluation criterion are expected to become more pronounced.

In this study, an efficient mixed-stage M&S approach was conducted to predict the radiation effects on ICs. First, n-MOSFET model parameters were extracted from the current–voltage characteristics of both standard and radiation-tolerant models based on device-level radiation impact M&S results. Using these parameters, SPICE models for both standard and radiation-tolerant devices were created to construct integrated circuits, allowing for an evaluation of circuit degradation and radiation tolerance before and after cumulative radiation exposure.

The mixed-stage M&S approach not only captures the physical and electrical parameters within a single device but also accounts for radiation-induced leakage current effects. As a result, it provides accuracy equivalent to the Full-TCAD method while significantly improving simulation speed.

3.1. Mixed-Stage M&S for ASIC Radiation Effects

Mixed-stage M&S for radiation effects was conducted on two application-specific ICs (ASICs) types: an analog two-stage operational amplifier (Op-Amp) and a digital D-latch. First, the target n-MOSFET for M&S was selected using the TCAD Victory Device tool, and a 3D model was designed by applying process variables such as materials, structure, and doping. The designed model was then used to simulate radiation effects by injecting interface charges, as previously mentioned, and performing electrical characteristic simulations. Next, based on the simulation results, Silvaco’s Utmost simulator was utilized to extract model parameters, such as those for Bsim3 and Bsim4, by configuring device characteristics. The extracted parameters were inserted into the SPICE device symbol to design the n-MOSFET SPICE model, which was then used to construct the mixed-stage IC model. Finally, an IC simulation was conducted using the SmartSpice tool to analyze radiation effects based on the TCAD-extracted parameters for each device. This mixed-stage M&S process is illustrated in Figure 5, and

Table 2. SPICE model parameters extracted from TCAD for IC TID effects simulation.

SPICE Model Extracted from TCAD
Parameter	Description	TID Effects
VTH0	Initial threshold voltage	Increases
U0	Low-field mobility	Decreases
ETA0	Drain-Induced Barrier Lowering (DIBL) coefficient	Increases
NFS	Fixed oxide charge density	Increases
XJ	Junction depth	Increases
WD	Depletion width	Increases
IS	Saturation current	Increases

shows the SPICE model parameters extracted from TCAD that are particularly sensitive to TID effects.

Figure 6 illustrates the mixed-stage models of the Op-Amp and D-latch based on the extracted parameters. These models allow the simulation of radiation effects at both the device and circuit levels, providing a comprehensive framework to evaluate the cumulative impact of radiation on ASIC performance.

Using the symbols of two models (ST and RT), mixed-stage models of the D-latch and Op-Amp were designed prior to radiation damage. Functional simulations were conducted for each Mixed-stage IC model to verify its performance and ensure operational reliability. The D-latch IC successfully demonstrates data storage functionality according to the clock (CLK) state. For the Op-Amp IC, the slew rate and DC gain were 1.54 V/μs and 92.4 dB for the ST-based IC and 1.47 V/μs and 92 dB for the RT-based IC.

To evaluate radiation-induced damage and tolerance, mixed-stage IC models were designed using the symbols for the radiation-injected models (ST + RI and RT + RI). The ST + RI model differed in the SPICE model parameters compared with the ST model, including the threshold voltage, channel length modulation parameter, and exponent for the substrate current-induced body effect. Conversely, the RT + RI model effectively suppressed the radiation effects, maintaining parameter values nearly identical to those of the RT model.

The charge due to an accumulated radiation dose of approximately 12 kGy(Si) was incorporated into each SPICE model parameter. This allows the mixed-stage IC radiation injection models to simulate the radiation-induced damage propagation or compounding within the circuit. To assess radiation tolerance, simulations were conducted on mixed-stage models of the Op-Amp and D-latch ICs with ST + RI and RT + RI devices. These simulations analyzed the characteristics of the circuits as radiation injection increased.

Figure 7a,b illustrate the gain variation simulation results of the Op-Amps with the ST + RI and RT + RI models as the radiation injection increased. Figure 7c,d show the corresponding slew rate changes. The ST + RI Op-Amp group showed a reduction in gain with increasing radiation dose. When subjected to an accumulated dose of 12 kGy(Si), the gain dropped from 92.40 dB to 61.55 dB, indicating a loss of over 30 dB. This degradation affected the slew rate of the driver buffer, decreasing it from 1.54 V/μs to 1.28 V/μs, thereby reducing performance.

In contrast, RT + RT + RI Op-Amp maintained its performance under radiation exposure. After injecting an accumulated dose of 12 kGy(Si), the gain slightly decreased from 92 dB to 90.17 dB, indicating negligible degradation. Similarly, the slew rate of the driver buffer built with the RT + RI Op-Amp remained stable at around 1.47 V/μs, demonstrating its radiation tolerance in advance.

Figure 8 presents the results of the D-latch mixed-stage models (ST + RI and RT + RI) under increasing radiation injection, showing their functional behavior and data integrity. The ST + RI D-latch operated correctly at a clock frequency of 30 kHz before radiation exposure, providing reliable data storage. However, as the cumulative dose increased to 12 kGy(Si), errors accumulated, leading to malfunctioning.

In contrast, the RT + RI D-latch maintained stable operation at 30 kHz before and after radiation injection. It successfully preserved its data-storage function under radiation exposure of up to 12 kGy(Si), demonstrating its radiation tolerance.

These results confirm that as the complexity and integration density of electronic circuit chips increase, the proposed mixed-stage M&S efficiently evaluates IC radiation tolerance.

3.2. Radiation-Tolerant CMOS ASIC Design and Fabrication

To fabricate and verify the radiation tolerance of the mixed-stage IC models for damage and resistance, full-custom IC designs were implemented based on a 0.18 µm CMOS STI bulk process [15,16]. Radiation-tolerant ICs comprise dozens to hundreds of transistors with varying channel sizes. The RT n-MOS with LMT maintained the original n-active region of the transistors while extending the polysilicon layer vertically to the original gate region, completely separating the n+ and p+ layers. This ensured that no channel changed before and after LMT application.

In contrast, conventional radiation-tolerant transistor structures experience channel changes after LMT application, requiring additional remodeling and challenging the standard IC design processes, such as design rule check, layout versus schematic (LVS), and layout parasitic extraction (LPE). In these cases, manual screening is insufficient for ensuring chip functionality.

The proposed RT n-MOS avoids these issues because of its channel-retention properties, allowing for a simpler IC design, which facilitates layout verification (LVS and LPE) and debugging through post-layout simulations to ensure the reliability of the chip operation.

Radiation-tolerant D-latch and two-stage Op-Amp ICs were designed by applying the radiation-tolerant LMT at the layout design stage. The RT n-MOS structures were adjusted according to the circuit signal connections and the positions of each node, completing the optimized IC layout design. Figure 9 shows the layout process diagrams of radiation-tolerant ICs.

Post-layout simulations were performed on the radiation-tolerant D-latch and Op-Amp following LPE. The results confirmed that the D-latch with radiation-tolerant LMT maintained normal data storage functionality in response to the CLK. The RT Op-Amp exhibited a DC gain of 91.87 dB, a phase margin of 60.57°, and a slew rate of 1.47 V/µs. These results were nearly identical to those of the pre- and post-layout simulations without applying the LMT. Therefore, the proposed radiation-tolerant IC design technique reliably verifies radiation tolerance from mixed-stage M&S to post-layout simulations prior to chip fabrication.

A test chip was fabricated for tolerance evaluation. This test chip included standard and radiation-tolerant ICs and was packaged in a single 100-pin dual-flat no-lead package, as shown in Figure 9. The electrical and functional test results of the fabricated RT-IC chip confirmed that the D-latch circuit operated normally under a 3.3 V voltage and 30 kHz CLK. In the radiation test, changes in the maximum operating frequency were set as the characteristic parameters for radiation tolerance evaluation. For the Op-Amp circuit, the change in the slew rate due to increasing radiation dose was selected as the characteristic parameter. Before radiation exposure, the slew rate under a 2 V unit step function input was measured at 1.47 V/µs. The change in the Op-Amp slew rate occurs due to variations in the DC gain, allowing for indirect measurement of changes in DC gain.

4. Experimental Validation of Radiation-Tolerant ICs

4.1. TID Testing of Proposed Radiation-Tolerant ASIC Chips

The TID testing of standard and radiation-tolerant IC chips fabricated through semiconductor processes was conducted at the Advanced Radiation Research Institute in Jeongeup. The testing utilized a high-level gamma-ray irradiation facility equipped with a Cobalt-60 source to measure the changes in the characteristic parameters of the ICs with increasing accumulated radiation dose [17].

To evaluate the high-level radiation tolerance of semiconductor ICs, TID test procedures and evaluation methods were established based on MIL-STD-883H 1019.8 and ESA/SCC Basic Specification No. 22900 [18,19]. The procedure verified the normal operation of the test chip samples before irradiation, setting the dose rate and accumulated dose by adjusting the distance between the DUT board and the radiation source and installing dosimetry at the exact location of the DUT board to measure the accumulated dose.

During irradiation, the test chips were biased to remain operational, and the characteristic parameter changes and key functional characteristics were monitored in real-time as the accumulated dose increased, with data collected accordingly. The TID test environment at the gamma-ray irradiation facility was set up, as shown in Figure 10. A DUT board containing the test chips was installed inside the irradiation chamber, and a 25 m cable connected the chamber to the control room to facilitate the power supply, input application, parameter monitoring, and data acquisition.

To verify the functionality and electrical characteristics of the standard and radiation-tolerant IC test chips under increasing accumulated radiation doses in real-time, appropriate measurement methods and conditions (biases) for each IC were established, as shown in

Table 3. Measurement methods and conditions for the radiation effect parameters of ICs.

Measurement Conditions
Irradiation conditions	Total dose [kGy(Si)]	20
	Dose rate [kGy/h]	5
RT-IC type (1)		Driver buffer with RT Op-Amp
Bias conditions	Supply voltage [V]	3.3
	Input	Unit step function/0~2 V
Term of elec. parameter		Slew rate [V/us]
RT-IC type (2)		RT D-latch
Bias conditions	Supply voltage [V]	3.3
	Input (D)	pulse/100 Hz/3.3 V
	Clock (CLK)	pulse/25~30 kHz/3.3 V
Term of elec. parameter		VOUT (Data error) and Operation Freq. [kHz]

. The accumulated radiation dose was tested at a maximum dose of 20 kGy(Si).

For the ST and RT two-stage single-ended Op-Amp ICs, a buffer circuit was configured to enable real-time slew rate (SR) measurements, which recorded the maximum rate of change in the output voltage per microsecond (µs). Standard and radiation-tolerant D-latch digital ICs were tested by applying a 3.3 V supply voltage along with CLK and input (D) signals from a function generator. The clock frequency was adjusted to measure the output peak voltage and maximum operating frequency changes.

Accumulated radiation tests were conducted according to an established test procedure. The buffer comprised the standard Op-Amp IC experienced a decrease in slew rate from 1.55 V/µs to 1.22 V/µs after exposure to a total accumulated dose of 20 kGy(Si), as shown in Figure 11, resulting in delayed output stabilization. In contrast, the RT Op-Amp IC buffer maintained an SR of approximately 1.46 V/µs after radiation exposure, confirming no change in the full bandwidth characteristics directly related to SR. Ultimately, the DC gain of Op-Amp was preserved, validating the radiation tolerance up to an accumulated dose of approximately 20 kGy(Si).

Figure 12 shows that the standard D-latch IC exhibits increased data errors and malfunctions at a clock frequency of 30 kHz after exposure to a total accumulated dose of approximately 20 kGy(Si). This behavior, caused by the TID effects, can result in abnormal states during high-frequency operations and impose clock speed limitations in nuclear or space environments. In contrast, the RT D-latch IC demonstrated no change in the peak voltage or maximum operating frequency as the radiation dose increased. It maintains normal functionality even at a total accumulated dose of approximately 20 kGy(Si), thereby validating its radiation tolerance.

4.2. Radiation Test Results and Analysis

Based on real-time data obtained through radiation testing of standard and radiation-tolerant digital/analog ICs, changes in the characteristic parameters before and after total accumulated dose irradiation were analyzed, as shown in Figure 13 and summarized in

Table 4. Summary of radiation tolerance and damage characteristics for ST and RT ICs.

TID Test Evaluation Results
Driver buffer with Op-Amp
Parameter	Irradiation	Standard	Rad-Tolerance
SR [V/μs]	Before	1.55	1.46
	After (20 kGy)	1.22	1.455
	Damage [%]	21.3	0.001
D-latch
Parameter	Irradiation	Standard	Rad-Tolerance
Max. operation Freq. [kHz]	Before	30	30
	After (2 kGy)	25.5	30
	Damage [%]	15	0
Data error (30 kHz) [#]	Before	0	0
	After (10 kGy)	4	0
	After (20 kGy)	Malfunction	Normal
	Damage [%]	100%	0

.

The standard D-latch IC comprises four NAND gates, each with eight nMOS and pMOS transistors. Figure 14a shows that nMOS transistors are vulnerable to radiation, causing a leakage current owing to the accumulated radiation dose. This leakage current increase can pose a risk of the NAND logic output entering an unknown state where High and Low cannot be distinguished.

The effect of radiation-induced leakage current was more pronounced when the nMOSs in the NAND gate were off. Consequently, the leakage current caused by radiation in the NAND gates affects the output signal of the D-latch IC in all logical states during operation. This signal was passed to the next stage, gradually reducing the operational speed and affecting the overall functioning of the circuit.

The SR of the two-stage Op-Amp analog IC is determined by the compensation capacitor (C_C) at the final output stage and the current (∆I) flowing through it. This relationship is expressed as SR = ∆I/C_C. Figure 14b shows that the radiation-induced leakage current from the nMOS transistors in the final output stage decreases ∆I, reducing the operation speed and bandwidth characteristics of the Op-Amp and degrading IC performance. For the standard Op-Amp IC, the change in SR with increasing accumulated dose showed a sharp decrease up to a total dose of 12 kGy, followed by a more gradual decline as the dose increased to 20 kGy. This behavior is due to the TID effect, where the leakage current of the nMOS transistors increases and then saturates. Such a leakage current deteriorates the Op-Amp’s gain characteristics and propagates damage by reducing the driver buffer SR, affecting the overall IC performance.

Here, the radiation-induced damage mechanism of ICs was analyzed. Instead of simply compensating for the radiation-induced leakage current through margin design, a radiation-hardened leakage-mitigating technology was applied at the transistor level to directly block the cause. Thus, radiation resilience was extended to the IC level, and RT ICs were evaluated through M&S, design, fabrication, and testing. The results listed in Table 4 indicate that the standard D-latch experiences a decrease in operating frequency of approximately 15% with an increasing cumulative dose up to 20 kGy(Si), and the standard Op-Amp shows a decrease in SR of approximately 21%. In contrast, the radiation-hardened ICs demonstrated no performance degradation before or after radiation exposure, confirming their radiation resistance of up to 20 kGy(Si). The characteristics of conventional transistors with the LMT mentioned in the introduction were compared with those of the RT-nMOS in this study, as summarized in

Table 5. Comparison of radiation-tolerant n-MOSFETs with layout modification technique.

Comparison Criteria	Radiation-Tolerant n-MOSFETs with LMT
	ELT [8]	DGA [9]	H-gate [10]	This Work
Radiation tolerance [kGy(Si)]	300	5	1.2	20
Source-drain symmetry	No	Yes	Yes	Yes
W/L ratio limitation	Yes	No	No	No
Channel size variation	Yes	Yes	Yes	No
Multi-finger implementation	No	Yes	Yes	Yes
Req. for additional process	No	Yes	No	No
Applicability to ICs	Low	Moderate	Moderate	High

. It can be concluded that the RT-nMOS is the most efficient structure for radiation-tolerant IC design.

The damage and radiation tolerance results obtained from radiation testing were compared and analyzed using M&S predictions. Figure 15 shows that the simulation results after radiation damage injection in the mixed-stage model for the Op-Amp and D-latch IC agree well with the experimental results for the standard and radiation-tolerant ICs, with a maximum error of less than 4%. This demonstrates that the mixed-stage M&S technology is a reliable tool for pre-radiation tolerance evaluation to develop radiation-hardened electronic circuit ICs.

5. Conclusions

This study addressed the repetitive fabrication and testing inefficiency while developing radiation-resistant semiconductor IC chips. Using semiconductor radiation damage M&S, transistor tolerance structures were derived. Based on the results of mixed-stage M&S predictions, radiation tolerance was expanded to the IC level to design and fabricate radiation-tolerant ASIC chips. Furthermore, the radiation test results verified the reliability of the radiation-tolerant IC design technology up to a total accumulated dose of 20 kGy(Si). The results can be expanded beyond the device level to the circuit, module, and system levels and are expected to be applied to develop electronic systems that require high reliability in various radiation environments, such as space, defense, and nuclear power.