Chips, Volume 4, Issue 2 (June 2025) – 6 articles

This paper presents the design and implementation of a linear, stable, low-power and PVT insensitive floating active resistor, which is realized using TSMC 40 nm CMOS process technology. By incorporating the automatic tuning circuit, this work has achieved improved performance metrics, which include low process sensitivity, reduced temperature coefficient, and good linearity. Monte Carlo (MC) simulations are conducted to evaluate the active resistor’s performance under variations in temperature, process, and supply voltage. The proposed design has demonstrated an average resistance process sensitivity of 0.64%, a temperature coefficient (T.C.) of 57 ppm/°C across −25 °C to 85 °C, and a linearity figure of merit (FOM) of 2.4 × 10⁻² V⁻¹ with a resistance close to MΩ level. It can achieve a linear resistance tuning range of 430.5 kΩ to 1.714 MΩ. The typical power consumption of a single active resistor is 0.25 µW at 2.1 V bootstrapped supply voltage through a Dickson charge pump (DCP) circuit using a DC input of 1 V. These results have confirmed that the proposed active resistor can function as a robust and efficient resistor for low-voltage integrated circuits and systems. Full article

The TDM Test Scheduler and TAM Optimization Toolkit is a novel, integrated, and user-friendly solution designed for engineers, researchers, and instructors working in the field of manufacturing tests. It effectively supports test planning for multicore, DVFS-based SoCs with multiple voltage islands, offering optimized solutions that minimize test costs while ensuring compliance with power and thermal constraints. The toolkit provides (a) a high-level language (HLL) for the intuitive representation of test processes, along with a smart syntax and logic checker for verification; (b) an advanced compilation and execution environment featuring two computationally efficient Time-Division Multiplexing (TDM)-specialized solvers; (c) a sophisticated Test Access Mechanism (TAM) optimization framework; (d) a customized visualization environment capable of depicting and animating power- and thermal-annotated test schedules; (e) a versatile testbed for educational and research activities. Full article

This work presents a cost-effective optical frequency comb generator (CEOFCG) solution for generating multiple, equally spaced carriers in wavelength-division-multiplexing coherent optical fiber communication systems (WDM-COFCS). It enables the replacement of multiple laser sources with a single continuous-wave laser, eliminating the need for additional amplification and filtering setups. The CEOFCG provides stable multicarrier spacing, broad phase coherence, and compatibility with advanced modulation formats, enhancing the performance of WDM-COFCS. Digital signal processing (DSP) techniques, including digital filtering, detection, and impairment compensation, contribute to high transmission and spectral efficiency (SE). The results demonstrate the potential of CEOFCG in achieving cost reduction, complexity reduction, high SE, and optimal utilization of optical fiber bandwidth, particularly in higher-order QAM-based COFCS. Full article

The rapid growth of the Internet of Things (IoT) has significantly expanded the deployment of resource-constrained devices, introducing new security and privacy challenges. To address these concerns, the National Institute of Standards and Technology (NIST) concluded a multi-year effort by announcing ASCON as the new lightweight cryptography standard in 2023. ASCON’s cipher suite includes both Authenticated Encryption with Associated Data (AEAD) and hashing functions, ensuring authenticity, confidentiality, and broad applicability. Since its standardization, there has been a significant research effort focused on enhancing ASCON’s performance under diverse application constraints as well as assessing its vulnerability to advanced side-channel attacks. This study offers a comprehensive overview of current ASCON hardware implementations on FPGA and ASIC platforms, examining key design trade-offs. Additionally, it examines the latest side-channel attacks on ASCON were examined. These attacks exploited weaknesses in the hardware implementations rather than in the algorithm itself. Being highly efficient, they could breach both unprotected and protected implementations. This survey also reviews the proposed countermeasures against these powerful attacks and analyzes how their associated overhead conflicts with the performance demands of real-world ASCON applications. The synthesis of these findings offers clear guidelines for designers seeking to implement ASCON. At the same time, areas requiring further investigation are identified. As ASCON sees ever more widespread deployment, this review serves as a reference for understanding the current state of research and guiding future developments toward efficient and secure implementations. Full article

This paper proposes novel two fault-tolerant routing methods for a 3D mesh network-on-chip (NoC). The existing method proposed by Boppana et al. combines two routing methods, minimal fully adaptive routing and fault-tolerant routing, for faulty region detouring. However, in the latter fault-tolerant routing, a detour direction is statically defined for each faulty region. Due to the long detour path and the use of eight virtual channels, this method has the problems of high communication latency and a large hardware overhead. To solve these problems, the first proposed method allows adaptive detours for faulty regions, and the second proposed method allows the passage of them. The simulation results show that, compared with the existing method, the second proposed method enables us to reduce the latency by about 30% and improve the throughput by about 3.1% with half of the virtual channels. Full article

With the increasing demand for efficient deep learning models in resource-constrained environments, Binary Neural Networks (BNNs) have emerged as a promising solution due to their ability to significantly reduce computational complexity while maintaining accuracy. Their integration into embedded and edge computing systems is essential for enabling real-time AI applications in areas such as autonomous systems, industrial automation, and intelligent security. Deploying BNN on FPGA using RISC-V, rather than directly deploying the model on FPGA, sacrifices detection speed but, in general, reduces power consumption and on-chip resource usage. The AI-extended RISC-V core is capable of handling tasks beyond BNN inference, providing greater flexibility. This work utilises the lightweight Zero-Riscy core to deploy a BNN on FPGA. Three custom instructions are proposed for convolution, pooling, and fully connected layers, integrating XNOR, POPCOUNT, and threshold operations. This reduces the number of instructions required per task, thereby decreasing the frequency of interactions between Zero-Riscy and the instruction memory. The proposed solution is evaluated on two case studies: MNIST dataset classification and an intrusion detection system (IDS) for in-vehicle networks. The results show that for MNIST inference, the hardware resources required are only 9% of those used by state-of-the-art solutions, though with a slight reduction in speed. For IDS-based inference, power consumption is reduced to just 13% of the original, while resource usage is only 20% of the original. Although some speed is sacrificed, the system still meets real-time monitoring requirements. Full article