Recent Advances in Microelectronics Fabrication and Packaging

Dear Colleagues,

With the growing demand in data processing for emerging applications in Artificial Intelligence (AI), High-Performance Computing (HPC), and Edge Computing (EC), the computational requirements in terms of Tera-Operations Per Second (TOPS) per unit area have grown exponentially. The added requirements of a reduced carbon footprint and environmental sustainability further place demands on the energy per bit and computational efficiency. Moore’s law of scaling, which has pushed transistor dimensions down by a factor of 0.7 every 18 months, has also become saturated due to the fundamental quantum and thermodynamic limitations of sub-nm channel lengths.

In modern electronic systems, the system performance in terms of TOPS and energy per bit is often dominated by the interconnect parasitic, particularly at the board level. While transistors have scaled down through sophisticated innovations in microelectronic processing, especially lithography, innovations of the electronic package that connects chips together have remained quite stagnant for the past 2–3 decades. Packages often have very coarse wiring pitches in the hundreds of microns, while the pad pitches on a modern Si chip approach sub 10 microns. This discrepancy is currently addressed through (1) the use of bulky space transformers, such as intermediate laminate layers that increase interconnect lengths and, hence, latency, and (2) data serialization through the use of energy and space-hungry SerDes (on chip) to account for the reduced number of connections at the board level. These limitations in conventional electronic packages have pushed up the energy per bit and reduced the achievable TOPS/unit area of the system. Hence, there is a need to give an overall ‘face-lift’ to current packaging technologies and move into the realm of advanced packaging based on microelectronic-like processing to enable fine wiring pitches of sub 10 microns at the board level.

New innovations are needed both in the electronic transistor space and in advanced packaging. In the transistor space, novel devices based on silicon technology, such as the Gate-All-Around (GAA) transistor, Nanowire transistors, etc., are currently being developed and manufactured by industry professionals. Non-silicon materials, such as III-V, 2D materials, etc., are also to be explored for next-generation transistors. These new transistors require vastly different microelectronic processing steps of lithography, etching, and deposition, which remain to be developed. In the advanced packaging space, newer packaging technologies such as Fan-Out Wafer-Level Packaging (FOWLP) and Wafer-scale die-let assembly though TCB/Hybrid bonding are currently being explored and commercialized. The combination of novel transistor manufacturing with advanced packaging will enable continued Moore’s law scaling of computational performance for future applications. 

Considering this, this Special Issue aims to focus on recent advances in both microelectronic fabrication for next-generation transistors and their interconnects as well as advanced packaging. We are pleased to invite you to submit original research articles and reviews. Research areas may include (but not limited to) the following:

1. Innovations in sub-nm lithography;
2. Innovations in etching technologies (wet and dry);
3. Dielectric and metal deposition technologies;
4. Electroplating and CMP;
5. Process yield monitoring, as well as testing and verification of KGD;
6. Advanced packaging such as FOWLP and Wafer-scale assembly;
7. TCB and hybrid bonding.

Dr. Goutham Ezhilarasu
Prof. Dr. Subramanian S. Iyer
Guest Editors

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• advanced packaging
• microfabrication
• nanomanufacturing