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Advanced Memory Devices
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Advanced Memory Devices

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Optics and Lasers".

Deadline for manuscript submissions: closed (20 August 2020) | Viewed by 12575

Special Issue Editor

Dr. Jer-Chyi Wang

E-Mail Website
Guest Editor
Department of Electronic Engineering, Chang Gung University, Taoyuan, Taiwan
Interests: the characteristics and reliability of MOSFETs; metal-gate/high-k technology; advanced memory device fabrication; 3D process and device simulation; biosensor device fabrication and its applications

Special Issue Information

Dear Colleagues,

I would like to cordially invite you to contribute a paper to a Special Issue of the open access journal Applied Sciences, entitled “Advanced Memory Devices”, which aims to present recent developments of advanced memories with volatile and nonvolatile behaviors for applications in high-speed and low-power operation, high-density storage, biomedicine, Internet of Things (IoT), neural networks, artificial intelligence (AI), and so on.

This Special Issue contains volatile memories (DRAM and SRAM) and nonvolatile memories (flash, RRAM, MRAM, PCM, FeRAM, etc.) with novel device strucutres, materials, and design for some specific applications. I invite you to submit your research on these topics, in the form of original research papers and articles.

Dr. Jer-Chyi Wang
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • volatile
  • nonvolatile
  • high-speed
  • low-power
  • high-density storage
  • biomedicine
  • Internet of Things (IoT)
  • neural network
  • artificial intelligence (AI)

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Published Papers (3 papers)

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Research

13 pages, 4872 KiB  
Article
Multilevel Bipolar Electroforming-Free Resistive Switching Memory Based on Silicon Oxynitride
by Nayan C. Das, Se-I Oh, Jarnardhanan R. Rani, Sung-Min Hong and Jae-Hyung Jang
Appl. Sci. 2020, 10(10), 3506; https://doi.org/10.3390/app10103506 - 19 May 2020
Cited by 17 | Viewed by 3457
Abstract
Resistive random-access memory (RRAM) devices are fabricated by utilizing silicon oxynitride (SiOxNy) thin film as a resistive switching layer. A SiOxNy layer is deposited on a p+-Si substrate and capped with a top electrode consisting of [...] Read more.
Resistive random-access memory (RRAM) devices are fabricated by utilizing silicon oxynitride (SiOxNy) thin film as a resistive switching layer. A SiOxNy layer is deposited on a p+-Si substrate and capped with a top electrode consisting of Au/Ni. The SiOxNy-based memory device demonstrates bipolar multilevel operation. It can switch interchangeably between all resistance states, including direct SET switching from a high-resistance state (HRS) to an intermediate-resistance state (IRS) or low-resistance state (LRS), direct RESET switching process from LRS to IRS or HRS, and SET/RESET switching from IRS to LRS or HRS by controlling the magnitude of the applied write voltage signal. The device also shows electroforming-free ternary nonvolatile resistive switching characteristics having RHRS/RIRS > 10, RIRS/RLRS > 5, RHRS/RLRS > 103, and retention over 1.8 × 104 s. The resistive switching mechanism in the devices is found to be combinatory processes of hopping conduction by charge trapping/detrapping in the bulk SiOxNy layer and filamentary switching mode at the interface between the SiOxNy and Ni layers. Full article
(This article belongs to the Special Issue Advanced Memory Devices)
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18 pages, 2335 KiB  
Article
Implications of NVM Based Storage on Memory Subsystem Management
by Hyokyung Bahn and Kyungwoon Cho
Appl. Sci. 2020, 10(3), 999; https://doi.org/10.3390/app10030999 - 3 Feb 2020
Cited by 6 | Viewed by 4244
Abstract
Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited. In this article, we explore the memory subsystems that use NVM [...] Read more.
Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited. In this article, we explore the memory subsystems that use NVM as an underlying storage device and discuss the challenges and implications of such systems. As storage performance becomes close to DRAM performance, existing memory configurations and I/O (input/output) mechanisms should be reassessed. This article explores the performance of systems with NVM based storage emulated by the RAMDisk under various configurations. Through our measurement study, we make the following findings. (1) We can decrease the main memory size without performance penalties when NVM storage is adopted instead of HDD. (2) For buffer caching to be effective, judicious management techniques like admission control are necessary. (3) Prefetching is not effective in NVM storage. (4) The effect of synchronous I/O and direct I/O in NVM storage is less significant than that in HDD storage. (5) Performance degradation due to the contention of multi-threads is less severe in NVM based storage than in HDD. Based on these observations, we discuss a new PC configuration consisting of small memory and fast storage in comparison with a traditional PC consisting of large memory and slow storage. We show that this new memory-storage configuration can be an alternative solution for ever-growing memory demands and the limited density of DRAM memory. We anticipate that our results will provide directions in system software development in the presence of ever-faster storage devices. Full article
(This article belongs to the Special Issue Advanced Memory Devices)
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26 pages, 6104 KiB  
Article
A Novel B-Tree Index with Cascade Memory Nodes for Improving Sequential Write Performance on Flash Storage Devices
by Bo-Kyeong Kim, Gun-Woo Kim and Dong-Ho Lee
Appl. Sci. 2020, 10(3), 747; https://doi.org/10.3390/app10030747 - 21 Jan 2020
Cited by 1 | Viewed by 4423
Abstract
Flash storage devices such as solid-state drives and multimedia cards have been widely used in various applications because of their fast access speed, low power consumption, and high reliability. They consist of NAND flash memories that perform slow block erasures before overwriting data [...] Read more.
Flash storage devices such as solid-state drives and multimedia cards have been widely used in various applications because of their fast access speed, low power consumption, and high reliability. They consist of NAND flash memories that perform slow block erasures before overwriting data on a prewritten page. This characteristic can lead to performance degradation when applying the original B-tree on the flash storage device without any changes. Although various B-trees have been proposed for flash memory, they still require many flash operations that degrade overall performance. To address the problem, we propose a novel B-tree index structure that reduces the number of write operations and improves the sequential writes by employing cascade memory nodes. The proposed B-tree index structure delays the updates for the modified B-tree nodes and later performs batch writes in a cascade manner. Also, when records with continuous key values are sequentially inserted, the proposed B-tree index structure does not split the leaf node so that it improves write throughput and page utilization. Through mathematical analysis and experimental results, we show that the proposed B-tree index structure always yields better performance than existing techniques. Full article
(This article belongs to the Special Issue Advanced Memory Devices)
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