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Design of Fault Tolerant Digital Circuits and Systems

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: closed (20 December 2022) | Viewed by 2919

Special Issue Editor


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Guest Editor
Department of Electronic Engineering, Kwangwoon University, Seoul 01897, Korea
Interests: variation aware circuit design; low voltage circuit design; memory yield estimation

Special Issue Information

Dear Colleagues,

With technology scaling down into the nanometer scale, the impact of variations in manufacturing or the environment on digital circuits and system has significantly enlarged. As a result, circuit operation has become uncertain and highly likely to experience malfunctions.

This Special Issue intends to present novel designs that make digital circuits and systems tolerant to faults or errors. Subjects covered in this Special Issue include, but are not limited to, design innovations in devices, circuits, systems, architecture, algorithms or test methodology, able to improve fault tolerance.

Dr. Hanwool Jeong
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (2 papers)

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Editorial

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1 pages, 136 KiB  
Editorial
Special Issue on Design of Fault-Tolerant Digital Circuits and Systems
by Hanwool Jeong
Appl. Sci. 2022, 12(18), 8935; https://doi.org/10.3390/app12188935 - 6 Sep 2022
Viewed by 670
Abstract
As technology scales down, the speed and power efficiency of digital circuits become greatly enhanced [...] Full article
(This article belongs to the Special Issue Design of Fault Tolerant Digital Circuits and Systems)

Review

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14 pages, 1854 KiB  
Review
Design of Static Random-Access Memory Cell for Fault Tolerant Digital System
by Taehwan Yoon, Jihwan Park and Hanwool Jeong
Appl. Sci. 2022, 12(22), 11500; https://doi.org/10.3390/app122211500 - 12 Nov 2022
Cited by 1 | Viewed by 1637
Abstract
This paper comparatively analyzes the static random-access memory (SRAM) cell designs for fault tolerance. Since SRAM cells are sensitive to radiation-induced single event upsets, various circuit-level approaches have been applied. Compared to the conventional SRAM cell circuits, one possibility is adding redundant storage [...] Read more.
This paper comparatively analyzes the static random-access memory (SRAM) cell designs for fault tolerance. Since SRAM cells are sensitive to radiation-induced single event upsets, various circuit-level approaches have been applied. Compared to the conventional SRAM cell circuits, one possibility is adding redundant storage nodes by means of additional transistors. The strength and weakness of the SRAM cells in terms of various performance aspects—speed, area, power, stability, fault tolerance, etc.—according to the design approaches are compared analytically and discussed. The discussion concludes that, in the future, it is paramount to develop an SRAM cell design with a mitigated trade-off between read/write performance and SEU tolerance. Full article
(This article belongs to the Special Issue Design of Fault Tolerant Digital Circuits and Systems)
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