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VLSI Architectures for Signal Processing

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: closed (31 January 2021) | Viewed by 7161

Special Issue Editor


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Guest Editor
Associate Professor, Department of Electronic Engineering, Myongji University, Yongin 17058, Korea
Interests: digital signal processing; VLSI for signal processing algorithms; system-on-chip design; HW-SW co-design; machine learning; digital communication

Special Issue Information

Dear Colleagues,

Recent digital signal processing applications such as artificial intelligence, 5G digital communication, automotive system, cyber security, computer vision, and video analysis require an increasing data rate as well as ultra-low power consumption for an embedded environment. Computation-intensive signal processing algorithms need to be implemented in dedicated VLSI to realize their real-time processing capabilities. Therefore, it is essential to develop VLSI-friendly digital signal processing algorithms and implement them through efficient design methodologies to achieve a balanced trade-off between speed, power consumption, silicon area, cost, and reconfigurability.

The main aim of this Special Issue is to attract recent high-quality research works as well as review articles on the recent progress for “VLSI Architectures for Signal Processing”, including the analysis and architectureal design of digital signal processing algorithms, practical implementations of digital circuits, VLSI design methodologies, and the application of circuit techniques to digital systems. Design optimizations at all the levels of abstraction fall within the field of interest of this Special Issue, e.g., at the algorithm level, at the register-transfer level, and at the circuit level for VLSI implementation of different components of signal processing algorithms.

Prof. Dr. Sang Yoon Park
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • VLSI for digital signal processing
  • VLSI for speech, image, and video processing
  • VLSI for digital communication system
  • VLSI for computer vision
  • VLSI for machine learning
  • VLSI for IoT
  • VLSI for security
  • VLSI for digital circuits and systems
  • VLSI for special purpose signal processing
  • VLSI for system-on-chip
  • VLSI for embedded system
  • VLSI for reconfigurable system

Published Papers (1 paper)

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Research

10 pages, 1745 KiB  
Article
Area-Efficient Short-Time Fourier Transform Processor for Time–Frequency Analysis of Non-Stationary Signals
by Hohyub Jeon, Yongchul Jung, Seongjoo Lee and Yunho Jung
Appl. Sci. 2020, 10(20), 7208; https://doi.org/10.3390/app10207208 - 15 Oct 2020
Cited by 22 | Viewed by 6478
Abstract
In this paper, we propose an area-efficient short-time Fourier transform (STFT) processor that can perform time–frequency analysis of non-stationary signals in real time, which is essential for voice or radar-signal processing systems. STFT processors consist of a windowing module and a fast Fourier [...] Read more.
In this paper, we propose an area-efficient short-time Fourier transform (STFT) processor that can perform time–frequency analysis of non-stationary signals in real time, which is essential for voice or radar-signal processing systems. STFT processors consist of a windowing module and a fast Fourier transform processor. The length of the window function is related to the time–frequency resolution, and the required window length varies depending on the application. In addition, the window function needs to overlap the input data samples to minimize the data loss in the window boundary, and overlap ratios of 25%, 50%, and 75% are generally used. Therefore, the STFT processor should ideally support a variable window length and overlap ratio and be implemented with an efficient hardware architecture for real-time time–frequency analysis. The proposed STFT processor is based on the radix-4 multi-path delay commutator (R4MDC) pipeline architecture and supports a variable length of 16, 64, 256, and 1024 and overlap ratios of 25%, 50%, and 75%. Moreover, the proposed STFT processor can be implemented with very low complexity by having a relatively lower number of delay elements, which are the ones that increase complexity in the most STFT processors. The proposed STFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using a standard cell library in a 65 nm CMOS process. The proposed STFT processor results in logic gates of 197,970, which is 63% less than that of the conventional radix-2 single-path delay feedback (R2SDF) based STFT processor. Full article
(This article belongs to the Special Issue VLSI Architectures for Signal Processing)
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