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Electronics
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New CMOS Devices and Their Applications II
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New CMOS Devices and Their Applications II

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: closed (31 December 2021) | Viewed by 19419

Special Issue Editor

Prof. Dr. Myounggon Kang

E-Mail Website
Guest Editor
Department of Electronics Engineering, Korea National University of Transportation, Chungju 27469, Korea
Interests: advanced CMOS devices; volatile/nonvolatile memory devices; device modeling and simulation; circuit design; reliability analysis (HCI/BTI/radiation)
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The next decade promises to be full of challenges and opportunities for next-generation CMOS devices. The surge of Big Data, Internet of Things, Artificial Intelligence, and 5G mobile networks will not only require an unprecedented amount of storage capacity, but also demand CMOS technologies be capable of fulfilling quite a variety of requirements related to cost, performance, and reliability. To take full advantage of the new market needs and keep their leading role in the semiconductor device area, the sub-10-nm multi-gate MOSFET, 3D stacked NAND Flash Memory, DRAM, and Emerging memory technologies will have to keep evolving, exploiting new integration schemes, new materials, and new working conditions able to prolong their historical scaling trends.  This Special Issue of Electronics aims at presenting an in-depth discussion of the new CMOS devices and technologies that will have an impact on the electronics world in the next decade. Papers are solicited on next-generation CMOS devices, 3D NAND Flash Memory, neuromorphic devices, and any other technology able to take up the challenges of the next ten years. Topics of interest include, but are not limited to: 

  • Sub-10-nm multi-gate MOSFET (FinFET, nanowire, nanoplate, etc.);
  • Next-generation CMOS devices (tunnel FETs, negative capacitance FETs, etc.);
  • Characterization of 3D stacked NAND Flash Memory and DRAM;
  • Emerging memories and neuromorphic devices;
  • Applications of new CMOS devices;
  • Design, modeling, simulation, and reliability of new devices/circuits;
  • Devices and circuits for high-frequency applications.

Dr. Myounggon Kang
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Sub-10-nm multi-gate MOSFET (FinFET, nanowire, nanoplate, etc.)
  • Next-generation CMOS devices (tunnel FETs, negative capacitance FETs, etc.)
  • Characterization of 3D stacked NAND Flash Memory and DRAM
  • Emerging memories and neuromorphic devices
  • Applications of new CMOS devices
  • Design, modeling, simulation, and reliability of new devices/circuits
  • Devices and circuits for high-frequency applications.

Published Papers (7 papers)

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Research

11 pages, 4452 KiB  
Article
Bidirectional Electric-Induced Conductance Based on GeTe/Sb2Te3 Interfacial Phase Change Memory for Neuro-Inspired Computing
by Shin-young Kang, Soo-min Jin, Ju-young Lee, Dae-seong Woo, Tae-hun Shim, In-ho Nam, Jea-gun Park, Yuji Sutou and Yun-heub Song
Electronics 2021, 10(21), 2692; https://doi.org/10.3390/electronics10212692 - 4 Nov 2021
Cited by 3 | Viewed by 1876
Abstract
Corresponding to the principles of biological synapses, an essential prerequisite for hardware neural networks using electronics devices is the continuous regulation of conductance. We implemented artificial synaptic characteristics in a (GeTe/Sb2Te3)16 iPCM with a superlattice structure under optimized [...] Read more.
Corresponding to the principles of biological synapses, an essential prerequisite for hardware neural networks using electronics devices is the continuous regulation of conductance. We implemented artificial synaptic characteristics in a (GeTe/Sb2Te3)16 iPCM with a superlattice structure under optimized identical pulse trains. By atomically controlling the Ge switch in the phase transition that appears in the GeTe/Sb2Te3 superlattice structure, multiple conductance states were implemented by applying the appropriate electrical pulses. Furthermore, we found that the bidirectional switching behavior of a (GeTe/Sb2Te3)16 iPCM can achieve a desired resistance level by using the pulse width. Therefore, we fabricated a Ge2Sb2Te5 PCM and designed a pulse scheme, which was based on the phase transition mechanism, to compare to the (GeTe/Sb2Te3)16 iPCM. We also designed an identical pulse scheme that implements both linear and symmetrical LTP and LTD, based on the iPCM mechanism. As a result, the (GeTe/Sb2Te3)16 iPCM showed relatively excellent synaptic characteristics by implementing a gradual conductance modulation, a nonlinearity value of 0.32, and 40 LTP/LTD conductance states by using identical pulse trains. Our results demonstrate the general applicability of the artificial synaptic device for potential use in neuro-inspired computing and next-generation, non-volatile memory. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications II)
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10 pages, 2965 KiB  
Article
A Broadband Gain Amplifier Designed with the Models for Package and Diode Using 0.5 μm GaAs E-pHEMT Process
by Min-Su Kim and Heesauk Jhon
Electronics 2021, 10(21), 2678; https://doi.org/10.3390/electronics10212678 - 1 Nov 2021
Cited by 1 | Viewed by 1814
Abstract
This paper presents a 50 MHz to 5 GHz broadband gain amplifier using a 0.5 μm gallium-arsenide pseudomorphic high-electron-mobility-transistor (GaAs pHEMT). For broadband design, a high gain cascode structure with a feedback network was used. To ensure the robustness of the design, the [...] Read more.
This paper presents a 50 MHz to 5 GHz broadband gain amplifier using a 0.5 μm gallium-arsenide pseudomorphic high-electron-mobility-transistor (GaAs pHEMT). For broadband design, a high gain cascode structure with a feedback network was used. To ensure the robustness of the design, the amplifier had to consider the effects of the Electrostatic Discharge (ESD)-protected diode and the package, which can degrade the broadband performance. Therefore, the equivalent circuit models of the package and the ESD-protected diode were analyzed and simulated in this paper. The designed broadband gain amplifier from 50 MHz to 5 GHz frequency band has a die size of 700 μm × 1000 μm and consumes 156 mW of dc power, and it was simulated with a gain of 18.7 dB to 20.6 dB, a P1dB of 15.3 to 16.9 dBm, and a OIP3 of 26.5 to 31 dBm. Furthermore, the excellent gain flatness exhibited within 18.7 dB ± 1.92 dB at the interest of the frequency band. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications II)
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14 pages, 3725 KiB  
Article
A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs
by Jia-He Zhu, Da-Wei Wang, Wen-Sheng Zhao, Jia-Yun Dai and Gaofeng Wang
Electronics 2021, 10(18), 2241; https://doi.org/10.3390/electronics10182241 - 12 Sep 2021
Cited by 2 | Viewed by 2715
Abstract
In this paper, an innovative vertical MOSFET based on through-oxide via (TOV) technology is proposed for silicon-on-insulator (SOI)-based monolithic 3-D ICs. The proposed vertical MOSFET is investigated numerically. It was found that SOI can effectively reduce the parasitic capacitance, leakage current, power consumption, [...] Read more.
In this paper, an innovative vertical MOSFET based on through-oxide via (TOV) technology is proposed for silicon-on-insulator (SOI)-based monolithic 3-D ICs. The proposed vertical MOSFET is investigated numerically. It was found that SOI can effectively reduce the parasitic capacitance, leakage current, power consumption, as well as suppress the pulse current interference of the substrate. The simulated results indicate that the proposed MOSFET possesses excellent characteristics in saturation current over 1500 μA, sub-threshold swing of 69 mV/dec, and on/off current ratio of 1.28 × 1011. Moreover, as temperature is a critical factor for the performance degradation of semiconductor devices, electrothermal simulations are conducted to predict the influence of the self-heating effect on device characteristics. The results show that device characteristics slightly deteriorate, but can still acceptable in their applications. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications II)
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6 pages, 2255 KiB  
Article
Gate All around with Back Gate NAND Flash Structure for Excellent Reliability Characteristics in Program Operation
by Jae-Min Sim, Bong-Seok Kim, In-Ho Nam and Yun-Heub Song
Electronics 2021, 10(15), 1828; https://doi.org/10.3390/electronics10151828 - 30 Jul 2021
Cited by 1 | Viewed by 3372
Abstract
A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology. We demonstrated the excellent characteristics of the GAAB NAND structure, especially in the self-boosting operation. Channel potential of GAAB shows a gradual slope compared with a conventional [...] Read more.
A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology. We demonstrated the excellent characteristics of the GAAB NAND structure, especially in the self-boosting operation. Channel potential of GAAB shows a gradual slope compared with a conventional GAA NAND structure, which leads to excellent reliability characteristics in program disturbance, pass disturbance and oxide break down issue. As a result, the GAAB structure is expected to be appropriate for a high stacking structure of future memory structure. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications II)
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11 pages, 2792 KiB  
Article
Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure
by Seonjun Choi, Changhwan Choi, Jae Kyeong Jeong, Myounggon Kang and Yun-heub Song
Electronics 2021, 10(13), 1561; https://doi.org/10.3390/electronics10131561 - 28 Jun 2021
Cited by 4 | Viewed by 4024
Abstract
In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation. The proposed FF structure [...] Read more.
In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation. The proposed FF structure can supply holes generated through the Gate-Induced Drain Leakage (GIDL) phenomenon in the upper polysilicon string select line (SSL) channel to the IGZO channel through a P-type filler, and the structure proposed by this operation shows a very fast erase speed of 4 μs. A fast erase speed was achieved because the filler adjacent to the IGZO channel, like IP structures in previous studies, functioned as a path through which electrons emitted from the charge storage layer moved easily, rather than simply supplying holes. This assumption was confirmed by assessing the change in electron density of the channel during the erase operation. Next, we investigated the optimum conditions for leakage current reduction through various condition changes of the lower ground select line (GSL) gate in the proposed structure. We confirmed that the leakage current of the proposed structure can be minimized by changing the number of lower GSL gates, changing the length of the GSL channel, and/or changing the work function of the GSL gate material. We obtained a leakage current of 10−17 A when the GSL channel was 480 nm long with six GSL gates, each with a length of 40 nm. The work function of the gates was 4.96 eV. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications II)
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9 pages, 4180 KiB  
Article
TID Circuit Simulation in Nanowire FETs and Nanosheet FETs
by Jongwon Lee and Myounggon Kang
Electronics 2021, 10(8), 956; https://doi.org/10.3390/electronics10080956 - 16 Apr 2021
Cited by 5 | Viewed by 2521
Abstract
In this study, the effects of the total ionizing dose (TID) on a nanowire (NW) field-effect transistor (FET) and a nanosheet (NS) FET were analyzed. The devices have Gate-all-around (GAA) structure that are less affected by TID effects because GAA structures have better [...] Read more.
In this study, the effects of the total ionizing dose (TID) on a nanowire (NW) field-effect transistor (FET) and a nanosheet (NS) FET were analyzed. The devices have Gate-all-around (GAA) structure that are less affected by TID effects because GAA structures have better gate controllability than previously proposed structures, such as planar MOSFETs and FinFETs. However, even for GAA devices with the same channel cross-sectional area and equivalent oxide thickness, structural differences can exist, which can result in different tolerances of TID effects. To observe the device and circuit operation characteristics of these GAA devices with structural differences, n-type and p-type devices were designed and simulated. The circuit simulation according to TID effects was conducted using Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. The NS-FET generated more VT shift than the NW-FET because the NS-FET had a wider gate oxide area and channel circumference, resulting in more interface hole traps. The abnormal VT shift leads to causing unstable circuit operation and delays. Therefore, it was confirmed that the ability of the NW-FET to tolerate TID effects was better than that of the NS-FET. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications II)
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6 pages, 2598 KiB  
Article
The Analysis of SEU in Nanowire FETs and Nanosheet FETs
by Yunjae Kim and Myounggon Kang
Electronics 2021, 10(7), 863; https://doi.org/10.3390/electronics10070863 - 5 Apr 2021
Cited by 1 | Viewed by 1989
Abstract
The effects of the single-event upset (SEU) generated by radiation on nanowire field-effect transistors (NW-FETs) and nanosheet (NS)-FETs were analyzed according to the incident angle and location of radiation, by using three-dimensional technology computer-aided design tools. The greatest SEU occurred when the particle [...] Read more.
The effects of the single-event upset (SEU) generated by radiation on nanowire field-effect transistors (NW-FETs) and nanosheet (NS)-FETs were analyzed according to the incident angle and location of radiation, by using three-dimensional technology computer-aided design tools. The greatest SEU occurred when the particle was incident at 90°, whereas the least occurred at 15°. SEU was significantly affected when the particle was incident on the drain, as compared to when it was incident on the source. The NS-FETs were robust to SEU, unlike the NW-FETs. This phenomenon can be attributed to the difference in the area exposed to radiation, even if the channel widths of these devices were identical. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications II)
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