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System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design
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System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 January 2025 | Viewed by 4547

Special Issue Editor

Prof. Dr. Nicola Lusardi

E-Mail Website
Guest Editor
Department of Electronics, Information and Bioengineering, Politecnico di Milano, 20133 Milano, Italy
Interests: digital electronic; time-to-digital converter; digital-to-time converter; field programmable gate array; system-on-chip
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The evolution of digital technology is firmly steered by key concepts such as field-programmable gate arrays (FPGAs) and the evolution of system-on-chip (SoC). These pivotal elements seamlessly integrate programmable logic, creating a potent synergy that manifests in spatial and temporal computing. While SoCs stand as a milestone in technological evolution, incorporating processors and reconfigurable logic areas, FPGAs emerge as fundamental devices for the rapid development of complex digital circuits. Together, SoCs and FPGAs create an ecosystem that not only accelerates the time to market but also opens the doors to a new computing paradigm, where flexibility and spatial–temporal optimization are at the forefront of digital innovation. The significance of these FPGA and SoC architectures extends beyond mere computing power, influencing the design of advanced devices in sectors such as artificial intelligence, the Internet of Things, and robotics, radically transforming how we interact with technology in our daily lives.

Prof. Dr. Nicola Lusardi
Guest Editor

Manuscript Submission Information

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Keywords

  • system-on-chip (SoC)
  • field-programmable gate arrays (FPGAs)
  • real-time processing
  • programmable temporal computing
  • programmable parallel computing
  • time mode

Published Papers (6 papers)

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Research

24 pages, 7772 KiB  
Article
A Trusted Execution Environment RISC-V System-on-Chip Compatible with Transport Layer Security 1.3
by Binh Kieu-Do-Nguyen, Khai-Duy Nguyen, Tuan-Kiet Dang, Nguyen The Binh, Cuong Pham-Quoc, Ngoc-Thinh Tran, Cong-Kha Pham and Trong-Thuc Hoang
Electronics 2024, 13(13), 2508; https://doi.org/10.3390/electronics13132508 - 26 Jun 2024
Viewed by 744
Abstract
The Trusted Execution Environment (TEE) is designed to establish a safe environment that prevents the execution of unauthenticated programs. The nature of TEE is a continuous verification process with hashing, signing, and verifying. Such a process is called the Chain-of-Trust, derived from the [...] Read more.
The Trusted Execution Environment (TEE) is designed to establish a safe environment that prevents the execution of unauthenticated programs. The nature of TEE is a continuous verification process with hashing, signing, and verifying. Such a process is called the Chain-of-Trust, derived from the Root-of-Trust (RoT). Typically, the RoT is pre-programmed, hard-coded, or embedded in hardware, which is locally produced and checked before booting. The TEE employs various cryptographic processes throughout the boot process to verify the authenticity of the bootloader. It also validates other sensitive data and applications, such as software connected to the operating system. TEE is a self-contained environment and should not serve as the RoT or handle secure boot operations. Therefore, the issue of implementing hardware for RoT has become a challenge that requires further investigation and advancement. The main objective of this proposal is to introduce a secured RISC-V-based System-on-Chip (SoC) architecture capable of securely booting a TEE using a versatile boot program while maintaining complete isolation from the TEE processors. The suggested design has many cryptographic accelerators essential for the secure boot procedure. Furthermore, a separate 32-bit MicroController Unit (MCU) is concealed from the TEE side. This MCU manages sensitive information, such as the root key, and critical operations like the Zero Stage BootLoader (ZSBL) and key generation program. Once the RoT is integrated into the isolated sub-system, it becomes completely unavailable from the TEE side, even after booting, using any method. Besides providing a secured boot flow, the system is integrated with essential crypto-cores supporting Transport Layer Security (TLS) 1.3. The chip is finally fabricated using the Complementary Metal–Oxide–Semiconductor (CMOS) 180 nm process. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design)
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20 pages, 4947 KiB  
Article
FPGA-Based Acceleration of Polar-Format Algorithm for Video Synthetic-Aperture Radar Imaging
by Dongmin Jeong, Myeongjin Lee, Wookyung Lee and Yunho Jung
Electronics 2024, 13(12), 2401; https://doi.org/10.3390/electronics13122401 - 19 Jun 2024
Viewed by 343
Abstract
This paper presents a polar-format algorithm (PFA)-based synthetic-aperture radar (SAR) processor that can be mounted on a small drone to support video SAR (ViSAR) imaging. For drone mounting, it requires miniaturization, low power consumption, and high-speed performance. Therefore, to meet these requirements, the [...] Read more.
This paper presents a polar-format algorithm (PFA)-based synthetic-aperture radar (SAR) processor that can be mounted on a small drone to support video SAR (ViSAR) imaging. For drone mounting, it requires miniaturization, low power consumption, and high-speed performance. Therefore, to meet these requirements, the processor design was based on a field-programmable gate array (FPGA), and the implementation results are presented. The proposed PFA-based SAR processor consists of both an interpolation unit and a fast Fourier transform (FFT) unit. The interpolation unit uses linear interpolation for high speed while occupying a small space. In addition, the memory transfer is minimized through optimized operations using SAR system parameters. The FFT unit uses a base-4 systolic array architecture, chosen from among various fast parallel structures, to maximize the processing speed. Each unit is designed as a reusable block (IP core) to support reconfigurability and is interconnected using the advanced extensible interface (AXI) bus. The proposed PFA-based SAR processor was designed using Verilog-HDL and implemented on a Xilinx UltraScale+ MPSoC FPGA platform. It generates an image 2048 × 2048 pixels in size within 0.766 s, which is 44.862 times faster than that achieved by the ARM Cortex-A53 microprocessor. The speed-to-area ratio normalized by the number of resources shows that it achieves a higher speed at lower power consumption than previous studies. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design)
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18 pages, 11258 KiB  
Article
Lightweight and Error-Tolerant Stereo Matching with a Stochastic Computing Processor
by Seongmo An, Jongwon Oh, Sangho Lee, Jinyeol Kim, Youngwoo Jeong, Jeongeun Kim and Seung Eun Lee
Electronics 2024, 13(11), 2024; https://doi.org/10.3390/electronics13112024 - 22 May 2024
Viewed by 475
Abstract
Stereo matching, utilized in diverse fields, poses a challenge to systems in resource-constrained environments due to the significant growth of computational load with image resolution. The challenge is crucial for the systems because fields utilizing stereo matching require short operational time for real-time [...] Read more.
Stereo matching, utilized in diverse fields, poses a challenge to systems in resource-constrained environments due to the significant growth of computational load with image resolution. The challenge is crucial for the systems because fields utilizing stereo matching require short operational time for real-time applications and low power architecture. Stochastic computing (SC) is able to be a valuable approach to address the challenge by reducing the computational load by representing binary numbers with stochastic sequences, which are encoded as a probability value, and by leveraging the concept of mathematical probability. Also, it is possible for a system to be error-tolerant by utilizing the characteristics of stochastic computing. Therefore, in this paper, we propose an approach for lightweight and error-tolerant stereo matching with a hardware-implemented stochastic computing processor. To verify the feasibility and error tolerance of the proposed system, we implemented the proposed system and conducted experiments comparing depth maps with or without stochastic computing by calculating similarities. According to the experimental results, the proposed system indicated no significant differences in output depth maps and achieved an improvement in the depth maps from error-injected input images by an average of 58.95%. Therefore, we demonstrated that stereo matching with stochastic computing is feasible and error-tolerant. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design)
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17 pages, 1675 KiB  
Article
Highly Fault-Tolerant Systolic-Array-Based Matrix Multiplication
by Hsin-Chen Lu, Liang-Ying Su and Shih-Hsu Huang
Electronics 2024, 13(9), 1780; https://doi.org/10.3390/electronics13091780 - 5 May 2024
Viewed by 566
Abstract
Matrix multiplication plays a crucial role in various engineering and scientific applications. Cannon’s algorithm, executed within two-dimensional systolic arrays, significantly enhances computational efficiency through parallel processing. However, as the matrix size increases, reliability issues become more prominent. Although the previous work has proposed [...] Read more.
Matrix multiplication plays a crucial role in various engineering and scientific applications. Cannon’s algorithm, executed within two-dimensional systolic arrays, significantly enhances computational efficiency through parallel processing. However, as the matrix size increases, reliability issues become more prominent. Although the previous work has proposed a fault-tolerant mechanism, it is only suitable for scenarios with a limited number of faulty processing elements (PEs). This paper introduces a pair-matching mechanism, assigning a fault-free PE as a proxy for each faulty PE to execute its tasks. Our fault-tolerant mechanism comprises two stages: in the first stage, each fault-free PE completes its designated computations; in the second stage, computations intended for each faulty PE are executed by its assigned fault-free PE proxy. The experimental results demonstrate that compared to the previous work, our approach not only significantly improves the fault tolerance of systolic arrays (applicable to scenarios with a higher number of faulty PEs) but also reduces circuit areas. Therefore, the proposed approach proves effective in practical applications. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design)
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21 pages, 5025 KiB  
Article
New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters
by Fabio Garzetti, Gabriele Bonanno, Nicola Lusardi, Enrico Ronconi, Andrea Costa and Angelo Geraci
Electronics 2024, 13(6), 1124; https://doi.org/10.3390/electronics13061124 - 19 Mar 2024
Viewed by 787
Abstract
Modern applications require the ability to measure time events with high resolution, a full-scale range, and multiple input channels. Time-to-Digital Converters (TDCs) are a popular option to convert time intervals into timestamps. To reduce the time-to-market and Non-Recurring Engineering (NRE) costs, a Field-Programmable [...] Read more.
Modern applications require the ability to measure time events with high resolution, a full-scale range, and multiple input channels. Time-to-Digital Converters (TDCs) are a popular option to convert time intervals into timestamps. To reduce the time-to-market and Non-Recurring Engineering (NRE) costs, a Field-Programmable Gate Array (FPGA) implementation has been chosen. The high number of requested bits and channels, however, gives rise to routing congestion issues when routed in a parallel manner. In this paper, we will propose and analyze a novel solution, the Belt-Bus (BB), which involves a parallel-to-serial conversion of the timestamp stream coming from the TDC while maintaining chronological order and a sufficient high rate, and flagging the presence of timestamp overflow. Moreover, two new useful features are added. The first is a “Virtual Delay” to compensate for offsets due to cable length and FPGA routing path mismatch. The second is a “Virtual Dead-Time” to filter out unforeseen events. Finally, the BB was tested on a Xilinx 28 nm 7-Series Kintex-7 325T FPGA, achieving an overall data rate of 199.9 Msps with very limited resource usage (i.e., lower than a total of 4.5%), consuming only 480 mW in a 16-channel implementation. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design)
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29 pages, 7863 KiB  
Article
Agile FPGA Computing at the 5G Edge: Joint Management of Accelerated and Software Functions for Open Radio Access Technologies
by Nikolaos Bartzoudis, José Rubio Fernández, David López-Bueno, Antonio Román Villarroel and Angelos Antonopoulos
Electronics 2024, 13(4), 701; https://doi.org/10.3390/electronics13040701 - 9 Feb 2024
Viewed by 1064
Abstract
This paper presents ReproRun, a flexible and extensible run-time framework for the reconfiguration of functions in field programmable gate array (FPGA) devices used in popular software-defined radio (SDR) platforms. The FPGA devices embed a hardwired or soft processing system (PS) which communicates with [...] Read more.
This paper presents ReproRun, a flexible and extensible run-time framework for the reconfiguration of functions in field programmable gate array (FPGA) devices used in popular software-defined radio (SDR) platforms. The FPGA devices embed a hardwired or soft processing system (PS) which communicates with the programmable logic (PL) using a standard embedded bus interface. In order to apply a seamless run-time partial reconfiguration, we made use of all the related building blocks, design guidelines, and tools offered by AMD-Xilinx. In ReproRun, each partial bitstream targeting a reconfigurable region (RR) of the PL area comes with its respective firmware (i.e., software functions) that runs on the PS side. Our work guarantees run-time updates of the firmware without interrupting the functionality of other software processes running in the PS or PL, by employing a specialized controller, denoted as Run-timE firmWare reconfIguration contRollEr (REWIRE). The latter leverages the open asymmetric multiprocessing framework (OpenAMP). The partial bitstreams and respective firmware are fetched from a remote location using the trivial file transfer protocol (TFTP). ReproRun can be applied in different FPGA accelerators residing in disaggregated open radio access network (RAN) equipment, adaptive radio access technologies, and Edge servers hosting virtualized functions. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design)
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