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FPGA and ASIC: State-of-the-Art Approaches to Time Measurement and Generation...
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FPGA and ASIC: State-of-the-Art Approaches to Time Measurement and Generation in Cutting-Edge Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 September 2025 | Viewed by 729

Special Issue Editors

Prof. Dr. Nicola Lusardi

E-Mail Website
Guest Editor
Department of Electronics, Information and Bioengineering, Politecnico di Milano, 20133 Milano, Italy
Interests: digital electronic; time-to-digital converter; digital-to-time converter; field programmable gate array; system-on-chip
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Fabio Garzetti

E-Mail Website
Guest Editor
Department of Electronics, Information and Bioengineering, Politecnico di Milano, 20133 Milano, Italy
Interests: FPGA; time-to-digital converters (TDC); digital electronics
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

An increasing number of applications, both in academic, metrological, and industrial contexts, rely on the measurement and generation of temporal intervals. Consider, for instance, 3D imaging applications based on time-of-flight principles such as Light Detection and Ranging (LiDAR) and Time-of-Flight Positron Emission Tomography (TOF-PET), as well as various time-resolved spectroscopic techniques like Time-Resolved Emission Spectroscopy (TRES), Fluorescence Lifetime Imaging Microscopy (FLIM), and Time-Correlated Single Photon Counting (TCSPC), to name a few. All these applications necessitate the development of so-called time-mode circuits, i.e., systems capable of measuring temporal information, such as Time-to-Digital Converters (TDCs) and Time-to-Amplitude Converters (TACs), and circuits capable of generating temporal delays, such as Digital-to-Time Converters (DTCs).

Cutting-edge applications pose an increasing number of technological challenges to TDCs, TACs, and DTCs, not only concerning performance enhancement, including precision, resolution, linearity, the number of channels operating in parallel, and processing speed, but also concerning greater compactness, flexibility, scalability, reduced power consumption, and area occupancy. This has led to the emergence of trade-offs that have given rise to various circuit solutions, not only integrated, i.e., Application Specific Integrated Circuits (ASIC), but also implemented in programmable logic devices like Field-Programmable Gate Arrays (FPGAs) and System-on-Chips (SoCs).

Moreover, modern and sophisticated measurement, calibration, and testing algorithms are at the forefront of scientific debate to optimize and validate available electronics effectively.

The purpose of this special edition is to promote the scientific dissemination of these state-of-the-art circuit solutions and testing instruments, emphasizing how application-imposed trade-offs are reflected concretely in various architectures and algorithms.

Prof. Dr. Nicola Lusardi
Prof. Dr. Fabio Garzetti
Guest Editors

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

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Keywords

  • time–mode circuit
  • time-to-digital converter (TDC)
  • time-to-amplitude converter (TAC)
  • digital-to-time converter (DTC)
  • delay-line (DL)
  • programmable delay-line (PDL)
  • tapped delay-line (TDL)
  • TDC/TAC architecture
  • DTC architecture
  • FPGA-based TDC
  • FPGA-based DTC
  • ASIC-based TDC/TAC
  • ASIC-based DTC
  • TDC/TAC/DTC calibration and encoding/decoding
  • TDC/TAC/DTC characterization and testing
  • TDC/TAC/DTC in time-resolved applications
  • TDC/TAC/DTC in time-of-fligth applications
  • TDC/TAC/DTC in time-based system

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Published Papers (2 papers)

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18 pages, 2108 KiB  
Article
An Efficient Multi-Output LUT Mapping Technique for Field-Programmable Gate Arrays
by Sheng Lu, Liuting Shang, Qianhou Qu, Sungyong Jung, Qilian Liang and Chenyun Pan
Electronics 2025, 14(9), 1782; https://doi.org/10.3390/electronics14091782 (registering DOI) - 27 Apr 2025
Abstract
The use of multi-output look-up tables (LUTs) is a widely adopted approach in contemporary commercial field-programmable gate arrays (FPGAs). Larger LUT configurations (e.g., six-input LUTs) can be partitioned into smaller LUTs (e.g., two five-input LUTs, maintaining a total input count of less than [...] Read more.
The use of multi-output look-up tables (LUTs) is a widely adopted approach in contemporary commercial field-programmable gate arrays (FPGAs). Larger LUT configurations (e.g., six-input LUTs) can be partitioned into smaller LUTs (e.g., two five-input LUTs, maintaining a total input count of less than six). This capability of generating a second output from a larger LUT is not only crucial for reducing logic cell count and enhancing the utilization efficiency of logic resources—thus conserving area—but also plays a key role in optimizing system-level delays and energy consumption. In this paper, we propose an efficient multi-output LUT mapping technique, incorporating several highly efficient technology mapping algorithms, which focus on optimizing the mapping from an interconnection perspective as alternatives to directly merging smaller LUTs. These algorithms include a side-fanout insertion algorithm, and a runtime multi-output cut generation algorithm. The proposed methods improve mapping efficiency and enhance performance. The benchmarking results demonstrate that the dual-output mapping algorithms achieve LUT area reductions of up to 35% and 6%, compared to the state-of-the-art ABC six-input, single-output LUT mapping technique and previous work focusing on dual-output LUT mapping techniques that optimize cut generation parameters. Moreover, FPGA system-level simulations also show that area, delay, and energy can all be optimized based on this multi-output mapping technique. Full article
(This article belongs to the Special Issue FPGA and ASIC: State-of-the-Art Approaches to Time Measurement and Generation in Cutting-Edge Applications)
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17 pages, 4741 KiB  
Article
First Study of Bubble Error Artifacts in Field-Programmable Gate Array (FPGA)-Based Tapped Delay-Line Time-to-Digital Converters with Sum-of-Ones Decoder on Xilinx 28 nm 7-Series FPGA
by Nicola Lusardi, Fabio Garzetti, Gabriele Fiumicelli, Mattia Morabito, Gabriele Bonanno, Enrico Ronconi, Andrea Costa and Angelo Geraci
Electronics 2025, 14(6), 1156; https://doi.org/10.3390/electronics14061156 - 15 Mar 2025
Viewed by 331
Abstract
Time-to-Digital Converters (TDCs) are increasingly vital in modern measurement systems, with Field-Programmable Gate Arrays (FPGAs) offering a cost-effective platform despite challenges in asynchronous circuit design. Among various solutions, Tapped Delay-Line (TDL)-TDCs stand out for balancing precision, speed, and resource efficiency. However, a primary [...] Read more.
Time-to-Digital Converters (TDCs) are increasingly vital in modern measurement systems, with Field-Programmable Gate Arrays (FPGAs) offering a cost-effective platform despite challenges in asynchronous circuit design. Among various solutions, Tapped Delay-Line (TDL)-TDCs stand out for balancing precision, speed, and resource efficiency. However, a primary concern in FPGA-based TDL-TDCs are the Bubble Errors (BEs), i.e., spurious zeros introduced in the information code in the TDL that put the measurement precision at severe risk. The main goal of this contribution is to investigate the distribution of BEs, utilizing the Clock Region Crossing (CRC) within the FPGA as a case study, in order to demonstrate theoretically and experimentally that if BEs are manipulated properly, they create an interpolation effect that reduces the quantization error of the TDL-TDC. The analysis is carried out on a 256-tap fully integrated TDL-TDC implemented in a 28 nm Xilinx Artix 100T FPGA. The outcome confirms the potential to use CRC-BEs instead of suppressing them with precision increasing up to 0.17 ps r.m.s., or by almost 2% while also supporting the correctness of the model. Full article
(This article belongs to the Special Issue FPGA and ASIC: State-of-the-Art Approaches to Time Measurement and Generation in Cutting-Edge Applications)
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