FPGA and ASIC: State-of-the-Art Approaches to Time Measurement and Generation in Cutting-Edge Applications

Dear Colleagues,

An increasing number of applications, both in academic, metrological, and industrial contexts, rely on the measurement and generation of temporal intervals. Consider, for instance, 3D imaging applications based on time-of-flight principles such as Light Detection and Ranging (LiDAR) and Time-of-Flight Positron Emission Tomography (TOF-PET), as well as various time-resolved spectroscopic techniques like Time-Resolved Emission Spectroscopy (TRES), Fluorescence Lifetime Imaging Microscopy (FLIM), and Time-Correlated Single Photon Counting (TCSPC), to name a few. All these applications necessitate the development of so-called time-mode circuits, i.e., systems capable of measuring temporal information, such as Time-to-Digital Converters (TDCs) and Time-to-Amplitude Converters (TACs), and circuits capable of generating temporal delays, such as Digital-to-Time Converters (DTCs).

Cutting-edge applications pose an increasing number of technological challenges to TDCs, TACs, and DTCs, not only concerning performance enhancement, including precision, resolution, linearity, the number of channels operating in parallel, and processing speed, but also concerning greater compactness, flexibility, scalability, reduced power consumption, and area occupancy. This has led to the emergence of trade-offs that have given rise to various circuit solutions, not only integrated, i.e., Application Specific Integrated Circuits (ASIC), but also implemented in programmable logic devices like Field-Programmable Gate Arrays (FPGAs) and System-on-Chips (SoCs).

Moreover, modern and sophisticated measurement, calibration, and testing algorithms are at the forefront of scientific debate to optimize and validate available electronics effectively.

The purpose of this special edition is to promote the scientific dissemination of these state-of-the-art circuit solutions and testing instruments, emphasizing how application-imposed trade-offs are reflected concretely in various architectures and algorithms.

Prof. Dr. Nicola Lusardi
Prof. Dr. Fabio Garzetti
Guest Editors

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• time–mode circuit
• time-to-digital converter (TDC)
• time-to-amplitude converter (TAC)
• digital-to-time converter (DTC)
• delay-line (DL)
• programmable delay-line (PDL)
• tapped delay-line (TDL)
• TDC/TAC architecture
• DTC architecture
• FPGA-based TDC
• FPGA-based DTC
• ASIC-based TDC/TAC
• ASIC-based DTC
• TDC/TAC/DTC calibration and encoding/decoding
• TDC/TAC/DTC characterization and testing
• TDC/TAC/DTC in time-resolved applications
• TDC/TAC/DTC in time-of-fligth applications
• TDC/TAC/DTC in time-based system