High-Speed I/O Circuits and Architectures

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (15 January 2022) | Viewed by 7783

Special Issue Editors


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Guest Editor
Ayar Labs, Santa Clara, CA 95054, USA
Interests: integrated circuits for silicon photonics; high-speed I/O circuits and architectures; non-volatile memory systems; agile hardware design methodology

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Guest Editor
Department of Electronic Engineering, Hanyang University, Seongdong-gu, Seoul 04763, Republic of Korea
Interests: high-speed analog; mixed-signal (AMS) circuit design; automation

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Guest Editor
Samsung Semiconductor Inc., San Jose, CA 95112, USA
Interests: high-speed link circuit design; signal/power integrity; interconnect modeling

Special Issue Information

Dear Colleagues,

The explosive growth of data traffic requires advances in both high-performance computing systems and data communication systems. Especially, the requirement of high-performance data communication systems is being emphasized more than ever, because of ever-increasing demand for data throughput in every computing system. A microprocessor with memory constituting a tiny computing system is now required to handle several hundreds of gigabits per second, and this is growing at a relentless rate. Similar trends are also occurring in longer-distance applications such as inter-server and long-haul communications. However, at the same time, the channel loss of electrical wires is becoming very significant as the required data rate increases, and I/O interfaces are facing many challenges. It will be tougher as the scaling ends because we will no longer be able to take advantage of faster transistors.The aim of this Special issue is to present circuit and architecture level techniques and to guide technology directions for the years to come. The topics to be covered in this Special Issue include but are not limited to the following:

  • Design techniques for high-speed I/O transmitters, receivers, and transceivers;
  • Building blocks for NRZ/PAM-N/DSP-based I/O transceivers;
  • Low-power I/O circuit techniques;
  • Memory interfaces;
  • Clock generation/distribution/recovery circuits;
  • Circuits and architectures for optical interconnect for computer communications

Dr. Woorham Bae
Prof. Dr. JaeDuk Han
Dr. Minsoo Choi
Guest Editors

Manuscript Submission Information

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Keywords

  • Integrated circuits
  • CMOS
  • High-speed I/O transceivers
  • Phase-locked loops
  • Clock and data recovery
  • Optical interconnect
  • Silicon photonics

Published Papers (2 papers)

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Research

12 pages, 5476 KiB  
Article
Design and Analysis of Asynchronous Sampling Duty Cycle Corrector
by Gijin Park, Jaeduk Han and Woorham Bae
Electronics 2021, 10(21), 2594; https://doi.org/10.3390/electronics10212594 - 24 Oct 2021
Cited by 2 | Viewed by 3173
Abstract
This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the settling [...] Read more.
This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the settling behavior of an asynchronous sampling duty cycle corrector is limited in some operation conditions, which degrades its robustness and performance. This paper, therefore, performs analysis on the settling behavior of the asynchronous sampling in various operating conditions and proposes a control scheme to avoid the lagged settling. To verify the proposed duty cycle corrector and its analysis, a prototype design is implemented in a 40-nm CMOS process and its performance is verified by post-layout simulations. The proposed duty cycle corrector achieved very small duty cycle errors (less than 0.8%) and consumed 540 uW per one DCC unit. Full article
(This article belongs to the Special Issue High-Speed I/O Circuits and Architectures)
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10 pages, 6822 KiB  
Article
An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation
by Changho Hyun, Yong-Un Jeong, Suhwan Kim and Joo-Hyung Chae
Electronics 2021, 10(15), 1768; https://doi.org/10.3390/electronics10151768 - 24 Jul 2021
Cited by 3 | Viewed by 3720
Abstract
This paper presents a method for preventing output level distortion while matching the channel impedance in the single-ended PAM-4 transmitter for memory interfaces. ZQ codes for all four output signal levels were obtained through ZQ calibration and saved in the ZQ code table. [...] Read more.
This paper presents a method for preventing output level distortion while matching the channel impedance in the single-ended PAM-4 transmitter for memory interfaces. ZQ codes for all four output signal levels were obtained through ZQ calibration and saved in the ZQ code table. The ZQ code generator then adaptively selected the appropriate codes depending on the data pattern and delivered them to the output driver; this can improve the level separation mismatch ratio (RLM) while matching the channel impedance. To validate the effectiveness of our approach, a prototype chip with an active area of 0.035 mm2 was fabricated in a 65 nm CMOS process. It achieved the energy efficiency of 3.09 pJ/bit/pin at 18 Gb/s/pin, and its RLM was 0.971 while matching the channel impedance. Full article
(This article belongs to the Special Issue High-Speed I/O Circuits and Architectures)
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