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Electronics
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Storage Systems with Non-volatile Memory Devices
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Storage Systems with Non-volatile Memory Devices

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 December 2021) | Viewed by 16612

Special Issue Editor

Prof. Dr. Seung-Ho Lim

E-Mail Website
Guest Editor
System Software Laboratory, Division of Computer and Electronic Systems Engineering, Hankuk University of Foreign Studies, 107, Imun-ro, Dongdaemun-gu, Seoul 130-791, Korea
Interests: operating systems; embedded systems; flash storage systems; mobile and IoT applications; big data systems; interconnection network for HPC

Special Issue Information

Dear Colleagues,

Due to advances in memory semiconductor technology, the performance of non-volatile memory devices has significantly improved its speed as well as storage capacity. Non-volatile memory-based storage devices and storage systems can greatly improve IO performance, which can greatly contribute to the improvement of computing system performance. In particular, as non-volatile memory is applied not only as a storage IO device, but also in the field of in-memory computing, it is leading the paradigm shift of computer architecture. Non-volatile memory-related technologies include non-volatile memory device technologies such as NAND flash memory, MRAM, PRAM, and FeRAM, IO interface technologies such as SaS, SATA, and PCIe NVMe, and non-volatile memory-based storage system technologies with storage media such as SSD and hybrid storage devices.

This Special Issue focuses on emerging hardware and software technologies related to non-volatile memory-device-based storage systems, including analysis, design, and implementation of storage systems with non-volatile memory devices.

Prof. Dr. Seung-Ho Lim
Guest Editor

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Keywords

  • Modeling and specifications for emerging NVMs
  • System architecture with NVM storage
  • Prototyping and evaluation for storage systems with NVMs and SSDs
  • NVM-based software and hardware
  • Interface technologies for NVMs

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Published Papers (5 papers)

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Research

19 pages, 6325 KiB  
Article
EXPRESS: Exploiting Energy–Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage
by Md Raquibuzzaman, Aleksandar Milenkovic and Biswajit Ray
Electronics 2022, 11(3), 424; https://doi.org/10.3390/electronics11030424 - 30 Jan 2022
Cited by 4 | Viewed by 5216
Abstract
The density and cost-effectiveness of flash memory chips continue to increase, driven by: (a) The continuous physical scaling of memory cells in a single layer; (b) The vertical stacking of multiple layers; and (c) Logical scaling through storing multiple bits of information in [...] Read more.
The density and cost-effectiveness of flash memory chips continue to increase, driven by: (a) The continuous physical scaling of memory cells in a single layer; (b) The vertical stacking of multiple layers; and (c) Logical scaling through storing multiple bits of information in a single memory cell. The physical properties of flash memories impose disproportionate latency and energy expenditures to ensure the high integrity of the data during flash memory writes. This paper experimentally explores this disproportionality on state-of-the-art commercial 3D NAND flash memories and introduces EXPRESS—a technique for increasing the energy efficiency of flash memory writes by exploiting the premature termination of the flash write operations. An experimental evaluation shows that EXPRESS reduces energy expenditures by 20–50%, relative to the traditional flash writes, at the cost of a minimal loss in the data integrity (<1%). In addition, we evaluate the effects of the page-to-page variability, program–erase cycling, and data retention on the implementation of EXPRESS, and we propose enhancements to counter these effects. Full article
(This article belongs to the Special Issue Storage Systems with Non-volatile Memory Devices)
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13 pages, 11471 KiB  
Article
Storage Type and Hot Partition Aware Page Reclamation for NVM Swap in Smartphones
by Hyejung Yoon, Kyungwoon Cho and Hyokyung Bahn
Electronics 2022, 11(3), 386; https://doi.org/10.3390/electronics11030386 - 27 Jan 2022
Cited by 2 | Viewed by 2664
Abstract
With the rapid advances in mobile app technologies, new activities using smartphones emerge every day including social network and location-based services. However, smartphones experience problems in handling high priority tasks, and often close apps without the user’s agreement when there is no available [...] Read more.
With the rapid advances in mobile app technologies, new activities using smartphones emerge every day including social network and location-based services. However, smartphones experience problems in handling high priority tasks, and often close apps without the user’s agreement when there is no available memory space. To cope with this situation, supporting swap with fast NVM storage has been suggested. Although swap in smartphones incurs serious slowing-down problems in I/O operations during saving and restoring the context of apps, NVM has been shown to resolve this problem due to its fast I/O features. Unlike previous studies that only focused on the management of NVM swap itself, this article discusses how the memory management system of smartphones can be further improved with NVM swap. Specifically, we design a new page reclamation algorithm for smartphone memory systems, which considers the following: (1) storage types of each partition (i.e., file system for flash storage and swap for NVM), and (2) access hotness of each partition including operation types and workload characteristics. By considering asymmetric I/O cost and access density for each partition, our algorithm improves the I/O performance of smartphones significantly. Specifically, it improves the I/O time by 15.0% on average and by up to 35.1% compared to the well-known CLOCK algorithm. Full article
(This article belongs to the Special Issue Storage Systems with Non-volatile Memory Devices)
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17 pages, 854 KiB  
Article
TA-CLOCK: Tendency-Aware Page Replacement Policy for Hybrid Main Memory in High-Performance Embedded Systems
by Jun Hyeong Choi, Kyung Min Kim and Jong Wook Kwak
Electronics 2021, 10(9), 1111; https://doi.org/10.3390/electronics10091111 - 8 May 2021
Cited by 2 | Viewed by 2546
Abstract
Recently, high-performance embedded systems have adopted phase change memory (PCM) as their main memory because PCMs have attractive advantages, such as non-volatility, byte-addressability, high density, and low power consumption. However, PCMs have disadvantages, such as limited write endurance in each cell and high [...] Read more.
Recently, high-performance embedded systems have adopted phase change memory (PCM) as their main memory because PCMs have attractive advantages, such as non-volatility, byte-addressability, high density, and low power consumption. However, PCMs have disadvantages, such as limited write endurance in each cell and high write latency compared to DRAMs. Therefore, researchers have investigated methods for enhancing the limitations of PCMs. In this paper, we propose a page replacement policy called tendency-aware CLOCK (TA-CLOCK) for the hybrid main memory of embedded systems. To improve the limited write endurance of PCMs, TA-CLOCK classifies the page access tendency of the victim page through access pattern analysis and determines the migration location of the victim page. Through the classification of the page access tendency, TA-CLOCK reduces unnecessary page migrations from DRAMs to PCMs. Unnecessary migrations cause an increase in write operations in PCMs and the energy consumption of the hybrid main memory in embedded systems. Thus, our proposed policy improves the limited write endurance of PCMs and enhances the access latency of the hybrid main memory of embedded systems by classifying the page access tendency. We compared the TA-CLOCK with existing page replacement policies to evaluate its performance. In our experiments, TA-CLOCK reduced the number of write operations in PCMs by 71.5% on average, and it enhanced the energy delay product by 38.3% on average compared with other page replacement policies. Full article
(This article belongs to the Special Issue Storage Systems with Non-volatile Memory Devices)
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20 pages, 774 KiB  
Article
ICEr: An Intermittent Computing Environment Based on a Run-Time Module for Energy-Harvesting IoT Devices with NVRAM
by Junho Kwak, Hyeongrae Kim and Jeonghun Cho
Electronics 2021, 10(8), 879; https://doi.org/10.3390/electronics10080879 - 7 Apr 2021
Cited by 1 | Viewed by 2364
Abstract
With the development of energy-harvesting technology, various applications have been developed that can be operated only with harvested energy, thereby making energy-harvesting technology suitable for edge devices in poor environments where battery replacement is difficult. However, devices with energy-harvesting technology have limitations: an [...] Read more.
With the development of energy-harvesting technology, various applications have been developed that can be operated only with harvested energy, thereby making energy-harvesting technology suitable for edge devices in poor environments where battery replacement is difficult. However, devices with energy-harvesting technology have limitations: an application can operate intermittently in an energy-harvesting device, and the device’s energy is greatly affected by the environment and the state of the device. Intermittent computing causes abnormal progress or affords incorrect results. The factors affecting the energy of the device can change the operation of the device. To solve these problems, we propose the “Intermittent Computing Environment based on a run-time module” (ICEr), which dynamically controls and manages an application for normal operation in intermittent computing. ICEr comprises an energy checker and a controller. The energy checker measures the energy state of a device at run-time, and the controller controls and manages an application through Backup, Restore, Sleep, and Wakeup. The controller optimizes those operations by considering the energy state and memory state together to minimize time and energy overhead. In this study, two kinds of experiments were conducted. In the first experiment, Embench was selected as the target application to validate ICEr and measure its performance. This experiment validated that ICEr behaves dynamically in various environments. Moreover, it showed a reduction in relative execution time overhead of up to 50% and a reduction in energy overhead of up to 49.5% against Hibernus, depending on the environment. In the second experiment, ICEr was applied to the Temperature Measurement Application, and the improvement of the energy efficiency for the real Internet-of-Things (IoT) application was confirmed. Full article
(This article belongs to the Special Issue Storage Systems with Non-volatile Memory Devices)
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23 pages, 1401 KiB  
Article
Polymorphic Memory: A Hybrid Approach for Utilizing On-Chip Memory in Manycore Systems
by Seung-Ho Lim, Hyunchul Seok and Ki-Woong Park
Electronics 2020, 9(12), 2061; https://doi.org/10.3390/electronics9122061 - 3 Dec 2020
Viewed by 2463
Abstract
The key challenges of manycore systems are the large amount of memory and high bandwidth required to run many applications. Three-dimesnional integrated on-chip memory is a promising candidate for addressing these challenges. The advent of on-chip memory has provided new opportunities to rethink [...] Read more.
The key challenges of manycore systems are the large amount of memory and high bandwidth required to run many applications. Three-dimesnional integrated on-chip memory is a promising candidate for addressing these challenges. The advent of on-chip memory has provided new opportunities to rethink traditional memory hierarchies and their management. In this study, we propose a polymorphic memory as a hybrid approach when using on-chip memory. In contrast to previous studies, we use the on-chip memory as both a main memory (called M1 memory) and a Dynamic Random Access Memory (DRAM) cache (called M2 cache). The main memory consists of M1 memory and a conventional DRAM memory called M2 memory. To achieve high performance when running many applications on this memory architecture, we propose management techniques for the main memory with M1 and M2 memories and for polymorphic memory with dynamic memory allocations for many applications in a manycore system. The first technique is to move frequently accessed pages to M1 memory via hardware monitoring in a memory controller. The second is M1 memory partitioning to mitigate contention problems among many processes. Finally, we propose a method to use M2 cache between a conventional last-level cache and M2 memory, and we determine the best cache size for improving the performance with polymorphic memory. The proposed schemes are evaluated with the SPEC CPU2006 benchmark, and the experimental results show that the proposed approaches can improve the performance under various workloads of the benchmark. The performance evaluation confirms that the average performance improvement of polymorphic memory is 21.7%, with 0.026 standard deviation for the normalized results, compared to the previous method of using on-chip memory as a last-level cache. Full article
(This article belongs to the Special Issue Storage Systems with Non-volatile Memory Devices)
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