Design of Ultra-Low Voltage/Power Circuits and Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (30 November 2021) | Viewed by 23474

Special Issue Editors


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Guest Editor
Department of Computer Science, Modeling, Electronics and Systems Engineering (DIMES), University of Calabria, 87036 Rende, Italy
Interests: ultralow-power CMOS digital; mixed-signal circuits; modeling and design methodologies for leakage- and variability-aware circuits; arithmetic circuits
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Guest Editor
Department of Computer Science, Modeling, Electronics and Systems Engineering (DIMES), University of Calabria, 87036 Rende (CS), Italy
Interests: low-voltage and low-power circuit design; hybrid CMOS/spintronics circuits and memories; hardware security

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Guest Editor
Department of Information Engineering (DII), University of Pisa, 56122 Pisa, Italy
Interests: emerging technologies for ultralow-voltage devices and non-volatile memories; circuits for innovative computing applications; CMOS image sensors
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Ultra-low voltage/power analog and digital designs are highly sought-after for tightly energy- and cost-constrained integrated systems such as sensor nodes for the Internet of Things, implantable devices, always-on or purely energy-harvested systems. The latter mandate extremely low power (even down to few nWs) and low minimum supply voltage (<< 1V) to prolong operations under unfavorable environmental conditions, along with small area occupation, low design effort, and technology/design portability. The primary aim of this Special Issue is to attract original research outcomes related to the theory, design, and application of ultra-low voltage/power circuits and systems. Review papers on the topic are also welcome.

Prof. Dr. Marco Lanuzza
Dr. Raffaele De Rose
Dr. Sebastiano Strangio
Guest Editors

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Keywords

  • Theory and design of ultra-low voltage/power analog and digital circuits
  • Novel applications of ultra-low voltage/power electronics
  • Energy-harvested systems
  • Implantable and wearable devices for biomedical monitoring applications
  • Ultra-low voltage/power circuits for Internet of Things (IoT) applications
  • Design techniques to achieve robustness and reliability at reduced power supply voltages

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Published Papers (6 papers)

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Editorial

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3 pages, 176 KiB  
Editorial
Design of Ultra-Low Voltage/Power Circuits and Systems
by Marco Lanuzza, Raffaele De Rose and Sebastiano Strangio
Electronics 2022, 11(4), 607; https://doi.org/10.3390/electronics11040607 - 16 Feb 2022
Cited by 2 | Viewed by 2170
Abstract
Over the last years, the Internet of Things (IoT), wireless sensor networks and the emergence of other energy-constrained applications have pushed the demand for low-cost systems-on-chip solutions, entailing tight area and small power/voltage budgets [...] Full article
(This article belongs to the Special Issue Design of Ultra-Low Voltage/Power Circuits and Systems)

Research

Jump to: Editorial

14 pages, 1856 KiB  
Article
Embedded Memories for Cryogenic Applications
by Esteban Garzón, Adam Teman and Marco Lanuzza
Electronics 2022, 11(1), 61; https://doi.org/10.3390/electronics11010061 - 25 Dec 2021
Cited by 17 | Viewed by 3610
Abstract
The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic [...] Read more.
The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below. Full article
(This article belongs to the Special Issue Design of Ultra-Low Voltage/Power Circuits and Systems)
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16 pages, 3661 KiB  
Article
A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V
by Andrea Ria, Alessandro Catania, Paolo Bruschi and Massimo Piotto
Electronics 2021, 10(16), 1901; https://doi.org/10.3390/electronics10161901 - 8 Aug 2021
Cited by 10 | Viewed by 6158
Abstract
A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS [...] Read more.
A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS bandgap core, properly modified to be compatible with low-threshold or zero-threshold MOSFETs. The advantages of the proposed circuit are illustrated with theoretical analysis and supported by numerical simulations. The core was combined with a recently proposed switched capacitor, inverter-like integrator implementing offset cancellation and low-frequency noise reduction techniques. Experimental results performed on a prototype designed and fabricated using a commercial 0.18 μm CMOS process are presented. The prototype produces a reference voltage of 220 mV with a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range. The proposed voltage reference can be used to source currents up to 100 μA with a quiescent current consumption of only 630 nA. Full article
(This article belongs to the Special Issue Design of Ultra-Low Voltage/Power Circuits and Systems)
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10 pages, 15786 KiB  
Article
A Low Dark Current 160 dB Logarithmic Pixel with Low Voltage Photodiode Biasing
by Alessandro Michel Brunetti and Bhaskar Choubey
Electronics 2021, 10(9), 1096; https://doi.org/10.3390/electronics10091096 - 7 May 2021
Cited by 4 | Viewed by 3932
Abstract
Extending CMOS Image Sensors’ dynamic range is of fundamental importance in applications, such as automotive, scientific, or X-ray, where a broad variation of incoming light should be measured. The typical logarithmic pixels suffer from poor performance under low light conditions due to a [...] Read more.
Extending CMOS Image Sensors’ dynamic range is of fundamental importance in applications, such as automotive, scientific, or X-ray, where a broad variation of incoming light should be measured. The typical logarithmic pixels suffer from poor performance under low light conditions due to a leakage current, usually referred to as the dark current. In this paper, we propose a logarithmic pixel design capable of reducing the dark current through low-voltage photodiode biasing, without introducing any process modifications. The proposed pixel combines a high dynamic range with a significant improvement in the dark response compared to a standard logarithmic pixel. The reported experimental results show this architecture to achieve an almost 35 dB improvement at the expense of three additional transistors, thereby achieving an unprecedented dynamic range higher than 160 dB. Full article
(This article belongs to the Special Issue Design of Ultra-Low Voltage/Power Circuits and Systems)
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11 pages, 1722 KiB  
Article
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder
by Kevin Vicuña, Cristhopher Mosquera, Ariana Musello, Sara Benedictis, Mateo Rendón, Esteban Garzón, Luis Miguel Prócel, Lionel Trojman and Ramiro Taco
Electronics 2021, 10(9), 1052; https://doi.org/10.3390/electronics10091052 - 29 Apr 2021
Cited by 6 | Viewed by 2766
Abstract
This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design [...] Read more.
This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode. Full article
(This article belongs to the Special Issue Design of Ultra-Low Voltage/Power Circuits and Systems)
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11 pages, 3853 KiB  
Article
A Low-Voltage, Low-Power Reconfigurable Current-Mode Softmax Circuit for Analog Neural Networks
by Massimo Vatalaro, Tatiana Moposita, Sebastiano Strangio, Lionel Trojman, Andrei Vladimirescu, Marco Lanuzza and Felice Crupi
Electronics 2021, 10(9), 1004; https://doi.org/10.3390/electronics10091004 - 22 Apr 2021
Cited by 8 | Viewed by 3358
Abstract
This paper presents a novel low-power low-voltage analog implementation of the softmax function, with electrically adjustable amplitude and slope parameters. We propose a modular design, which can be scaled by the number of inputs (and of corresponding outputs). It is composed of input [...] Read more.
This paper presents a novel low-power low-voltage analog implementation of the softmax function, with electrically adjustable amplitude and slope parameters. We propose a modular design, which can be scaled by the number of inputs (and of corresponding outputs). It is composed of input current–voltage linear converter stages (1st stages), MOSFETs operating in a subthreshold regime implementing the exponential functions (2nd stages), and analog divider stages (3rd stages). Each stage is only composed of p-type MOSFET transistors. Designed in a 0.18 µm CMOS technology (TSMC), the proposed softmax circuit can be operated at a supply voltage of 500 mV. A ten-input/ten-output realization occupies a chip area of 2570 µm2 and consumes only 3 µW of power, representing a very compact and energy-efficient option compared to the corresponding digital implementations. Full article
(This article belongs to the Special Issue Design of Ultra-Low Voltage/Power Circuits and Systems)
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