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Electronics
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Embedded IoT: System Design and Applications
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Embedded IoT: System Design and Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 July 2021) | Viewed by 30251

Special Issue Editors

Prof. Dr. Abdellah Touhafi

E-Mail Website
Guest Editor
Department of Engineering Sciences and Technology (INDI), Vrije Universiteit Brussel, 1090 Brussels, Belgium
Interests: security; wireless sensor network; network; sensors; computer engineering; FPGA; reconfigurable computing; hardware
Special Issues, Collections and Topics in MDPI journals
Dr. Gianluca Cornetta

E-Mail Website
Guest Editor
Department of Information Engineering, Universidad San Pablo-CEU, 28003 Madrid, Spain
Interests: IoT; energy harvesting and RF communication technologies; embedded AI; Edge and Cloud software and hardware architectures
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Embedded IoT systems combine a vast number of technological challenges related to embedded software, embedded computing, low-power communication protocols, embedded security protocols, embedded energy harvesting, near sensor data processing, embedded AI techniques, and integration in cloud and edge computing systems.

It is only by tackling all those challenges on their own or within a cross-layer optimization approach that the next generation of IoT-enabled embedded devices will become a reality and some emerging applications will find their way in our daily life and in industry. The impact of embedded IoT devices is starting to appear in many new domains like interconnected vehicles, Industry 4.0, smart buildings, smart cities, e-farming, e-health, and education. As such, it becomes necessary to reflect on the developed theories, engineering, and development techniques and the applications.

In this Special Issue, we aim at collecting high-quality submissions that include the theoretical aspects, the engineering aspects, and the application aspects of embedded IoT devices and systems. The topics of interest include but are not limited to:

  • Embedded data visualization techniques for IoT-based instrumentation;
  • Embedded AI techniques for IoT;
  • Embedded energy harvesting for ultralow-power IoT devices;
  • Low-power data processing techniques for energy-constrained IoT devices;
  • Security aspects of IoT-based systems;
  • Advanced IoT hardware platforms and innovative architectures;
  • Cross platform software design techniques for embedded IoT;
  • Embedded operating systems for IoT;
  • Real-time operating systems for IoT;
  • Communication strategies for embedded IoT;
  • Innovative antenna design for embedded IoT systems;
  • Edge computing techniques for IoT applications;
  • Fog computing for IoT applications;
  • Optimization techniques for embedded IoT infrastructure;
  • Embedded IoT for Industry 4.0 applications;
  • Embedded IoT for e-health applications;
  • Embedded IoT for smart buildings;
  • Embedded IoT for smart cities;
  • Embedded IoT for smart mobility infrastructure;
  • Embedded IoT for education;
  • Embedded IoT for the green economy;
  • Embedded IoT for the sharing economy.

Prof. Dr. Abdellah Touhafi
Prof. Dr. Gianluca Cornetta
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • embedded IoT
  • embedded AI
  • IoT hardware platforms
  • IoT software platforms
  • RTOS for IoT
  • IoT security
  • low-power IoT
  • edge computing
  • fog computing
  • e-health
  • embedded energy harvesting

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Published Papers (7 papers)

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Research

23 pages, 3627 KiB  
Article
Person Re-Identification Microservice over Artificial Intelligence Internet of Things Edge Computing Gateway
by Ching-Han Chen and Chao-Tsu Liu
Electronics 2021, 10(18), 2264; https://doi.org/10.3390/electronics10182264 - 15 Sep 2021
Cited by 9 | Viewed by 2955
Abstract
With the increase in the number of surveillance cameras being deployed globally, an important topic is person re-identification (Re-ID), which identifies the same person from multiple different angles and different directions across multiple cameras. However, because of the privacy issues involved in the [...] Read more.
With the increase in the number of surveillance cameras being deployed globally, an important topic is person re-identification (Re-ID), which identifies the same person from multiple different angles and different directions across multiple cameras. However, because of the privacy issues involved in the identification of individuals, Re-ID systems cannot send the image data to cloud, and these data must be processed on edge servers. However, there has been a significant increase in computing resources owing to the processing of artificial intelligence (AI) algorithms through edge computing (EC). Consequently, the traditional AI Internet of Things (AIoT) architecture is no longer sufficient. In this study, we designed a Re-ID system at the AIoT EC gateway, which utilizes a microservice to perform Re-ID calculations on EC and balances efficiency with privacy protection. Experimental results indicate that this architecture can provide sufficient Re-ID computing resources to allow the system to scale up or down flexibly to support different scenarios and demand loads. Full article
(This article belongs to the Special Issue Embedded IoT: System Design and Applications)
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21 pages, 2318 KiB  
Article
Impact of Input Data on Intelligence Partitioning Decisions for IoT Smart Camera Nodes
by Isaac Sánchez Leal, Irida Shallari, Silvia Krug, Axel Jantsch and Mattias O’Nils
Electronics 2021, 10(16), 1898; https://doi.org/10.3390/electronics10161898 - 7 Aug 2021
Cited by 3 | Viewed by 2106
Abstract
Image processing systems exploit image information for a purpose determined by the application at hand. The implementation of image processing systems in an Internet of Things (IoT) context is a challenge due to the amount of data in an image processing system, which [...] Read more.
Image processing systems exploit image information for a purpose determined by the application at hand. The implementation of image processing systems in an Internet of Things (IoT) context is a challenge due to the amount of data in an image processing system, which affects the three main node constraints: memory, latency and energy. One method to address these challenges is the partitioning of tasks between the IoT node and a server. In this work, we present an in-depth analysis of how the input image size and its content within the conventional image processing systems affect the decision on where tasks should be implemented, with respect to node energy and latency. We focus on explaining how the characteristics of the image are transferred through the system until finally influencing partition decisions. Our results show that the image size affects significantly the efficiency of the node offloading configurations. This is mainly due to the dominant cost of communication over processing as the image size increases. Furthermore, we observed that image content has limited effects in the node offloading analysis. Full article
(This article belongs to the Special Issue Embedded IoT: System Design and Applications)
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52 pages, 2321 KiB  
Article
Towards Secure Fog Computing: A Survey on Trust Management, Privacy, Authentication, Threats and Access Control
by Abdullah Al-Noman Patwary, Ranesh Kumar Naha, Saurabh Garg, Sudheer Kumar Battula, Md Anwarul Kaium Patwary, Erfan Aghasian, Muhammad Bilal Amin, Aniket Mahanti and Mingwei Gong
Electronics 2021, 10(10), 1171; https://doi.org/10.3390/electronics10101171 - 14 May 2021
Cited by 47 | Viewed by 7817
Abstract
Fog computing is an emerging computing paradigm that has come into consideration for the deployment of Internet of Things (IoT) applications amongst researchers and technology industries over the last few years. Fog is highly distributed and consists of a wide number of autonomous [...] Read more.
Fog computing is an emerging computing paradigm that has come into consideration for the deployment of Internet of Things (IoT) applications amongst researchers and technology industries over the last few years. Fog is highly distributed and consists of a wide number of autonomous end devices, which contribute to the processing. However, the variety of devices offered across different users are not audited. Hence, the security of Fog devices is a major concern that should come into consideration. Therefore, to provide the necessary security for Fog devices, there is a need to understand what the security concerns are with regards to Fog. All aspects of Fog security, which have not been covered by other literature works, need to be identified and aggregated. On the other hand, privacy preservation for user’s data in Fog devices and application data processed in Fog devices is another concern. To provide the appropriate level of trust and privacy, there is a need to focus on authentication, threats and access control mechanisms as well as privacy protection techniques in Fog computing. In this paper, a survey along with a taxonomy is proposed, which presents an overview of existing security concerns in the context of the Fog computing paradigm. Moreover, the Blockchain-based solutions towards a secure Fog computing environment is presented and various research challenges and directions for future research are discussed. Full article
(This article belongs to the Special Issue Embedded IoT: System Design and Applications)
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13 pages, 510 KiB  
Article
Compact Implementation of ARIA on 16-Bit MSP430 and 32-Bit ARM Cortex-M3 Microcontrollers
by Hwajeong Seo, Hyunjun Kim, Kyoungbae Jang, Hyeokdong Kwon, Minjoo Sim, Gyeongju Song and Siwoo Uhm
Electronics 2021, 10(8), 908; https://doi.org/10.3390/electronics10080908 - 11 Apr 2021
Cited by 5 | Viewed by 2721
Abstract
In this paper, we propose the first ARIA block cipher on both MSP430 and Advanced RISC Machines (ARM) microcontrollers. To achieve the optimized ARIA implementation on target embedded processors, core operations of ARIA, such as substitute and diffusion layers, are carefully re-designed for [...] Read more.
In this paper, we propose the first ARIA block cipher on both MSP430 and Advanced RISC Machines (ARM) microcontrollers. To achieve the optimized ARIA implementation on target embedded processors, core operations of ARIA, such as substitute and diffusion layers, are carefully re-designed for both MSP430 (Texas Instruments, Dallas, TX, USA) and ARM Cortex-M3 microcontrollers (STMicroelectronics, Geneva, Switzerland). In particular, two bytes of input data in ARIA block cipher are concatenated to re-construct the 16-bit wise word. The 16-bit word-wise operation is executed at once with the 16-bit instruction to improve the performance for the 16-bit MSP430 microcontroller. This approach also optimizes the number of required registers, memory accesses, and operations to half numbers rather than 8-bit word wise implementations. For the ARM Cortex-M3 microcontroller, the 8×32 look-up table based ARIA block cipher implementation is further optimized with the novel memory access. The memory access is finely scheduled to fully utilize the 3-stage pipeline architecture of ARM Cortex-M3 microcontrollers. Furthermore, the counter (CTR) mode of operation is more optimized through pre-computation techniques than the electronic code book (ECB) mode of operation. Finally, proposed ARIA implementations on both low-end target microcontrollers (MSP430 and ARM Cortex-M3) achieved (209 and 96 for 128-bit security level, respectively), (241 and 111 for 192-bit security level, respectively), and (274 and 126 for 256-bit security level, respectively). Compared with previous works, the running timing on low-end target microcontrollers (MSP430 and ARM Cortex-M3) is improved by (92.20% and 10.09% for 128-bit security level, respectively), (92.26% and 10.87% for 192-bit security level, respectively), and (92.28% and 10.62% for 256-bit security level, respectively). The proposed ARIA–CTR implementation improved the performance by 6.6% and 4.0% compared to the proposed ARIA–ECB implementations for MSP430 and ARM Cortex-M3 microcontrollers, respectively. Full article
(This article belongs to the Special Issue Embedded IoT: System Design and Applications)
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41 pages, 2739 KiB  
Article
Design and Evaluation of a New Machine Learning Framework for IoT and Embedded Devices
by Gianluca Cornetta and Abdellah Touhafi
Electronics 2021, 10(5), 600; https://doi.org/10.3390/electronics10050600 - 4 Mar 2021
Cited by 13 | Viewed by 4681
Abstract
Low-cost, high-performance embedded devices are proliferating and a plethora of new platforms are available on the market. Some of them either have embedded GPUs or the possibility to be connected to external Machine Learning (ML) algorithm hardware accelerators. These enhanced hardware features enable [...] Read more.
Low-cost, high-performance embedded devices are proliferating and a plethora of new platforms are available on the market. Some of them either have embedded GPUs or the possibility to be connected to external Machine Learning (ML) algorithm hardware accelerators. These enhanced hardware features enable new applications in which AI-powered smart objects can effectively and pervasively run in real-time distributed ML algorithms, shifting part of the raw data analysis and processing from cloud or edge to the device itself. In such context, Artificial Intelligence (AI) can be considered as the backbone of the next generation of Internet of the Things (IoT) devices, which will no longer merely be data collectors and forwarders, but really “smart” devices with built-in data wrangling and data analysis features that leverage lightweight machine learning algorithms to make autonomous decisions on the field. This work thoroughly reviews and analyses the most popular ML algorithms, with particular emphasis on those that are more suitable to run on resource-constrained embedded devices. In addition, several machine learning algorithms have been built on top of a custom multi-dimensional array library. The designed framework has been evaluated and its performance stressed on Raspberry Pi III- and IV-embedded computers. Full article
(This article belongs to the Special Issue Embedded IoT: System Design and Applications)
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35 pages, 3596 KiB  
Article
M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera
by Jurgen Vandendriessche, Bruno da Silva, Lancelot Lhoest, An Braeken and Abdellah Touhafi
Electronics 2021, 10(3), 317; https://doi.org/10.3390/electronics10030317 - 29 Jan 2021
Cited by 6 | Viewed by 3625
Abstract
Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, when targeting real-time. Such a constraint limits the use [...] Read more.
Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, when targeting real-time. Such a constraint limits the use of acoustic cameras in many wireless sensor network applications (surveillance, industrial monitoring, etc.). In this paper, we propose a multi-mode System-on-Chip (SoC) Field-Programmable Gate Arrays (FPGA) architecture capable to satisfy the high computational demand while providing wireless communication for remote control and monitoring. This architecture produces real-time acoustic images of 240 × 180 resolution scalable to 640 × 480 by exploiting the multithreading capabilities of the hard-core processor. Furthermore, timing cost for different operational modes and for different resolutions are investigated to maintain a real time system under Wireless Sensor Networks constraints. Full article
(This article belongs to the Special Issue Embedded IoT: System Design and Applications)
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27 pages, 747 KiB  
Article
NVM-Shelf: Secure Hybrid Encryption with Less Flip for Non-Volatile Memory
by Thomas Haywood Dadzie, Jiwon Lee, Jihye Kim and Hyunok Oh
Electronics 2020, 9(8), 1304; https://doi.org/10.3390/electronics9081304 - 13 Aug 2020
Viewed by 3172
Abstract
The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the [...] Read more.
The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the NVM degrades the performance of the memory (high energy consumption, short lifetime), since typical encryption causes an avalanche effect while most NVMs suffer from the memory-write operation. In this paper, we propose NVM-shelf: Secure Hybrid Encryption with Less Flip (shelf) for Non-Volatile Memory (NVM), which is hybrid encryption to reduce the flip penalty. The main idea is that a stream cipher, such as block cipher CTR mode, is flip-tolerant when the keystream is reused. By modifying the CTR mode in AES block cipher, we let the keystream updated in a short period and reuse the keystream to achieve flip reduction while maintaining security against physical attacks. Since the CTR mode requires additional storage for the nonce, we classify write-intensive cache blocks and apply our CTR mode to the write-intensive blocks and apply the ECB mode for the rest of the blocks. To extend the cache-based NVM-shelf implementation toward SPM-based systems, we also propose an efficient compiler for SA-SPM: Security-Aware Scratch Pad Memory, which ensures the security of main memories in SPM-based embedded systems. Our compiler is the first approach to support full encryption of memory regions (i.e., stack, heap, code, and static variables) in an SPM-based system. By integrating the NVM-shelf framework to the SA-SPM compiler, we obtain the NVM-shelf implementation for both cache-based and SPM-based systems. The cache-based experiment shows that the NVM-shelf achieves encryption flip penalty less than 3%, and the SPM-based experiment shows that the NVM-shelf reduces the flip penalty by 31.8% compared to the whole encryption. Full article
(This article belongs to the Special Issue Embedded IoT: System Design and Applications)
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