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Electronics
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Mixed-Signal VLSI Design
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Mixed-Signal VLSI Design

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (20 January 2021) | Viewed by 17339

Special Issue Editors

Prof. Dr. Jeongjin Roh

E-Mail Website1 Website2
Guest Editor
Department of Electronics Engineering, Hanyang University, Ansan, Korea
Interests: mixed-signal VLSI design; over-sampling delta-sigma data converters; power management ICs; DC-DC converters
Prof. Dr. Byoungho Kim

E-Mail Website1 Website2
Guest Editor
Department of Electronics Engineering, Hanyang University, Ansan, Republic of Korea
Interests: reliable analog and mixed-signal circuits and systems; digitally-assisted analog circuits; low-distortion and low-noise circuits; high-speed I/O design for testing

Special Issue Information

Dear Colleagues,

This Special Issue focuses on mixed-signal VLSI design. Authors working in conventional analog and mixed-signal circuits, as well as in the new circuit areas such as AI neural circuits and sensor systems, are welcome to submit papers.

The high integration of system ICs have large silicon areas of digital blocks. However, the analog and mixed-signal blocks are still the bottleneck of the VLSI implementation due to nature of the analog design works.

This Special Issue tries to provide advances on analog and mixed-signal design techniques for mixed-signal VLSI design area.

Prof. Dr. Jeongjin Roh
Prof. Dr. Byoungho Kim
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Analog circuits
  • data converters
  • power management IC
  • low-power circuits
  • memory circuits
  • sensor circuits

Published Papers (3 papers)

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Research

9 pages, 3359 KiB  
Article
A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links
by Dongjun Park, Sungwook Choi and Jongsun Kim
Electronics 2021, 10(2), 177; https://doi.org/10.3390/electronics10020177 - 15 Jan 2021
Cited by 6 | Viewed by 3042
Abstract
An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining [...] Read more.
An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz. Full article
(This article belongs to the Special Issue Mixed-Signal VLSI Design)
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10 pages, 5712 KiB  
Article
A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS
by Woorham Bae, Sung-Yong Cho and Deog-Kyoon Jeong
Electronics 2021, 10(1), 68; https://doi.org/10.3390/electronics10010068 - 2 Jan 2021
Cited by 2 | Viewed by 3349
Abstract
This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To [...] Read more.
This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits. Full article
(This article belongs to the Special Issue Mixed-Signal VLSI Design)
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16 pages, 5969 KiB  
Article
A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR
by Heejae Hwang and Jongsun Kim
Electronics 2020, 9(7), 1113; https://doi.org/10.3390/electronics9071113 - 9 Jul 2020
Cited by 6 | Viewed by 9546
Abstract
A 100 Gb/s quad-lane SerDes receiver with a phase-interpolator (PI)-based quarter-rate all-digital clock and data recovery (CDR) is presented. The proposed CDR utilizes a multi-phase multiplying delay-locked loop (MDLL) to generate the eight-phase reference clocks, which achieves multi-phase frequency multiplication with a small [...] Read more.
A 100 Gb/s quad-lane SerDes receiver with a phase-interpolator (PI)-based quarter-rate all-digital clock and data recovery (CDR) is presented. The proposed CDR utilizes a multi-phase multiplying delay-locked loop (MDLL) to generate the eight-phase reference clocks, which achieves multi-phase frequency multiplication with a small area and less power consumption. The shared MDLL generates and distributes eight-phase clocks to each CDR. The proposed CDR uses a new initial phase tracker that uses a preamble to achieve a fast lock time of about 12 ns and to provide a constant output data sequence. The CDR utilizes quarter-rate 2x-oversampling architecture, and the PI controller is designed full custom to minimize the loop latency. To improve the dithering jitter performance of the recovered clock, the decimation factor of the CDR can be adjustable. Also, a new continuous-time linear equalizer (CTLE) receiver was adopted to reduce power consumption and achieved a data rate of 25 Gb/s/lane. The proposed SerDes receiver with a digital CDR is implemented in 40 nm CMOS technology. The 100 Gb/s four-channel SerDes receiver (4 CTLEs + 4 CDRs + MDLL) occupies an active area of only 0.351 mm2 and consumes 241.8 mW, which achieves a high energy efficiency of 2.418 pJ/bit. Full article
(This article belongs to the Special Issue Mixed-Signal VLSI Design)
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