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Circuits and Systems Advances in Near Threshold Computing
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Circuits and Systems Advances in Near Threshold Computing

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (30 September 2020) | Viewed by 22001

Printed Edition Available!
A printed edition of this Special Issue is available here.

Special Issue Editor

Prof. Dr. Sanghamitra Roy

E-Mail Website
Guest Editor
Electrical and Computer Engineering, Utah State University, Logan, UT 84322-4120, USA
Interests: AI hardware design; low power computing; computer systems
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

As a broad spectrum of applications shift to the edge of the network, near-threshold computing (NTC) is emerging as one of the promising low-power computing platforms. Despite showing a substantial promise of energy efficiency, NTC (gray silicon) operation is yet to see a wide-scale commercial adoption. This is because circuits and systems operating at NTC suffer from several problems, including increased sensitivity to process variation, reliability problems, performance degradation, and security vulnerabilities, to name a few. To realize its potential, we need designs, techniques, and solutions to overcome these challenges of NTC circuits and systems. To enable energy-proportional computing, future heterogeneous manycore systems may comprise cores and IP blocks operating at super threshold (STC), as well as near threshold (NTC).

The readers of this Special Issue will be able to familiarize themselves with the recent advances in electronics systems focusing on near-threshold computing. Original contributions, including but not limited to the following topics, are solicited:

  • Design automation/algorithms for NTC circuits and systems;
  • Architectural techniques for NTC;
  • Reliability or variation aware design of NTC circuits and systems;
  • Design of deep learning hardware for the edge at NTC;
  • Security vulnerabilities at NTC and countermeasures;
  • Recovering performance at NTC operation;
  • Design techniques for hybrid STC and NTC architectures.

Dr. Sanghamitra Roy
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Ultra-low Power
  • Near Threshold
  • Edge Computing
  • Low Power AI
  • IOT
  • Security

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Published Papers (5 papers)

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Research

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35 pages, 5162 KiB  
Article
Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data Paths
by Mehdi Tahoori and Mohammad Saber Golanbari
J. Low Power Electron. Appl. 2020, 10(4), 42; https://doi.org/10.3390/jlpea10040042 - 3 Dec 2020
Cited by 1 | Viewed by 2813
Abstract
Modern electronic devices are an indispensable part of our everyday life. A major enabler for such integration is the exponential increase of the computation capabilities as well as the drastic improvement in the energy efficiency over the last 50 years, commonly known as [...] Read more.
Modern electronic devices are an indispensable part of our everyday life. A major enabler for such integration is the exponential increase of the computation capabilities as well as the drastic improvement in the energy efficiency over the last 50 years, commonly known as Moore’s law. In this regard, the demand for energy-efficient digital circuits, especially for application domains such as the Internet of Things (IoT), has faced an enormous growth. Since the power consumption of a circuit highly depends on the supply voltage, aggressive supply voltage scaling to the near-threshold voltage region, also known as Near-Threshold Computing (NTC), is an effective way of increasing the energy efficiency of a circuit by an order of magnitude. However, NTC comes with specific challenges with respect to performance and reliability, which mandates new sets of design techniques to fully harness its potential. While techniques merely focused at one abstraction level, in particular circuit-level design, can have limited benefits, cross-layer approaches result in far better optimizations. This paper presents instruction multi-cycling and functional unit partitioning methods to improve energy efficiency and resiliency of functional units. The proposed methods significantly improve the circuit timing, and at the same time considerably limit leakage energy, by employing a combination of cross-layer techniques based on circuit redesign and code replacement techniques. Simulation results show that the proposed methods improve performance and energy efficiency of an Arithmetic Logic Unit by 19% and 43%, respectively. Furthermore, the improved performance of the optimized circuits can be traded to improving the reliability. Full article
(This article belongs to the Special Issue Circuits and Systems Advances in Near Threshold Computing)
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19 pages, 7164 KiB  
Article
Challenges and Opportunities in Near-Threshold DNN Accelerators around Timing Errors
by Pramesh Pandey, Noel Daniel Gundi, Prabal Basu, Tahmoures Shabanian, Mitchell Craig Patrick, Koushik Chakraborty and Sanghamitra Roy
J. Low Power Electron. Appl. 2020, 10(4), 33; https://doi.org/10.3390/jlpea10040033 - 16 Oct 2020
Cited by 6 | Viewed by 3719
Abstract
AI evolution is accelerating and Deep Neural Network (DNN) inference accelerators are at the forefront of ad hoc architectures that are evolving to support the immense throughput required for AI computation. However, much more energy efficient design paradigms are inevitable to realize the [...] Read more.
AI evolution is accelerating and Deep Neural Network (DNN) inference accelerators are at the forefront of ad hoc architectures that are evolving to support the immense throughput required for AI computation. However, much more energy efficient design paradigms are inevitable to realize the complete potential of AI evolution and curtail energy consumption. The Near-Threshold Computing (NTC) design paradigm can serve as the best candidate for providing the required energy efficiency. However, NTC operation is plagued with ample performance and reliability concerns arising from the timing errors. In this paper, we dive deep into DNN architecture to uncover some unique challenges and opportunities for operation in the NTC paradigm. By performing rigorous simulations in TPU systolic array, we reveal the severity of timing errors and its impact on inference accuracy at NTC. We analyze various attributes—such as data–delay relationship, delay disparity within arithmetic units, utilization pattern, hardware homogeneity, workload characteristics—and uncover unique localized and global techniques to deal with the timing errors in NTC. Full article
(This article belongs to the Special Issue Circuits and Systems Advances in Near Threshold Computing)
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8 pages, 667 KiB  
Article
Idleness-Aware Dynamic Power Mode Selection on the i.MX 7ULP IoT Edge Processor
by Alfio Di Mauro, Hamed Fatemi, Jose Pineda de Gyvez and Luca Benini
J. Low Power Electron. Appl. 2020, 10(2), 19; https://doi.org/10.3390/jlpea10020019 - 5 Jun 2020
Cited by 3 | Viewed by 3913
Abstract
Power management is a crucial concern in micro-controller platforms for the Internet of Things (IoT) edge. Many applications present a variable and difficult to predict workload profile, usually driven by external inputs. The dynamic tuning of power consumption to the application requirements is [...] Read more.
Power management is a crucial concern in micro-controller platforms for the Internet of Things (IoT) edge. Many applications present a variable and difficult to predict workload profile, usually driven by external inputs. The dynamic tuning of power consumption to the application requirements is indeed a viable approach to save energy. In this paper, we propose the implementation of a power management strategy for a novel low-cost low-power heterogeneous dual-core SoC for IoT edge fabricated in 28 nm FD-SOI technology. Ss with more complex power management policies implemented on high-end application processors, we propose a power management strategy where the power mode is dynamically selected to ensure user-specified target idleness. We demonstrate that the dynamic power mode selection introduced by our power manager allows achieving more than 43% power consumption reduction with respect to static worst-case power mode selection, without any significant penalty in the performance of a running application. Full article
(This article belongs to the Special Issue Circuits and Systems Advances in Near Threshold Computing)
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16 pages, 9874 KiB  
Article
Low-Power Embedded System for Gait Classification Using Neural Networks
by Francisco Luna-Perejón, Manuel Domínguez-Morales, Daniel Gutiérrez-Galán and Antón Civit-Balcells
J. Low Power Electron. Appl. 2020, 10(2), 14; https://doi.org/10.3390/jlpea10020014 - 1 May 2020
Cited by 15 | Viewed by 4896
Abstract
Abnormal foot postures can be measured during the march by plantar pressures in both dynamic and static conditions. These detections may prevent possible injuries to the lower limbs like fractures, ankle sprain or plantar fasciitis. This information can be obtained by an embedded [...] Read more.
Abnormal foot postures can be measured during the march by plantar pressures in both dynamic and static conditions. These detections may prevent possible injuries to the lower limbs like fractures, ankle sprain or plantar fasciitis. This information can be obtained by an embedded instrumented insole with pressure sensors and a low-power microcontroller. However, these sensors are placed in sparse locations inside the insole, so it is not easy to correlate manually its values with the gait type; that is why a machine learning system is needed. In this work, we analyse the feasibility of integrating a machine learning classifier inside a low-power embedded system in order to obtain information from the user’s gait in real-time and prevent future injuries. Moreover, we analyse the execution times, the power consumption and the model effectiveness. The machine learning classifier is trained using an acquired dataset of 3000+ steps from 6 different users. Results prove that this system provides an accuracy over 99% and the power consumption tests obtains a battery autonomy over 25 days. Full article
(This article belongs to the Special Issue Circuits and Systems Advances in Near Threshold Computing)
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Review

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23 pages, 12524 KiB  
Review
Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips
by Sriram Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, James Tschanz and Vivek De
J. Low Power Electron. Appl. 2020, 10(2), 16; https://doi.org/10.3390/jlpea10020016 - 14 May 2020
Cited by 5 | Viewed by 5711
Abstract
Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (VT) of the CMOS transistors. The improved silicon energy [...] Read more.
Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (VT) of the CMOS transistors. The improved silicon energy efficiency promises to fit more cores in a given power envelope. As a result, many-core Near-threshold computing (NTC) has emerged as an attractive paradigm. Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale microcontroller (MCU) designs. We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs. Evaluation results spanning Intel’s 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore’s law. Full article
(This article belongs to the Special Issue Circuits and Systems Advances in Near Threshold Computing)
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