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State-of-the-Art Memristor and Optoelectronic Memristor: Materials, Fabrication, Mechanism and Applications
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State-of-the-Art Memristor and Optoelectronic Memristor: Materials, Fabrication, Mechanism and Applications

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D：Materials and Processing".

Deadline for manuscript submissions: 20 August 2026 | Viewed by 3709

Special Issue Editors

Dr. Liyuan Long

E-Mail Website
Guest Editor
Micro-Electronics Research Institute and School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China
Interests: memristor; optoelectronic memristor; photosynapse; photodetector; photocarrier dynamics; 2D materials; heterostructure
Dr. Kangmin Leng

E-Mail Website
Guest Editor Assistant
Department of Physics, School of Physics and Materials Science, Nanchang University, Nanchang 330031, China
Interests: memristor; neuromorphic computing; optoelectronic semiconductor; optoelectronic detection

Special Issue Information

Dear Colleagues,

With the advent of an era of artificial intelligence and big data, traditional von Neumann architecture encounters a range of issues stemming from the physical separation of the memory and processor units, including energy consumption wall and memory wall. Memristors provide significant opportunities for overcoming such issues, through achieving in-memory computing or bio-inspired neuromorphic computing. In addition, newly emerging optoelectronic memristors further integrate sensory functionalities with memory and computing to develop advanced neuromorphic vision systems. The exploration and application of memristors and optoelectronic memristors have gained significant interest, as they will likely contribute to a revolution in information devices.

This Special Issue aims to compile original research and review papers that focus on advanced memristors and optoelectronic memristors with the above application potentials, especially those concerning materials and device design, large-scale integration fabrication technology, and mechanism understanding.

It is our pleasure to invite you to submit a manuscript to this Special Issue. Full papers, short communications, and reviews are welcome.

Dr. Liyuan Long
Guest Editor

Dr. Kangmin Leng
Guest Editor Assistant

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2100 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • memristor
  • optoelectronic memristor
  • synapse
  • neuromorphic computing
  • resistive switching
  • reconfigurable neuromorphic devices

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Published Papers (3 papers)

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Research

19 pages, 3434 KB  
Article
Influence of the Ge–Chalcogenide Active Layer on Electrical Conduction in Self-Directed Channel Memristors
by Ahmed A. Taher and Kristy A. Campbell
Micromachines 2026, 17(4), 403; https://doi.org/10.3390/mi17040403 - 26 Mar 2026
Viewed by 590
Abstract
The self-directed channel (SDC) class of memristors employs a multilayer architecture that is designed to enable robust Ag ion conduction, long cycling lifetime, and thermal stability. While several layers contribute to mechanical and chemical reliability, two layers primarily govern the electrical behavior: the [...] Read more.
The self-directed channel (SDC) class of memristors employs a multilayer architecture that is designed to enable robust Ag ion conduction, long cycling lifetime, and thermal stability. While several layers contribute to mechanical and chemical reliability, two layers primarily govern the electrical behavior: the amorphous Ge–chalcogenide active layer that is adjacent to the bottom electrode and the overlying metal–chalcogenide source layer. In this work, we investigate how the variation in the chalcogen species in these two layers influences switching characteristics in the pre-write regime, both in the pristine state and after a write/erase cycle, as well as the conduction behavior at room temperature. The devices were fabricated using Ge-rich chalcogenides containing O, S, Se, or Te, combined with SnS, SnSe, or Ag2Se metal–chalcogenide layers. The DC current-voltage measurements were analyzed using the standard linearization approaches to examine whether the transport behavior in the pre-write regime exhibits characteristics that are associated with Ohmic, Schottky, Poole–Frenkel, or space charge limited conduction. These measurements specifically probe the pre-write region of the I-V curve, where early ionic redistribution and structural rearrangement precede the abrupt formation of the conductive channels responsible for the resistive switching. The results show that the chalcogen composition strongly affects the threshold voltage, the resistance window, and the onset of field-enhanced transport, reflecting the differences in ionic distribution and channel formation dynamics. The results indicate that transport evolves with a bias and a compliance current, transitioning between regimes that are influenced by the interface injection and bulk-limited conduction, depending on the material stack. These findings clarify the role of chalcogen chemistry in governing the SDC switching behavior and provide guidance for the material selection in application-specific device design. Full article
(This article belongs to the Special Issue State-of-the-Art Memristor and Optoelectronic Memristor: Materials, Fabrication, Mechanism and Applications)
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10 pages, 1489 KB  
Article
Investigation of Resistive Switching in Cu/a-SiC/P+-Si Structure for Multilevel Nonvolatile Memory Applications
by Hehong Shao, Xiuwei Zhu, Xin Zhang, Wanting Zheng, Libing Zhang and Liangliang Chen
Micromachines 2026, 17(3), 364; https://doi.org/10.3390/mi17030364 - 17 Mar 2026
Viewed by 274
Abstract
Here, the resistive switching characteristics in a Cu/a-SiC/P+-Si sandwiched structure are systematically investigated for multilevel nonvolatile memory applications. The formation of Cu conducting filaments is believed to be the switching mechanism through temperature-dependent testing. Four distinguished resistance states can be achieved in the [...] Read more.
Here, the resistive switching characteristics in a Cu/a-SiC/P+-Si sandwiched structure are systematically investigated for multilevel nonvolatile memory applications. The formation of Cu conducting filaments is believed to be the switching mechanism through temperature-dependent testing. Four distinguished resistance states can be achieved in the Cu/a-SiC/P+-Si memory device through the modulation of suitable compliance current, which could be attributed to the formation of more conductive filaments when applying a higher compliance current during the Set process. In addition, these different resistance values can be easily distinguished and show reliable retention (~105 s), with the temperature even reaching 85 °C, which offers considerable potential for high-density RRAM applications. Full article
(This article belongs to the Special Issue State-of-the-Art Memristor and Optoelectronic Memristor: Materials, Fabrication, Mechanism and Applications)
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22 pages, 1159 KB  
Article
Compaction-Aware Flash Memory Remapping for Key–Value Stores
by Jialin Wang, Zhen Yang, Yi Fan and Yajuan Du
Micromachines 2025, 16(6), 699; https://doi.org/10.3390/mi16060699 - 11 Jun 2025
Viewed by 2345
Abstract
With the rapid development of big data and artificial intelligence, the demand for memory has exploded. As a key data structure in modern databases and distributed storage systems, the Log-Structured Merge Tree (LSM-tree) has been widely employed (such as LevelDB, RocksDB, etc.) in [...] Read more.
With the rapid development of big data and artificial intelligence, the demand for memory has exploded. As a key data structure in modern databases and distributed storage systems, the Log-Structured Merge Tree (LSM-tree) has been widely employed (such as LevelDB, RocksDB, etc.) in systems based on key–value pairs due to its efficient writing performance. In LSM-tree-based KV stores, typically deployed on systems with DRAM-SSD storage, the KV items are first organized into MemTable as buffer for SSTables in main memory. When the buffer size exceeds the threshold, MemTable is flushed to the SSD and reorganized into an SSTable, which is then passed down level by level through compaction. However, the compaction degrades write performance and SSD endurance due to significant write amplification. To address this issue, recent proposals have mostly focused on redesigning the structure of LSM trees. We discover the prevalence of unchanged data blocks (UDBs) in the LSM-tree compaction process, i.e., UDBs are written back to SSD the same as they are read into memory, which induces extra write amplification and degrades I/O performance. In this paper, we propose a KV store design in SSD, called RemapCom, to exploit remapping on these UDBs. RemapCom first identifies UDBs with a lightweight state machine integrated into the compaction merge process. In order to increase the ratio of UDBs, RemapCom further designs a UDB retention method to further develop the benefit of remapping. Moreover, we implement a prototype of RemapCom on LevelDB by providing two primitives for the remapping. Compared to the state of the art, the evaluation results demonstrate that RemapCom can reduce write amplification by up to 53% and improve write throughput by up to 30%. Full article
(This article belongs to the Special Issue State-of-the-Art Memristor and Optoelectronic Memristor: Materials, Fabrication, Mechanism and Applications)
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