Power Electronics Components Analysis

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E:Engineering and Technology".

Deadline for manuscript submissions: closed (20 May 2022) | Viewed by 1964

Special Issue Editor


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Guest Editor
Department of Automotive Engineering, Hanyang University, Seoul 04763, Korea
Interests: sensors; power electronics; electronics for vehicles; electronics reliability
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Special Issue Information

Dear Colleagues,

Power electronics are becoming more important in diverse applications including smart grids, renewable energies, power supplies, motor drives, and electrified vehicles. One key enabler is the advancement in components and analysis methods. Passive and active components facilitate high performance and reliability in power electronics circuit and control. Meanwhile, analysis methods incorporate electrical, magnetic, thermal, and mechanical domains. Therefore, component technologies and analysis methods are critical.

The topics interested in this special issue include but not limited to

  • Design, simulation, fabrication, or evaluation of power semiconductors and passive components;
  • Theoretical background, simulation, calibration, or comparison of analysis methods in electrical, magnetic, thermal, and/or mechanical domains;
  • Analysis considering multi-physical characteristics;
  • Sensors and measurement for power electronics.

Dr. Sang Won Yoon
Guest Editor

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Keywords

  • power electronics
  • power semiconductors
  • power devices

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Published Papers (1 paper)

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Research

9 pages, 4024 KiB  
Article
Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing
by Xiaoming Chen, Zhixuan Wang, Zhiyang Yu and Hsiang-Chen Chui
Micromachines 2022, 13(6), 853; https://doi.org/10.3390/mi13060853 - 29 May 2022
Viewed by 1678
Abstract
To improve the test accuracy and fault coverage of high-speed railway-related equipment boards, a time-varying pseudorandom disturbance algorithm based on the automatic test pattern generation technology in chip testing is proposed. The algorithm combines the pseudorandom pattern generation algorithm with the deterministic pattern [...] Read more.
To improve the test accuracy and fault coverage of high-speed railway-related equipment boards, a time-varying pseudorandom disturbance algorithm based on the automatic test pattern generation technology in chip testing is proposed. The algorithm combines the pseudorandom pattern generation algorithm with the deterministic pattern generation D algorithm. The existing pseudorandom number generation method usually requires random seeds to generate a series of pseudorandom numbers. In this algorithm, the system timer is used as the random seed to design a pseudorandom pattern generation method of time-varying seed to improve the randomness of pseudorandom pattern generation. In addition, in combination with the D algorithm, this work proposes a new switching logic between two algorithms by counting invalid pattern proportions. When the algorithm is applied to track a circuit netlist, the fault coverage can reach near 100%. However, the large-scale circuit fault coverage cannot easily reach 100%. The test results for the standard circuits of different sizes show that at the same time, compared with the independent pattern generation methods, the proposed algorithm can improve fault coverage by more than 50% and 30% and significantly improve the pattern generation efficiency. Therefore, it can be used perfectly in the subsequent construction of high-speed railway equipment test platforms. Full article
(This article belongs to the Special Issue Power Electronics Components Analysis)
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