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Micromachines
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Progress of Emerging Hardware Development for Post-Moore’s Computing, Volume II
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Progress of Emerging Hardware Development for Post-Moore’s Computing, Volume II

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A：Physics".

Deadline for manuscript submissions: closed (20 May 2022) | Viewed by 4750

Special Issue Editor

Dr. Yao-Feng Chang

E-Mail Website
Guest Editor
1. Microelectronics Research Center, The University of Texas, Austin, TX 78758, USA
2. Intel Corporation, Hillsboro, OR 97124, USA
Interests: memristor; memcomputing; neuromorphic systems; biomimic smart system
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The potential of machine learning and novel computing architecture can be exploited in the immediate future if more efficient hardware is developed that meets the special requirements of bio-inspired computing or unconventional computing schemes. In this area, nonvolatile memory technology using memristive devices (not restrained to any type of devices) in combination with neuromorphic systems and memcomputing (memristor + computing) is a promising way to achieve such hardware. The aim of this Special Issue is to provide a platform for interdisciplinary research into unconventional computing with emerging physical substrates. It will include studies in areas such as biological modeling, materials physics and analytics, memristive devices in miniature scale, neuromorphic circuits, memcomputing, advanced arithmetic operations for logic applications, and other novel computing concepts and circuit schemes for potential biomimic smart systems.

Dr. Yao-Feng Chang
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • memristor
  • memcomputing
  • neuromorphic systems
  • biomimic smart systems

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Related Special Issue

Published Papers (2 papers)

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Research

15 pages, 3864 KiB  
Article
A New NVM Device Driver for IoT Time Series Database
by Tao Cai, Yueming Ma, Peiyao Liu, Dejiao Niu and Lei Li
Micromachines 2022, 13(3), 385; https://doi.org/10.3390/mi13030385 - 27 Feb 2022
Cited by 1 | Viewed by 2217
Abstract
Numerous IoT devices in IoT systems collect data concurrently, which brings great challenges to IoT time series databases to store and manage these data. NVM device has high read–write speed compared with HDD and Flash-based SSD, and it is a possible way to [...] Read more.
Numerous IoT devices in IoT systems collect data concurrently, which brings great challenges to IoT time series databases to store and manage these data. NVM device has high read–write speed compared with HDD and Flash-based SSD, and it is a possible way to solve the storage bottleneck. However, there are some limitations that should be solved such as the overhead of the I/O software stack for NVM devices and the lack of optimization for IoT time series databases in a Linux environment. By analyzing the characteristics of IoT time series databases and NVM devices, we optimized the device driver of NVM in Linux and provide a new structure of a NVM device driver for IoT time series databases. A multi-queue management strategy and a lightweight load balance mechanism based on frequency were designed to improve the concurrency and efficiency of NVM device drivers. The prototype of an IoT-oriented NVM device driver named TS-PMEM was implemented based on an open-source NVM device driver. Six prototypes were used for evaluation with YCSB-TS, a test tool for time series databases. Results showed that TS-PMEM can improve write throughput of the time series databases by 18.6%, query throughput by 10.6%, and reduce the write latency by 8.3% and query latency by 6.4%. Full article
(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing, Volume II)
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13 pages, 4583 KiB  
Article
Synapse-Neuron-Aware Training Scheme of Defect-Tolerant Neural Networks with Defective Memristor Crossbars
by Jiyong An, Seokjin Oh, Tien Van Nguyen and Kyeong-Sik Min
Micromachines 2022, 13(2), 273; https://doi.org/10.3390/mi13020273 - 8 Feb 2022
Cited by 6 | Viewed by 2064
Abstract
To overcome the limitations of CMOS digital systems, emerging computing circuits such as memristor crossbars have been investigated as potential candidates for significantly increasing the speed and energy efficiency of next-generation computing systems, which are required for implementing future AI hardware. Unfortunately, manufacturing [...] Read more.
To overcome the limitations of CMOS digital systems, emerging computing circuits such as memristor crossbars have been investigated as potential candidates for significantly increasing the speed and energy efficiency of next-generation computing systems, which are required for implementing future AI hardware. Unfortunately, manufacturing yield still remains a serious challenge in adopting memristor-based computing systems due to the limitations of immature fabrication technology. To compensate for malfunction of neural networks caused from the fabrication-related defects, a new crossbar training scheme combining the synapse-aware with the neuron-aware together is proposed in this paper, for optimizing the defect map size and the neural network’s performance simultaneously. In the proposed scheme, the memristor crossbar’s columns are divided into 3 groups, which are the severely-defective, moderately-defective, and normal columns, respectively. Here, each group is trained according to the trade-off relationship between the neural network’s performance and the hardware overhead of defect-tolerant training. As a result of this group-based training method combining the neuron-aware with the synapse-aware, in this paper, the new scheme can be successful in improving the network’s performance better than both the synapse-aware and the neuron-aware while minimizing its hardware burden. For example, when testing the defect percentage = 10% with MNIST dataset, the proposed scheme outperforms the synapse-aware and the neuron-aware by 3.8% and 3.4% for the number of crossbar’s columns trained for synapse defects = 10 and 138 among 310, respectively, while maintaining the smaller memory size than the synapse-aware. When the trained columns = 138, the normalized memory size of the synapse-neuron-aware scheme can be smaller by 3.1% than the synapse-aware. Full article
(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing, Volume II)
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