Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
5.2
3.0
Journals
Micromachines
Special Issues
Micro/Nanoscale Semiconductor Memory Devices
share announcement

Micro/Nanoscale Semiconductor Memory Devices

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A：Physics".

Deadline for manuscript submissions: closed (31 December 2020) | Viewed by 9277

Special Issue Editor

Dr. Jiyong Woo

E-Mail Website
Guest Editor
ICT Creative Laboratory, Electronics and Telecommunications Research Institute, Daejeon 34129, Korea
Interests: emerging nonvolatile memories; neuromoprhic devices; nanoelectronic devices

Special Issue Information

Dear Colleagues,

The development of semiconductor memory devices has led to the era of the Internet of Things, where electronic devices are connected everywhere. In the early 2000s, geometric scaling of memory devices was one of the biggest driving forces for improving performance and increasing memory capacity to meet demands. However, due to the fundamental limitation of the silicon material, which is the main component of the devices, scaling has become a major challenge. To overcome this problem, approaches have been proposed that can be classified into two types: three-dimensional stacked memory and emerging resistive memory technologies.  

Therefore, the aim of this Special Issue is to provide research papers, short communications, and review articles that discuss and report on recent developments of semiconductor memory devices for possible applications such as high-density, storage-class, and neuromorphic computing. Topics of interest for this Special Issue include but are not limited to: (1) advanced fabrication process and novel architectures of silicon based memory (dynamic RAM and FLASH) and emerging resistive memories; (2) improvement of electrical and reliability performances of the memory devices; and (3) device design guideline of the memories for storage-class and neuromorphic computing.

Dr. Jiyong Woo
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Micro/nanoscale semiconductor memory devices
  • Resistive memories (e.g., RRAM, CBRAM, PCRAM, FeRAM, MRAM)
  • 3D-stacked memory (3D NAND) and cross-pint/bar memory
  • Storage-class memory and neuromorphic computing applications

Benefits of Publishing in a Special Issue

  • Ease of navigation: Grouping papers by topic helps scholars navigate broad scope journals more efficiently.
  • Greater discoverability: Special Issues support the reach and impact of scientific research. Articles in Special Issues are more discoverable and cited more frequently.
  • Expansion of research network: Special Issues facilitate connections among authors, fostering scientific collaborations.
  • External promotion: Articles in Special Issues are often promoted through the journal's social media, increasing their visibility.
  • e-Book format: Special Issues with more than 10 articles can be published as dedicated e-books, ensuring wide and rapid dissemination.

Further information on MDPI's Special Issue polices can be found here.

Published Papers (3 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

13 pages, 3065 KiB  
Article
Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM
by Songyi Yoo, Wookyung Sun and Hyungsoon Shin
Micromachines 2020, 11(11), 952; https://doi.org/10.3390/mi11110952 - 22 Oct 2020
Cited by 2 | Viewed by 1986
Abstract
A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge [...] Read more.
A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations. Full article
(This article belongs to the Special Issue Micro/Nanoscale Semiconductor Memory Devices)
►▼ Show Figures

Figure 1

10 pages, 3946 KiB  
Communication
Ferroelectric Switching in Trilayer Al2O3/HfZrOx/Al2O3 Structure
by Solyee Im, Seung-Youl Kang, Yeriaron Kim, Jeong Hun Kim, Jong-Pil Im, Sung-Min Yoon, Seung Eon Moon and Jiyong Woo
Micromachines 2020, 11(10), 910; https://doi.org/10.3390/mi11100910 - 30 Sep 2020
Cited by 8 | Viewed by 4471
Abstract
Since ferroelectricity has been observed in simple binary oxide material systems, it has attracted great interest in semiconductor research fields such as advanced logic transistors, non-volatile memories, and neuromorphic devices. The location in which the ferroelectric devices are implemented depends on the specific [...] Read more.
Since ferroelectricity has been observed in simple binary oxide material systems, it has attracted great interest in semiconductor research fields such as advanced logic transistors, non-volatile memories, and neuromorphic devices. The location in which the ferroelectric devices are implemented depends on the specific application, so the process constraints required for device fabrication may be different. In this study, we investigate the ferroelectric characteristics of Zr doped HfO2 layers treated at high temperatures. A single HfZrOx layer deposited by sputtering exhibits polarization switching after annealing at a temperature of 850 °C. However, the achieved ferroelectric properties are vulnerable to voltage stress and higher annealing temperature, resulting in switching instability. Therefore, we introduce an ultrathin 1-nm-thick Al2O3 layer at both interfaces of the HfZrOx. The trilayer Al2O3/HfZrOx/Al2O3 structure allows switching parameters such as remnant and saturation polarizations to be immune to sweeping voltage and pulse cycling. Our results reveal that the trilayer not only makes the ferroelectric phase involved in the switching free from pinning, but also preserves the phase even at high annealing temperature. Simultaneously, the ferroelectric switching can be improved by preventing leakage charge. Full article
(This article belongs to the Special Issue Micro/Nanoscale Semiconductor Memory Devices)
►▼ Show Figures

Figure 1

13 pages, 4252 KiB  
Article
Li-Doping Effect on Characteristics of ZnO Thin Films Resistive Random Access Memory
by Xiaofeng Zhao, Ping Song, Huiling Gai, Yi Li, Chunpeng Ai and Dianzhong Wen
Micromachines 2020, 11(10), 889; https://doi.org/10.3390/mi11100889 - 24 Sep 2020
Cited by 15 | Viewed by 2387
Abstract
In this study, a Pt/Ag/LZO/Pt resistive random access memory (RRAM), doped by different Li-doping concentrations was designed and fabricated by using a magnetron sputtering method. To determine how the Li-doping concentration affects the crystal lattice structure in the composite ZnO thin films, X-ray [...] Read more.
In this study, a Pt/Ag/LZO/Pt resistive random access memory (RRAM), doped by different Li-doping concentrations was designed and fabricated by using a magnetron sputtering method. To determine how the Li-doping concentration affects the crystal lattice structure in the composite ZnO thin films, X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) tests were carried out. The resistive switching behaviors of the resulting Pt/Ag/LZO/Pt devices, with different Li-doping contents, were studied under direct current (DC) and pulse voltages. The experimental results showed that compared with the devices doped with Li-8% and -10%, the ZnO based RRAM device doped by 5% Li-doping presented stable bipolar resistive switching behaviors with DC voltage, including a low switching voltage (<1.0 V), a high endurance (>103 cycles), long retention time (>104 s), and a large resistive switching window. In addition, quick switching between a high-resistance state (HRS) and a low-resistance state (LRS) was achieved at a pulse voltage. To investigate the resistive switching mechanism of the device, a conduction model was installed based on Ag conducting filament transmission. The study of the resulting Pt/Ag/LZO/Pt devices makes it possible to further improve the performance of RRAM devices. Full article
(This article belongs to the Special Issue Micro/Nanoscale Semiconductor Memory Devices)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-3
Back to TopTop