Search Results (81)

This paper presents an electrical thermometry method designed for kilowatt(kW)-level Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs). The dependence of the drain current on the channel temperature in GaN HEMTs is utilized as a means to measure the transient channel temperature. However, in kW-class GaN HEMTs, the gate current can reach tens of milliamperes, and trap-induced capture resulting from high doping concentrations can both influence the drain current. Through modifications to the gate bias circuit, the gate voltage self-biasing phenomenon caused by the gate current is mitigated. A theoretical model is derived to express the relationship between the drain current and the channel temperature. Experimentally, amplifier modules equipped with kW-level HEMTs were placed on thermal stages set at 45 °C, 60 °C, and 80 °C. The transient drain current curves and the corresponding channel temperature profiles were measured. The measured drain current versus channel temperature curves at different ambient temperatures were fitted and compared with the theoretically derived formula. The relative error between the measured and calculated drain current values at the same channel temperature was found to be within 1%. Full article

Micro-accelerometers are in high demand across many due to their compact size, low energy consumption, and excellent precision. Since gravity causes a large movement when the device is positioned vertically, measuring low gravitational acceleration is challenging. This study examines the intrinsic relationship between applied voltage levels and displacement in micro-accelerometers. The study introduces a novel design that integrates hybrid flexures, comprising both linear and angular configurations, with an out-of-plane overlap varying (OPOV) electrostatic actuation mechanism. This design aims to measure the micro-accelerometer’s movement and low frequency response. The proposed device with silicon material is designed and simulated using the IntelliSuite^® software, considering its small dimensions and 25 µm thickness. The norm value of 28.0916 μN from gravity’s reaction forces on the body, a resonant frequency of 179.668 Hz at the first desired mode, and a maximum stress of 24.7 MPa were obtained through the electro-mechanical analysis. A comparison of the proposed design was conducted with other configurations, measuring a frequency of 179.668 Hz at a minimum downward displacement of 7.69916 µm under the influence of gravity without electrostatic mechanisms. Following this, an electrostatic actuation mechanism was introduced to minimize displacement by applying different voltage levels, including 1 V, 1.5 V, and 3 V. At 3 V, a significant improvement in displacement reduction was observed compared to the other applied voltages. Additionally, dynamic and sensitivity analyses were carried out to validate the performance of the proposed design further. Full article

This paper presents an all-CMOS temperature sensor with low power consumption, wide temperature range, and high precision in a 180 nm CMOS process. Based on the I–V characteristics of MOSFETs in the subthreshold region and the negative exponential biasing current generated by the self-bootstrapped bias circuit, the proposed temperature-sensing front-end produces CTAT and PTAT voltages with high linearity and high sensitivity. The voltage-to-time converter (VTC) adopts a dual-comparator architecture to expand the time interval for improving resolution. The control logic unit is designed to count only within the time interval, eliminating interference during low-level periods and enhancing the accuracy of temperature measurement. The implemented sensor achieves an inaccuracy of −0.45 °C/+0.51 °C ($3\sigma$) from −40 °C to 130 °C after a two-point calibration with a resolution of 28 mK and consumes 503 nW at 27 °C when operating at 1 V, with an FoM of 7.9 pJ·K². Full article

This study provides an in-depth numerical simulation to optimize the structure of InGaN-based p-i-n single homojunction solar cells using SCAPS-1D software. The cell comprised a p-type ${\mathrm{I}\mathrm{n}}_{0.6}{\mathrm{G}\mathrm{a}}_{0.4}\mathrm{N}$ layer, an intrinsic i-type ${\mathrm{I}\mathrm{n}}_{0.52}{\mathrm{G}\mathrm{a}}_{0.48}\mathrm{N}$ layer, and an n-type ${\mathrm{I}\mathrm{n}}_{0.48}{\mathrm{G}\mathrm{a}}_{0.52}\mathrm{N}$ layer. A systematic parametric optimization methodology was employed, involving a sequential investigation of doping concentrations, layer thicknesses, and indium composition to identify the optimal device configuration. Initial optimization of doping levels established optimal concentrations of ${\mathrm{N}}_{\mathrm{d}}=1\times {10}^{16} {\mathrm{c}\mathrm{m}}^{-3}$ for the p-layer and ${\mathrm{N}}_{\mathrm{a}}=8\times {10}^{17} {\mathrm{c}\mathrm{m}}^{-3}$ for the n-layer. Subsequently, structural parameters were optimized through systematic variation of layer thicknesses while maintaining optimal doping concentrations. The comprehensive optimization culminated in the identification of an optimal device architecture featuring a p-type layer thickness of 0.2 μm, an intrinsic layer thickness of 0.4 μm, an n-type layer thickness of 0.06 μm, and an indium composition of x = 0.59 in the intrinsic layer. This fully optimized configuration achieved a maximum conversion efficiency (η) of 21.40%, a short-circuit current density (${\mathrm{J}}_{\mathrm{s}\mathrm{c}}$) of 28.2 mA/cm², and an open-circuit voltage ($V_{oc}$) of 0.874 V. The systematic optimization approach demonstrates the critical importance of simultaneous parameter optimization in achieving superior photovoltaic performance, with the final device configuration representing a 30.01% efficiency improvement compared to the baseline structure. These findings provide critical insights for improving the design and performance of InGaN-based solar cells, serving as a valuable reference for future experimental research. Full article

This study evaluates and compares centralized and distributed reactive power compensation strategies using Static Var Compensators (SVCs) to enhance the performance of a high-voltage transmission system in the Caribbean region of Colombia. The methodology comprises four stages: system characterization, assessment of the uncompensated condition under peak demand, definition of four SVC-based scenarios, and steady-state analysis through power flow simulations using DIgSILENT PowerFactory. SVCs were modeled as Thyristor-Controlled Devices (“SVC Type 1”) operating as PV nodes for voltage regulation. The evaluated scenarios include centralized SVCs at the Slack node, node N4, and node N20, as well as a distributed scheme across load nodes N51 to N55. Node selection was guided by power flow analysis, identifying voltage drops below 0.9 pu and overloads above 125%. Technically, the distributed strategy outperformed the centralized alternatives, reducing active power losses by 37.5%, reactive power exchange by 46.1%, and improving node voltages from 0.71 pu to values above 0.92 pu while requiring only 437 MVAr of compensation compared to 600 MVAr in centralized cases. Economically, the distributed configuration achieved the highest annual energy savings (36 GWh), the greatest financial return (USD 5.94 M/year), and the shortest payback period (7.4 years), highlighting its cost-effectiveness. This study’s novelty lies in its system-level comparison of SVC deployment strategies under real operating constraints. The results demonstrate that distributed compensation not only improves technical performance but also provides a financially viable solution for enhancing grid reliability in infrastructure-limited transmission systems. Full article

This paper presents the design, fabrication, calibration, and comprehensive characterization of a homemade tri-axial fluxgate magnetometer. The magnetometer, utilizing a ring core configuration, was developed to measure ultra-low magnetic fields with high sensitivity and stability. Critical stages from material selection to sensor geometry optimization are discussed in detail. A series of critical characterization processes were conducted, including zero-field voltage determination, scale factor calculation, resolution measurement, noise analysis, bias assessment, cross-field effect evaluation, temperature dependency, and bandwidth determination. The sensor demonstrated a minimum detectable magnetic field resolution of 2.2 nT with a noise level of 1.1 nT/√Hz at 1 Hz. Temperature dependency tests revealed minimal impact on sensor output with a maximum shift of 120 nT in the range of 60 °C, which was effectively compensated through calibration to less than 5 nT. Additionally, the paper introduces a model function in matrix form to relate the magnetometer’s output voltage to the measured magnetic field, incorporating temperature dependency and cross-field effects. This work highlights the importance of meticulous calibration and optimization in developing fluxgate magnetometers suitable for various applications, from space exploration to biomedical diagnostics. Full article

This paper presents a highly efficient, low-power, fully integrated neural stimulation circuit implemented using solely low-voltage devices. The circuit primarily consists of a high-voltage-generation circuit, an output driver circuit, and a constant-current source, designed and simulated using a 180 nm low-voltage CMOS process. The high-voltage-generation circuit utilizes a negative-voltage-generation module together with a series–parallel capacitor charge pump circuit, which effectively reduces the number of charge pump stages by three, and saves 29% of the area compared to a conventional charge pump circuit. A bootstrap clock generation circuit was utilized to generate the control signal to ensure that all transistors work within their voltage limit. To realize the high-voltage output driver circuit using low-voltage devices, a stacked transistor structure with deep N-well (DNW) devices was utilized. The four different output voltage levels from the high-voltage-generation circuit were utilized to generate a different voltage domain of control signals and bias voltage for the stacked transistors, making sure that all transistors work within their voltage limit. Simulation results show that the high-voltage-generation circuit can generate an output of up to 12.69 V from a 1.65 V low input voltage, with a maximum output current of 1 mA, achieving 74.9% efficiency. The overall efficiency of the neural stimulation circuit, including the high-voltage-generation circuit, output driver circuit and constant-current source, reaches 74% under the voltage-controlled stimulation (VCS) mode and 59.5% under the current-controlled stimulation (CCS) mode, whereas the standby static power consumption is as low as 66 pW. Full article

This work presents a current-controlled CMOS ring oscillator (CCRO) optimized for ultra-low-voltage applications in next-generation energy-constrained systems. Leveraging bulk voltage tuning in 22 nm FDSOI differential inverter stages, the topology enables frequency adjustment while operating MOSFETs in the subthreshold region—critical for minimizing power in sub-1 V environments. Simulations at 0.4 V supply demonstrate robust performance: a three-stage oscillator achieves a 537–800 MHz tuning range with bias current (I_BIAS) modulation from 30–130 nA, while a four-stage configuration spans 388–587 MHz. At 70 nA I_BIAS, the three-stage design delivers a nominal frequency of 666.8 MHz with just 10.23 µW power dissipation, underscoring its suitability for ultra-low-power IoT and biomedical applications. The oscillator’s linear frequency sensitivity (2.63 MHz/nA) allows precise, dynamic control over performance–power tradeoffs. To address diverse application needs, the design integrates three tunability mechanisms: programmable capacitor arrays for coarse frequency adjustments, configurable stage counts (three- or four-stage topologies), and supply voltage scaling. This multi-modal approach extends the operational range to 1 MHz–1 GHz, ensuring compatibility with low-speed sensor interfaces and high-speed edge-computing tasks. The CCRO’s subthreshold operation at 0.4 V—coupled with nanoampere-level current consumption—makes it uniquely suited for battery-less systems, wearable health monitors, and implantable medical devices where energy efficiency and adaptive clocking are paramount. By eliminating traditional voltage-controlled oscillators’ complexity, this topology offers a compact, scalable solution for emerging ultra-low-power technologies. Full article

In this paper, a better power optimizer architecture has been presented for PV strings, using a buck converter for each PV module to address partial shading conditions. The buck converter, though rarely used, is a natural converter for partial shading effects, as it converts the lower current of the shaded module to a higher output current. Usually, the advanced architecture activates the isolated converters (complex) of only shaded modules to draw extra current from the inverter’s DC-link node to maintain the string current ($I_{string}$). On the other hand, the conventional architecture activates converters (basic) of all modules regardless of their shading status. The proposed architecture contains a unique design with a new schematic layout, where it activates the buck converters of only shaded modules without drawing extra current from the DC-link. Thus, it combines the benefits of both architectures—selective converter operation, basic topology, high efficiency, low voltage stress, and low control complexity—while eliminating their drawbacks. The designing philosophy, control mechanism, and fundamental operation of the proposed architecture have been comprehensively explained and validated through simulation experiments. Three levels of shading are used to test the proposed architecture for string containing three PV modules: (1) a single module moderate (15%) shading level, (2) a single module strong (50%) shading level, and (3) a double module extreme (75%) and moderate (25%) shading levels. The results show a successful operation of the proposed architecture as it maintains a common $I_{string}$ for an inverter, where all the shaded modules remain active. The architecture exhibits an average efficiency over 97% under normal conditions. A comparative analysis of architectures has been presented to indicate the enhanced features of the proposed architecture. Full article

Type 1 diabetes (T1D) is a chronic metabolic disease defined by sustained hyperglycemia, leading to oxidative stress (OS) and systemic complications, including male subfertility. This study investigates the potential impact of T1D-induced OS on microtubule (MTs) dynamics and microtubule-associated proteins (MAPs) in the testis and spermatozoa (SPZ). Using a streptozotocin-induced T1D rat model, we examined the expression and localization of key MAPs, including Microtubule Affinity-Regulating Kinase 4 (MARK4), Microtubule-Associated Protein 1A (MAP1A), Dynein Light Chain LC8-Type 1 (DYNLL1), Prolyl Endopeptidase (PREP), and Radial Spoke Head 6 Homolog A (RSPH6A), alongside sperm functional parameters. Our findings showed that T1D significantly impaired the expression and distribution of these proteins, which may affect MTs organization and be associated with cytoskeletal disorganization, and impaired germ cell differentiation. Moreover, T1D rats exhibited reduced sperm count, viability, and motility, accompanied by increased DNA fragmentation and chromatin defects. Elevated levels of 4-hydroxy-2-nonenal (4-HNE), a marker of OS, were detected in SPZ, particularly in the acrosome and flagellum, correlating with mitochondrial dysfunction and ATP depletion. Additionally, decreased intracellular Ca²⁺ levels, downregulation of Cation Channel of Sperm (CATSPER) and Voltage-Dependent Anion Channel 3 (VDAC3), and altered tubulin acetylation, possibly due to imbalanced Alpha-Tubulin N-Acetyltransferase 1 (ATAT1) and Histone Deacetylase 6 (HDAC6) expression, were also associated with impaired sperm motility. The combined data suggest that T1D-induced OS is linked to disrupted MTs dynamics, which may contribute to testicular dysfunction and reduced sperm quality, potentially affecting male fertility. A better understanding of these associations may support the development of therapeutic strategies to mitigate the reproductive consequences of T1D and improve male fertility outcomes. Full article

The explosive demand for high-performance secondary power sources in artificial intelligence (AI) has brought significant opportunities for low-voltage GaN devices. This paper focuses on research on high-efficiency and high-reliability low-voltage p-GaN gate HEMTs with a gate–drain distance, L_GD, of 1 to 3 μm in our pilot line, manufactured on 6-inch Si using a CMOS-compatible process, with extraordinary wafer-level uniformity. Specifically, these fabricated p-GaN gate HEMTs with an L_GD of 1.5 μm demonstrate a blocking voltage of over 180 V and a high V_TH of 1.6 V and exhibit a low R_ON of 2.8 Ω·mm. It is found that device structure optimization can significantly enhance device reliability. That is, through the dedicated optimization of source field plate structure and interlayer dielectric (ILD) thickness, the dynamic ON-resistance, R_ON, degradation of devices with an L_GD of 1.5 µm was successfully suppressed from 60% to 20%, and the V_TH shift was significantly reduced from 1.1 to 0.5 V. Further, the devices also passed preliminary gate bias stress and high-voltage OFF-state stress tests, providing guidance for preparing high-performance, low-voltage p-GaN gate HEMTs in the future. Full article

This paper presents a highly stable and integrated silicon-based carrier with broad application prospects. Traditional 800 G optical modules employ architectures based on aluminum nitride (AlN) carriers with externally mounted capacitors. However, such AlN-based architectures suffer from issues including high process complexity, elevated costs, poor environmental temperature adaptability, and difficulties in systematic crosstalk optimization. To address these challenges, this study conducted research on coplanar waveguide (CPW) transmission line structure design and optimization, high-density capacitor design and process implementation, and multi-channel crosstalk suppression. Based on these investigations, a silicon-based integrated carrier was designed and fabricated, incorporating resistors, capacitors, high-speed signal lines, and preformed AuSn structures. Test results demonstrate that the CPW transmission line structures fabricated on the silicon carrier exhibit excellent radio frequency performance with transmission losses below 1 dB within 67 GHz. The developed high-density capacitor structure achieves a remarkable capacitance density of 26.83 nF/mm² and withstands voltages exceeding 24 V at 1 μA current, reaching state-of-the-art levels. This paper also proposes crosstalk reduction solutions including increased channel spacing, the addition of wave-absorbing materials, and the implementation of metal barriers. Experimental results confirm that the developed integrated carrier demonstrates outstanding performance and reliability in high-frequency communications and optoelectronic devices. Full article

Accurate parameter extraction for the Enz–Krummenacher–Vittoz (EKV) model is crucial for low-power integrated circuit design, especially in weak and moderate inversion regions. This work introduces a novel iterative subranging (ISR) technique for EKV model fitting, implemented in Python (version 3.10.12) using SciPy (version 1.10.1), NumPy (version 1.24.3), and Matplotlib (version 3.7.1). The core of the methodology is the Fitter class, which refines the threshold voltage ($V_{TH}$) by progressively narrowing the fitting range, controlled by the fit_range_parameter. This approach achieves a relative fitting error below 5% within a continuous interval of drain current, ensuring accurate parameter extraction in the region of interest while considering the full data range. Validation using SkyWater130 NMOS data demonstrated that the ISR method covers an inversion coefficient (IC) range from $1\times {10}^{-3}$ to nearly 50, showcasing its ability to accurately model device behavior across weak, moderate, and strong inversion. Compared to state-of-the-art EKV extraction methods, the ISR method exhibited at least a ×2 reduction in fitting error within the weak inversion region. More importantly, the ISR method is easily tunable by the designer in order to focus on specific current regions, where a greater accuracy is desired. This is a distinctive characteristic of the ISR method not present in any other extraction procedure. Moreover, the method demonstrated strong robustness against measurement noise, maintaining accuracy even with a 1 nA RMS noise level. This work provides a powerful and accessible tool for EKV model parameter extraction, enhancing reproducibility and accuracy in analog circuit design for low-power applications. Full article

The novel concept of reliable voltage balancing on N fast high-voltage (HV) transistors, connected in series, is verified by computer modeling/experimental testing. The essence of the concept is to transfer the balancing function from conventional snubbers, resistive dividers, varistors, etc., or sophisticated gate-side control techniques, to “individual” resistive loads (of transistors) connected to “individual” HV sources of power. The concept has been implemented in the recently patented architecture of HV rectangular pulse generators. The operation of any series-connected stack requires (1) synchronization of control actions on gates of all N transistors; (2) static HV balancing on all transistors in OFF states; and (3) dynamic HV balancing during ON↔OFF transients. The goals of the new design are to achieve an exceptionally high level of HV balancing in modes (2) and (3), as well as to simplify the process of configuring/customizing the circuit. Testing confirms that new generators exhibit minimal ripple during ON→OFF transients. Reliable operation with high-quality rectangular pulses is ensured even at a voltage slew rate of more than 100 kV/µs, while each transistor blocks a voltage close to the maximum value specified in its datasheet. The presented novelties are likely suitable for high-speed instrumentation. Full article

This paper introduces an analog differential optoelectronic receiver (ADOR) integrated with digital slicers for short-range LiDAR systems, consisting of a spatially modulated P⁺/N-well on-chip avalanche photodiode (APD), a cross-coupled differential transimpedance amplifier (CCD-TIA) with cross-coupled active loads, a continuous-time linear equalizer (CTLE), a limiting amplifier (LA), and dual digital slicers. A key feature is the integration of an additional on-chip dummy APD at the differential input node, which enables the proposed ADOR to outperform a traditional single-ended TIA in terms of common-mode noise rejection ratio. Also, the CCD-TIA utilizes cross-coupled PMOS-NMOS active loads not only to generate the symmetric output waveforms with maximized voltage swings, but also to provide wide bandwidth characteristics. The following CTLE extends the receiver bandwidth further, allowing the dual digital slicers to operate efficiently even at high sampling rates. The LA boosts the output amplitudes to suitable levels for the following slicers. Then, the inverter-based slicers with low power consumption and a small chip area produce digital outputs. The fabricated ADOR chip using a 180 nm CMOS process demonstrates a 20 dB dynamic range from 100 μA_pp to 1 mA_pp, 2 Gb/s data rate with a 490 fF APD capacitance, and 22.7 mW power consumption from a 1.8 V supply. Full article