Search Results (137)

The Logical Range is a mission-oriented, reconfigurable environment that integrates testing, training, and simulation by virtually connecting distributed systems. In such environments, task-processing devices often experience highly dynamic workloads due to varying task demands, leading to scheduling inefficiencies and increased latency. To address this, we propose GCSG, a hybrid load forecasting model tailored for Logical Range operations. GCSG transforms time-series device load data into image representations using Gramian Angular Field (GAF) encoding, extracts spatial features via a Convolutional Neural Network (CNN) enhanced with a Squeeze-and-Excitation network (SENet), and captures temporal dependencies using a Gated Recurrent Unit (GRU). Through the integration of spatial–temporal features, GCSG enables accurate load forecasting, supporting more efficient resource scheduling. Experiments show that GCSG achieves an $R^2$ of 0.86, MAE of 4.5, and MSE of 34, outperforming baseline models in terms of both accuracy and generalization. Full article

This study proposes a novel framework integrating long short-term memory (LSTM) networks with Bayesian optimization (BO) to address process–device co-optimization challenges in trench-gate metal–oxide–semiconductor field-effect transistor (MOSFET) manufacturing. Conventional TCAD simulations, while accurate, suffer from computational inefficiency in high-dimensional parameter spaces. To overcome this, an LSTM-based TCAD proxy model is developed, leveraging hierarchical temporal dependencies to predict electrical parameters (e.g., breakdown voltage, threshold voltage) with deviations below 3.5% compared to physical simulations. The model, validated on both N-type and P-type 20 V trench MOS devices, outperforms conventional RNN and GRU architectures, reducing average relative errors by 1.78% through its gated memory mechanism. A BO-driven inverse optimization methodology is further introduced to navigate trade-offs between conflicting objectives (e.g., minimizing on-resistance while maximizing breakdown voltage), achieving recipe predictions with a maximum deviation of 8.3% from experimental data. Validation via TCAD-simulated extrapolation tests and SEM metrology confirms the framework’s robustness under extended operating ranges (e.g., 0–40 V drain voltage) and dimensional tolerances within industrial specifications. The proposed approach establishes a scalable, data-driven paradigm for semiconductor manufacturing, effectively bridging TCAD simulations with production realities while minimizing empirical trial-and-error iterations. Full article

In recent years, missions requiring payload telemetry data transmission to ground stations have increasingly demanded a higher bandwidth. Traditional ranging techniques for spacecraft position determination often use a dedicated spectrum, reducing the available bandwidth for telemetry. To overcome this limitation, a transmission system capable of simultaneously sending high data-rate telemetry and ranging signals within the same bandwidth represents a key advancement for modern space missions, particularly Lagrangian science missions and planetary probes. To enhance the technological readiness of such a system, a hardware demonstrator has been developed using the AMD Xilinx (San Jose, CA, USA) ZCU111 Field Programmable Gate Array (FPGA), selected for its high-speed digital signal processing capabilities and integrated converters. The system, in this preliminary breadboarding phase, operates at a fixed telemetry rate of 4.25 Msym/s and a ranging rate of 2.987 Mchip/s, constrained within a 10 MHz bandwidth typical for science missions. Despite these limitations, tests demonstrated that integrating telemetry with Pseudo Noise (PN) Ranging introduces negligible implementation losses compared to telemetry-only transmission. The system also supports high-order modulations up to 64-APSK, improving spectral efficiency within the available bandwidth. Although some limitations have been found in the use of very high-order modulations, this prototype demonstrates the feasibility of integrating advanced coding techniques with PN Ranging. Full article

Using convolutional neural networks (CNNs) to recognize forest fires in complex outdoor environments is a hot research direction in the field of intelligent forest fire recognition. Due to the storage-intensive and computing-intensive characteristics of CNN algorithms, it is difficult to implement them at edge terminals with limited memory and computing resources. This paper uses a FPGA (Field-Programmable Gate Array) to accelerate CNNs to realize forest fire recognition in the field environment and solves the problem of the difficulty in giving consideration to the accuracy and speed of a forest fire recognition network in the implementation of edge terminal equipment. First, a simple seven-layer lightweight network, LightFireNet, is designed. The network is compressed using a knowledge distillation method and the classical network ResNet50 is used as the teacher network to supervise the learning of LightFireNet so that its accuracy rate reaches 97.60%. Compared with ResNet50, the scale of LightFireNet is significantly reduced. Its model parameter amount is 24 K and its calculation amount is 9.11 M, which are 0.1% and 1.2% of ResNet50, respectively. Secondly, the hardware acceleration circuit of LightFireNet is designed and implemented based on the FPGA development board ZYNQ Z7-Lite 7020. In order to further compress the network and speed up the forest fire recognition circuit, the following three methods are used to optimize the circuit: (1) the network convolution layer adopts a depthwise separable convolution structure; (2) the BN (batch normalization) layer is fused with the upper layer (or full connection layer); (3) half float or ap_fixed<16,6>-type data is used to express feature data and model parameters. After the circuit function is realized, the LightFireNet terminal circuit is obtained through the circuit parallel optimization method of loop tiling, ping-pong operation, and multi-channel data transmission. Finally, it is verified on the test dataset that the accuracy of the forest fire recognition of the FPGA edge terminal of the LightFireNet model is 96.70%, the recognition speed is 64 ms per frame, and the power consumption is 2.23 W. The results show that this paper has realized a low-power-consumption, high-accuracy, and fast forest fire recognition terminal, which can thus be better applied to forest fire monitoring. Full article

In the age of hardware accelerators, increasing pressure is applied on computer architects and hardware engineers to improve the balance between the cost and benefits of specialized computing units, in contrast to more general-purpose architectures. The first part of this study presents the embedded Streaming Hardware Accelerator (eSAC) architecture. This architecture can reduce the idle time of specialized logic. The remainder of this paper explores the integration of an eSAC into a Central Processing Unit (CPU) core embedded inside a System-on-Chip (SoC) design, using the AXI-Stream protocol specification. The three evaluated architectures are the Tightly Coupled Streaming, Protocol Adapter FIFO, and Direct Memory Access (DMA) Streaming architectures. When comparing the tightly coupled architecture with the one including the DMA, the experiments in this paper show an almost 3× decrease in frame latency when using the DMA. Nevertheless, this comes at the price of an increase in FPGA resource utilization as follows: LUT (2.5×), LUTRAM (3×), FF (3.4×), and BRAM (1.2×). Four different test scenarios were run for the DMA architecture, showcasing the best and worst practices for data organization. The evaluation results highlight that poor data organization can lead to a more than 7× increase in latency. The CPU model was selected as the newly released MicroBlaze-V softcore processor. The designs presented herein successfully operate on a popular low-cost Field-Programmable Gate Array (FPGA) development board at 100 MHz. Block diagrams, FPGA resource utilization, and latency metrics are presented. Finally, based on the evaluation results, possible improvements are discussed. Full article

In order to solve the testing and verification problems at the early development stage of a high-speed Maglev positioning and speed measurement system (MPSS), a hardware-in-the-loop (HIL) simulation platform is presented, which includes induction loops, transmitting antennas, a power driver unit, a simulator based on a field-programmable gate array (FPGA), a host computer, etc. This HIL simulation platform simulates the operation of a high-speed Maglev train and generates the related loop-induced signals to test the performance of a real ground signal processing unit (GSPU). Furthermore, an absolute position detection method based on Gray-coded loops is proposed to identify which Gray-coded period the train is in. A relative position detection method based on height compensation is also proposed to calculate the exact position of the train in a Gray-coded period. The experimental results show that the positioning error is only 2.58 mm, and the speed error is 6.34 km/h even in the 600 km/h condition. The proposed HIL platform also effectively simulates the three kinds of operation modes of high-speed Maglev trains, which verifies the effectiveness and practicality of the HIL simulation strategy. This provides favorable conditions for the development and early validation of high-speed MPSS. Full article

In this work, floating-gate organic field-effect transistor memory using the n-type semiconductor poly-{[N,N′-bis(2-octyldodecyl) naphthalene-1,4,5,8-bis (dicarbo- ximide)-2,6-dili]-alt-5,5′-(2,2′-bithiophene)} (N2200) as a charge-trapping layer is presented. With the assistance of a technology computer-aided design (TCAD) tool (Silvaco-Atlas), the storage characteristics of the device are numerically simulated by using the carrier injection and Fower–Nordheim (FN) tunneling models. The shift in the transfer characteristic curves and the charge-trapping mechanism after programming/erasing (P/E) operations under different P/E voltages and different pulse operation times are discussed. The impacts of different thicknesses of the tunneling layer on storage characteristics are also analyzed. The results show that the memory window with a tunneling layer thickness of 8 nm is 16.1 V under the P/E voltage of ±45 V, 5 s. After 1000 cycle tests, the memory shows good fatigue resistance, and the read current on/off ratio reaches 10³. Full article

In complex electromagnetic environments, such as substations, converter stations in power systems, and the compartments of aircraft, trains, and automobiles, electromagnetic immunity testing is crucial. It requires that the electric field sensor has features such as a large dynamic measurement range (amplitude from hundreds of V/m to tens of kV/m), a fast response speed (response time in the order of nanoseconds or sub-nanoseconds), a wide test bandwidth (DC to 1 GHz even above), miniaturization, and robustness to strong electromagnetic interference. This paper introduces a multi-channel, ultra-wideband transient electric field measurement system. The system’s analog bandwidth covers the spectrum from DC and a power frequency of 50 Hz to partial discharge signals, from DC to 1.65 GHz, with a storage depth of 2 GB (expandable). It overcomes issues related to the instability, insufficient bandwidth, and lack of accuracy of optical fibers in analog signal transmission by using front-end digital sampling based on field-programmable gate array (FPGA) technology and transmitting digital signals via optical fibers. This approach is effectively applicable to measurements in strong electromagnetic environments. Additionally, the system can simultaneously access four channels of signals, with synchronization timing reaching 300 picoseconds, can be connected to voltage and current sensors simultaneously, and the front-end sensor can be flexibly replaced. The performance of the system is verified by means of a disconnect switch operation and steady state test in an HVDC converter station. It is effectively applicable in scenarios such as the online monitoring of transient electromagnetic environments in high-voltage power equipment, fault diagnosis, and the precise localization of radiation sources such as partial discharge or intentional electromagnetic interference (IEMI). Full article

In response to the need for deploying the YOLOv4-Tiny model on resource-constrained Field-Programmable Gate Array (FPGA) platforms for rapid inference, this study proposes a general optimization acceleration strategy and method aimed at achieving fast inference for object detection networks. This approach centers on the synergistic effect of several key strategies: a refined resource management strategy that dynamically adjusts FPGA hardware resource allocation based on the network architecture; a dynamic dual-buffering strategy that maximizes the parallelism of data computation and transmission; an interface access latency pre-configuration strategy that effectively improves data throughput; and quantization operations for dynamic bit width tuning of model parameters and cached variables. Experimental results on the ZYNQ7020 platform demonstrate that this accelerator operates at a frequency of 200 MHz, achieving an average computing performance of 36.97 Giga Operations Per Second (GOPS) with an energy efficiency of 8.82 Giga Operations Per Second per Watt (GOPS/W). Testing with a metal surface defect dataset maintains an accuracy of approximately 90% per image, while reducing the inference delay per frame to 185 ms, representing a 52.2% improvement in inference speed. Compared to other FPGA accelerator designs, the accelerator design strategies and methods proposed in this study showcase significant enhancements in average computing performance, energy efficiency, and inference latency. Full article

Accurately and precisely obtaining field crop information is crucial for evaluating the effectiveness of rice transplanter operations. However, the working environment of rice transplanters in paddy fields is complex, and data obtained solely from GPS devices installed on agricultural machinery cannot directly reflect the specific information of seedlings, making it difficult to accurately evaluate the quality of rice transplanter operations. This study proposes a CAD-UNet model for detecting rice seedling rows based on low altitude orthorectified remote sensing images, and uses evaluation indicators such as straightness and parallelism of seedling rows to evaluate the operation quality of the rice transplanter. We have introduced convolutional block attention module (CBAM) and attention gate (AG) modules on the basis of the original UNet network, which can merge multiple feature maps or information flows together, helping the model better select key areas or features of seedling rows in the image, thereby improving the understanding of image content and task execution performance. In addition, in response to the characteristics of dense and diverse shapes of seedling rows, this study attempts to integrate deformable convolutional network version 2 (DCNv2) into the UNet network, replacing the original standard square convolution, making the sampling receptive field closer to the shape of the seedling rows and more suitable for capturing various shapes and scales of seedling row features, further improving the performance and generalization ability of the model. Different semantic segmentation models are trained and tested using low altitude high-resolution images of drones, and compared. The experimental results indicate that CAD-UNet provides excellent results, with precision, recall, and F1-score reaching 91.14%, 87.96%, and 89.52%, respectively, all of which are superior to other models. The evaluation results of the rice transplanter’s operation effectiveness show that the minimum and maximum straightnessof each seedling row are 4.62 and 13.66 cm, respectively, and the minimum and maximum parallelismbetween adjacent seedling rows are 5.16 and 23.34 cm, respectively. These indicators directly reflect the distribution of rice seedlings in the field, proving that the proposed method can quantitatively evaluate the field operation quality of the transplanter. The method proposed in this study can be applied to decision-making models for farmland crop management, which can help improve the efficiency and sustainability of agricultural operations. Full article

Field Programmable Gate Arrays (FPGAs), with their wide portfolio of configurable resources such as Look-Up Tables (LUTs), Block Random Access Memory (BRAM), and Digital Signal Processing (DSP) blocks, are the best option for custom hardware designs. Their low power consumption and cost-effectiveness give them an advantage over Graphics Processing Units (GPUs) and Central Processing Units (CPUs) in providing efficient accelerator solutions for compute-intensive Convolutional Neural Network (CNN) models. CNN accelerators are dedicated hardware modules capable of performing compute operations such as convolution, activation, normalization, and pooling with minimal intervention from a host. Designing accelerators for deeper CNN models requires FPGAs with vast resources, which impact its advantages in terms of power and price. In this paper, we propose the VCONV Intellectual Property (IP), an efficient and scalable CNN accelerator architecture for applications where power and cost are constraints. VCONV, with its configurable design, can be deployed across multiple smaller FPGAs instead of a single large FPGA to provide better control over cost and parallel processing. VCONV can be deployed across heterogeneous FPGAs, depending on the performance requirements of each layer. The IP’s performance can be evaluated using embedded monitors to ensure that the accelerator is configured to achieve the best performance. VCONV can be configured for data type format, convolution engine (CE) and convolution unit (CU) configurations, as well as the sequence of operations based on the CNN model and layer. VCONV can be interfaced through the Advanced Peripheral Bus (APB) for configuration and the Advanced eXtensible Interface (AXI) stream for data transfers. The IP was implemented and validated on the Avnet Zedboard and tested on the first layer of AlexNet, VGG16, and ResNet18 with multiple CE configurations, demonstrating 100% performance from MAC units with no idle time. We also synthesized multiple VCONV instances required for AlexNet, achieving the lowest BRAM utilization of just 1.64 Mb and deriving a performance of 56GOPs. Full article

Using chaos for communication can provide more robust channel security, covert transmission, and inherent support for spread-spectrum modulation. Although numerous studies have explored this technology, its practical deployment remains limited due to substantial hardware demands, complex signal processing, and a lack of efficient modulation methods for chaotic signals. In this study, a novel chaotic digital communication system is proposed and studied. A prototype of a frequency-modulated antipodal chaos shift keying (FM-ACSK) system is implemented on an Intel Cyclone V field-programmable gate array (FPGA) along with a complete mathematical model using Matlab R2022a Simulink software. Using FPGAs to implement chaotic oscillators avoids analog system problems such as component drift and high thermal instability while providing determined system parameters, rapid prototyping, and high throughput. The employment of FM over a chaotic modulation layer provides a passband operation (currently at an intermediate frequency of 10.7 MHz) while adding the benefits of carrier frequency offset robustness and constant signal envelope. Within this study, the robustness of FM-ACSK to white noise in the channel was evaluated using bit error rate, which was tested through hardware experiments and simulations. The results show the feasibility and potential performance limitations of this approach to chaotic communication system design. Full article

Silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) are a future trend in traction inverters in electric vehicles (EVs), and their thermal safety is crucial. Temperature-sensitive electrical parameters’ (TSEPs) indirect detection normally requires additional circuits, which can interfere with the system and increase costs, thereby limiting applications. Therefore, there is still a lack of cost-effective and sensorless thermal monitoring techniques. This paper proposes a high-efficiency datasheet-driven method for sensorless estimation utilizing the third-quadrant characteristics of MOSFETs. Without changing the existing hardware, the closure degree of MOS channels is controlled through a dual-gate bias (DGB) strategy to achieve reverse conduction in different patterns with body diodes. This method introduces a MOSFET operating current that TSEPs are equally sensitive to into the two-argument function, improving the complexity and accuracy. A two-stage current pulse is used to decouple the motor effect in various conduction modes, and the TSEP-combined temperature function is built dynamically by substituting the currents. Then, the junction temperature is estimated by the measured bus voltage and current. Its effectiveness was verified through spice model simulation and a test bench with a three-phase inverter. The average relative estimation error of the proposed method is below $7.2\%$ in centigrade. Full article

Visible Light Communication (VLC) is a cutting-edge transmission technique where data is sent by modulating light intensity. Manchester On–Off Keying (OOK) is among the most used modulation techniques in VLC and is normed by IEEE 802.15.7 standard for wireless networks. Various Manchester decoder schemes are documented in the literature, often leveraging minimal two-level analog-to-digital converters followed by straightforward digital logic. These methods often compromise performance for simplicity. However, the VLC applications in fields like automotive and/or aerospace require the maximum performance in terms of bit error rate (BER) with respect to Signal-to-Noise Ratio (SNR), together with a real-time low-latency implementation. In this work, we introduce a high-performance Manchester decoder and detail its implementation in a Field Programmable Gate Array (FPGA). The decoder operates by acquiring a fully resolved signal (12-bit resolution) and by calculating the phase of the transmitted bit. Additionally, the proposed decoder achieves and maintains synchronization with the incoming signal, tolerating frequency shifts and jitter up to 1%. The Manchester decoder was tested in a VLC system with automotive-certified headlamps, realizing an IEEE 802.15.7-compliant link at 100 kb/s. The proposed decoder ensures a BER below 10⁻² for SNR > −12 dB and, compared to a standard decoder, achieves the same BER when the input signal has an SNR of 10 dB lower. Full article

In this paper, we propose a method to enhance the performance of a random number generator (RNG) that exploits ring oscillators (ROs). Our approach employs additional phase detectors to extract more entropy; thus, RNG uses fewer resources to produce bit sequences that pass all statistical tests proposed by National Institute of Standards and Technology (NIST). Generating a specified number of bits is on-demand, eliminating the need for continuous RNG operation. This feature enhances the security of the produced sequences, as eavesdroppers are unable to observe the continuous random bit generation process, such as through monitoring power lines. Furthermore, our research demonstrates that the proposed RNG’s perfect properties remain unaffected by the manufacturer of the field-programmable gate arrays (FPGAs) used for implementation. This independence ensures the RNG’s reliability and consistency across various FPGA manufacturers. Additionally, we highlight that the tests recommended by the NIST may prove insufficient in assessing the randomness of the output bit streams produced by RO-based RNGs. Full article