Search Results (270)

We propose a terahertz (THz) antenna-coupled wire-channel field-effect transistor—modified EdgeFET (m-EdgeFET), formed by combining single-gate FinFET and dual-side-gate EdgeFET concepts, which is used for THz detection. The proposed hybrid design was implemented on AlGaN/GaN high-electron-mobility transistor (HEMT) structures, demonstrating distinct response characteristics under 150 GHz and 300 GHz radiation at room temperature. The responsivity dependence on the channel length was determined, revealing that the peak responsivity reached up to 6.5 V/W at a gate voltage of −3 V, i.e., at a gate bias that is an order lower in magnitude than that required for EdgeFET to reach the maximum response. Meanwhile, the gate leakage current decreased by an order of magnitude (to about 1 nA) compared to a FinFET with similar geometry. The proposed geometry was shown to operate in two regimes: source-drain coupling (SD) and gate coupling (GG) of THz radiation with the transistor wire channel. The results confirm that the m-EdgeFET design is suitable for electrically controlled and fast THz detection. Full article

In this study, enhancement- and depletion-mode (E- and D-mode) GaN-based 120 nm-wide fin-gated multiple nanochannel metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) were manufactured on the epitaxial Al_0.83In_0.17N/GaN/Al_0.18Ga_0.82N/GaN two-dimensional electron gas (2DEG) channel layers grown on Si substrates using a metal-organic chemical vapor deposition system. The oxide layer grown directly by the photoelectrochemical oxidation method was used as the gate oxide layer in D-mode MOS-HEMTs. Furthermore, E-mode MOS-HEMTs used ferroelectric stacked LiNbO₃/HfO₂/Al₂O₃ layers as the gate oxide layers. The 120 nm-wide multiple nanochannels and various-length source field plates (SFPs) were fabricated and incorporated into monolithic complementary MOS-HEMTs (CMOS-HEMTs) consisting of D- and E-mode MOS-HEMTs. The resulting monolithic unskewed inverter was achieved by modulating the drain-source current of the D-mode MOS-HEMTs. The noise low margin of 2.03 V and noise high margin of 2.10 V of the unskewed monolithic inverter were obtained. From the dynamic experimental results, the rising time and falling time of the unskewed monolithic inverter were 4.9 μs and 3.2 μs, respectively. The breakdown voltage could be improved by incorporating an SFP. When the SFP edge was located at the center between the gate electrode and the drain electrode, the maximum breakdown voltage of 855 V was obtained. Full article

This paper presents a novel Double Buried-Window Junctionless Field-Effect Transistor (DBW-FET) designed for high-sensitivity, label-free biosensing applications. The proposed device integrates two buried windows, one N-type and one P-type, beneath the active channel within the buried oxide layer, along with two nanocavities serving as biomolecular recognition sites. The dual buried windows form two depletion regions that enhance electrostatic coupling, suppress short-channel effects, and improve biomolecular sensitivity. Numerical simulations using Silvaco TCAD Atlas were performed to investigate device performance under various biomolecular binding conditions. Results show that the DBW-FET exhibits higher drain current, lower subthreshold swing, and improved sensitivity compared with a conventional junctionless FET (C-FET). Furthermore, a machine-learning-assisted optimization framework employing Gaussian Process Regression (GPR) and Bayesian Optimization (BO) was implemented to identify optimal buried window parameters. The optimized design achieved a 20–25% improvement in current sensitivity while maintaining low leakage. These findings demonstrate that the proposed DBW-FET offers a promising and Complementary Metal-Oxide-Semiconductor (CMOS)-compatible architecture for next-generation nanoscale biosensors. Full article

Channel length modulation (CLM) in indium gallium zinc oxide (IGZO) thin film transistors (TFTs) reduces the output resistance (r_o) in the saturation regime. It also degrades current driving accuracy for active matrix organic light emitting diode (AMOLED) backplanes. For top gate, self-aligned devices with nominal channel lengths of 5–15 μm, transmission line method (TLM) analysis yields an effective channel length reduction (ΔL) of about 1.8 μm. This result is consistent with lateral hydrogen redistribution from the self-aligned source/drain (S/D) process. At L = 5 μm, the conventional TFT exhibits r_o = 13.5 ± 2.5 MΩ and an Early voltage (V_A) = 56.1 ± 10.4 V (n = 5). We propose a source connected bottom gate (SCBG) structure that electrostatically stabilizes the pinch-off region and suppresses CLM. The SCBG TFT increases r_o to 475 ± 52 MΩ and V_A to 1159 ± 173 V at L = 5 μm (n = 5), while maintaining normal transfer characteristics. Two-dimensional device simulations reproduce the trend and show that the drain-bias-induced pinch-off shift is reduced, with d(ΔL)/dV_DS decreasing from 0.027 to 0.012 μm/V (about 55%). These results indicate that the SCBG approach is effective for enhancing current saturation in short channel IGZO TFTs for high-resolution AMOLED applications. Full article

This work presents an advanced electro-physical model for hydrogenated amorphous silicon (a-Si:H) Junction Field Effect Transistors (JFETs) to enable the design of devices with energy-efficient analog interface building blocks for Lab-on-Chip (LoC) systems. The presence of this device can support monolithic integration with thin-film sensors and circuit-level design through a validated compact formulation. The model accurately describes the behavior of a-Si:H JFETs addressing key physical phenomena, such as the channel thickness dependence on the gate-source voltage when the channel approaches full depletion. A comprehensive framework was developed, integrating experimental data and mathematical refinements to ensure robust predictions of JFET performance across operating regimes, including the transition toward full depletion and the associated current-limiting behavior. The model was validated through a broad set of fabricated devices, demonstrating excellent agreement with experimental data in both the linear and saturation regions. Specifically, the validation was carried out at 25 °C on 15 fabricated JFET configurations (12 nominally identical devices per configuration), using the mean characteristics of 9 devices with standard-deviation error bars. In the investigated bias range, the devices operate in a sub-µA regime (up to several hundred nA), which naturally supports µW-level dissipation for low-power interfaces. This work provides a compact, experimentally validated modeling basis for the design and optimization of a-Si:H JFET-based LoC front-end/readout circuits within technology-constrained and energy-efficient operating conditions. Full article

We investigated the radio frequency (RF) performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon carbide substrates, featuring two distinct T-shaped gate structures. A comparative analysis between a silicon nitride (SiN_x)-passivated T-gate and a floating T-gate design reveals significant differences in parasitic capacitance and high-frequency behavior. The floating gate structure effectively reduces fringe capacitance, resulting in improved cut-off frequency (f_T) and maximum oscillation frequency (f_max), achieving f_T = 82.7 GHz and f_max = 80.2 GHz, respectively. These enhancements underscore the critical importance of optimizing gate structures to advance GaN-based HEMTs for high-speed and high-power applications. The findings provide valuable insights for the design of future RF and millimeter-wave (mm-wave) devices. Full article

We extend our compact physics model (CPM) for hot-carrier degradation (HCD) to cover the impact of ambient temperature on HCD. Three components of this impact are taken into account. First, variations in temperature perturb carrier transport. Second, the thermal component of Si-H bond rupture becomes more prominent at elevated temperatures. Third, vibrational lifetime of the bond decreases with temperature. While the first and the third mechanisms impede HCD, the second one accelerates this detrimental phenomenon. The aforementioned mechanisms are consolidated in our extended CPM, which was verified against experimental data acquired from foundry quality n-channel transistors with a gate length of 28 nm. For model validation, we use experimental data recorded using four combinations of gate and drain voltages and across a broad temperature range of 150–300 K. We demonstrate that the extended CPM is capable of reproducing measured degradation $\Delta I_{\mathrm{d},\mathrm{lin}}\left(t\right)$ (normalized change of the linear drain current with stress time) traces with good accuracy over a broad temperature range. Full article

Gallium nitride (GaN)-based high electron mobility transistors (HEMTs) are pivotal for next-generation power-switching applications, but their reliability under high electric fields remains constrained by lattice mismatches and high dislocation densities in heterogeneous substrates. Herein, we systematically investigate the electrical performance and reliability of GaN-on-GaN HEMTs in comparison to conventional GaN-on-SiC HEMTs via DC characterization, reverse gate step stress, off-state drain step stress, and on-state electrical stress tests. Notably, the homogeneous epitaxial structure of GaN-on-GaN devices reduces dislocation density by 83.3% and minimizes initial tensile stress, which is obtained through HRXRD and Raman spectroscopy. The GaN-on-GaN HEMTs exhibit a record BFOM of 950 MW/cm², enabled by a low specific on-resistance (R_ON-SP) of 0.6 mΩ·cm² and a high breakdown voltage (BV) of 755 V. They withstand gate voltages up to −200 V and drain voltages beyond 200 V without significant degradation, whereas GaN-on-SiC HEMTs fail at −95 V (reverse gate stress) and 150 V (off-state drain stress). The reduced dislocation density suppresses leakage channels and defect-induced degradation, as confirmed by post-stress Schottky/transfer characteristics and Frenkel–Poole emission analysis. These findings establish GaN-on-GaN technology as a transformative solution for power electronics, offering a unique combination of high efficiency and long-term stability for demanding high-voltage applications. Full article

This work presents the simulation and design of 3C-SiC power MOSFETs, focusing on critical parameters including avalanche impact ionization, breakdown voltage, bulk and channel mobilities, and the trade-off between on-resistance and breakdown voltage. The device design is carried out by evaluating the blocking voltage of scaled structures as a function of the blocking layer’s doping concentration. To mitigate edge-effect breakdown at the p-well/n-drift interface, a step-profile doping strategy is employed. Multiple transistor layouts with varying pitches are developed using a commercially available device simulator. Results are benchmarked against a one-dimensional analytical model, validating the on-state resistance, current–voltage behavior, and overall accuracy of the simulation approach. For the selected material properties, simulations predict that a 600 V 3C-SiC MOSFET achieves an on-state resistance of 0.8 mΩ·cm², corresponding to a 7 μm drift layer with a doping concentration of 1 × 10¹⁶ cm⁻³. Full article

NMOSFET, whose gate is on the top of the n-p-n junction with gate oxide in between, is called the n-channel transistor. This bipolar junction underneath the gate oxide may provide an n-n-n-conductive channel as the gate is applied with a positive bias over the threshold voltage (V_th). Conceptually, the definition of an n-type or p-type semiconductor depends on whether the corresponding Fermi energy is higher or lower than the intrinsic Fermi energy, respectively. The positive bias applied to the gate would bend down the intrinsic Fermi energy until it is lower than the original p-type Fermi energy, which means that the p-type becomes strongly inverted to become an n-type. First, the thickness of the inversion layer is derived and presented in a planar 40 nm MOSFET, a 3D 240 nm FinFET, and a power discrete IGBT, with the help of the p (1/m³) of the p-type semiconductor. Different ways of finding p (1/m³) are, thus, proposed to resolve the strong inversion layers. Secondly, the conventional formulas, including the triode region and saturation region, are already modified, especially in the triode region from a continuity point of view. The modified formulas then become necessary and available for fitting the measured characteristic curves at different applied gate voltages. Nevertheless, they work well but not well enough. Thirdly, the electromagnetic wave (EM wave) generated from accelerating carriers (radiation by accelerated charges, such as synchrotron radiation) is proposed to demonstrate phonon scattering, which is responsible for the Source–Drain current reduction at the adjoining of the triode region and saturation region. This consideration of reduction makes the fitting more perfect. Fourthly, the strongly inverted layer may be formed but not conductive. The existing trapping would stop carriers from moving (nearly no mobility, μ) unless the applied gate bias is over the threshold voltage. The quantum confinement addressing the quantum well, which traps the carriers, is to be estimated. Full article

AlGaN/GaN heterostructure high electron mobility transistors (HEMTs) have exceptional characteristics, but the structure-function relationship remains to be experimentally fully studied. This study presents a systematic experimental investigation of the synergistic effects of AlGaN barrier thickness and channel length on device performance, a critical gap in the literature, which is often dominated by simulation studies. We experimentally investigated how barrier thickness and channel length influence AlGaN/GaN FET performance. We observed that the transconductance increases with decreasing AlGaN barrier thickness for shorter channel lengths (15 and 50 µm) but showed the opposite trend for the longest channel length (100 µm). Meanwhile, the subthreshold swing was predominantly influenced by the barrier thickness, with thinner barriers generally yielding lower values. These results highlight the intricate interplay between barrier thickness and channel length, providing foundational insights into the design–performance relationship of AlGaN/GaN HEMTs and guiding the development of optimized sensors for different applications. Full article

This study aims to implement universal logic gates using polarity control within a single silicon transistor structure. For this purpose, a reconfigurable transistor based on a p-i-n structure featuring two polarity gates (PGs) and one control gate was proposed, and its electrical characteristics and logic-in-memory (LIM) circuit operations were analyzed via two-dimensional technology computer-aided design simulations. The proposed device could be perfectly reconfigured into p-channel or n-channel modes because virtual doping effects could be induced according to the polarity of the PG voltage. Moreover, based on the positive feedback and latch-up phenomena, a steep subthreshold swing of approximately 1 mV/dec and a high ON/OFF current ratio of the order of 10¹⁰ were achieved. Building on these characteristics, we successfully verified NAND LIM operation in the p-channel mode and NOR LIM operation in the n-channel mode by connecting two of the proposed devices in parallel. The reconfigurable silicon transistor proposed in this study could perform both NAND and NOR LIM operations while sharing the same device structure and can be expected to play a key role in implementing high-density, low-power LIM systems in the future. Full article

Early diagnosis of Alzheimer’s disease (AD) remains challenging due to the extremely low concentration of relevant biomarkers and the limited sensitivity of conventional detection techniques. In this study, we present a carbon nanotube field-effect transistor (CNT-FET) immunosensor for label-free detection of phosphorylated tau at threonine 217 (p-tau217). The device employs a Y₂O₃/HfO₂ dielectric layer and gold nanoparticles (AuNPs) to improve biofunctionalization, with anti-p-tau217 antibodies immobilized on the CNT channels. In phosphate-buffered saline (PBS), the sensor exhibited a linear response over a concentration range of 3 fM to 30 pM (R² = 0.973) and achieved a limit of detection (LOD) of 1.66 fM. The device demonstrated high selectivity, with a normalized signal response (NSR) for p-tau217 that was 5–6 times higher than for human serum albumin (HSA) and p-tau231, even at 1000-fold higher concentrations of these interferents. The sensor exhibited reproducibility with a relative standard deviation (RSD) of 4.8% (n = 9) and storage stability with only a 10% decrease in signal after 7 days at 4 °C. Mechanistic analysis indicated that the net positive charge and structural flexibility of the p-tau217 peptide led to a reduction in drain current upon binding, consistent with electrostatic gating effects in p-type CNT-FETs. Current limitations include the absence of standardized p-tau217 reference materials. Future work will focus on validation with clinical samples. This CNT-FET platform enables rapid, minimally invasive detection of p-tau217 and holds strong potential for integration into clinical workflows to facilitate early AD diagnosis. Full article

This paper presents a simplified matching network using coupled transmission lines (CTLs) for broadband power amplifiers. The proposed structure consists of a CTL with an electrical length shorter than $\lambda$/4 and a single shunt component, exhibiting excellent frequency characteristics across a wide bandwidth at both the input and load networks of the transistor. The reactance variation of the non-Foster elements in the equivalent circuit of the CTL with respect to frequency was analyzed, and the external reactive components were accordingly optimized to extend the bandwidth of the matching network. The proposed network was applied to the input and load networks of a GaN HEMT-based power amplifier. It was designed to maintain required performances over a wide frequency range of 1.9–4.9 GHz, covering both LTE and sub-6 GHz 5G bands, thereby achieving a fractional bandwidth (FBW) of 88.2%. The CTLs were fabricated on a two-layer printed-circuit board (PCB), and the additional shunt components were designed using surface-mount devices (SMDs). The overall power-amplifier module occupied a small area of 40 × 35 mm². Using the continuous-wave (CW) signal, the proposed power amplifier exhibited a power gain of 10–14.8 dB and a drain efficiency (DE) of 47.5–60% at a saturated output power of 7.1–9.3 W across the entire operating frequency band. Using a 5G New Radio (NR) signal with a 100 MHz bandwidth and a peak-to-average power ratio (PAPR) of 7.8 dB, the amplifier achieved an average output power of 30 dBm, a DE of 20–27.5%, and an adjacent-channel leakage power ratio (ACLR) better than −30 dBc. Full article

This work presents a comprehensive study of GaN-on-Si pseudo-vertical MOSFETs focusing on single-trench and multi-trench designs. Thanks to a gate-first process flow based on an Al₂O₃/TiN MOS stack, both fabricated devices exhibit promising transistor behavior, with steady normally OFF operation, very low gate leakage current, and good switching performance. Following the extraction of a low effective channel mobility, the frequency dependence of gate-to-source C–V characteristics is studied. In addition, using TCAD Sentaurus Synopsys simulations, the impact of positive fixed charge and donor-type defects at the p-GaN/dielectric interface is investigated, together with the frequency dependency. Finally, by comparing experimental and simulated results, a mechanism is proposed linking the observed threshold voltage shift to the presence of sharp trench-bottom micro-trenching. This mechanism may further explain the origin of the additional C–V hump observed at high frequencies, which could arise from charge trapping at the p-GaN/dielectric interface or from charge inversion in the p-GaN region. Full article