Search Results (71)

We present a Genetic Algorithm (GA)-based inverse design framework for creating a single-layer, fabrication-compatible dielectric nano-patterned surface that enables efficient color routing in both transmissive and reflective optical systems. Unlike traditional multilayer or absorption-based color filters, the proposed structure employs a fabrication-compatible architecture that spatially routes red, green, and blue light into designated output channels, significantly enhancing light utilization and color fidelity. The design process integrates a GA with full-wave finite-difference time-domain (FDTD) simulations to optimize the structural pillar height distribution, using a figure of merit that simultaneously maximizes optical efficiency and minimizes spectral crosstalk. For CMOS image sensor-scale designs, the nano-patterned surface achieved peak optical efficiencies of 76%, 72%, and 78% for blue, green, and red channels, respectively, with an average efficiency of 75.5%. Parametric studies further revealed the dependence of performance on pillar geometry, refractive index, and unit cell scaling, providing practical design insights for scalable fabrication using nanoimprint or grayscale lithography. Extending the approach to reflective displays, we demonstrate tunable-mirror-based architectures that emulate electrophoretic microcapsules, achieving efficient color reflection and an expanded color gamut beyond the sRGB standard. This single-layer, inverse-designed nano-patterned surface offers a high-performance and fabrication-ready solution for compact, energy-efficient imaging and display technologies. Full article

Quantum-dot Cellular Automata (QCA) technology has emerged as a promising approach for constructing nanoscale digital circuits, offering notable advantages such as minimal power consumption, rapid processing speeds, and highly compact layouts. Traditional CMOS technology faces significant challenges at the nanoscale, including reduced gate control and increased current leakage. QCA, on the other hand, provides a robust platform for building next-generation digital systems. In this study, a unique single-layer QCA-based Full-Adder (QCAFA) and Carry-Save Adder (CSA) architecture is developed to enhance key performance factors such as delay, space, cost, and cell block count. The outlined designs demonstrate superior efficiency compared to state-of-the-art single-layer and multilayer QCA designs. Simulation results conducted with QCADesigner 2.0.3 and QCADesigner-E reveal that the proposed architecture achieves a substantial 34.29% diminution in total cells compared with the recent design, utilising only 46 QCA cells. Similarly, for the CSA, the proposed design attains an 18.62% reduction in cell count compared with its best counterpart, utilising only 424 QCA cell blocks. To enhance design credibility and hardware relevance, this research additionally models and validates the architecture using the Verilog hardware description language (HDL Version 12.0), thereby bridging the gap between nano-architecture and HDL-based prototyping. Simulation results obtained through QCADesigner confirm the correctness and stability of the QCA layout, while HDL simulation verifies functional equivalence at the behavioural and structural levels. The proposed designs not only enhance speed and reduce energy consumption but also offer better manufacturability. The findings of this study highlight the potential of QCA technology as a feasible substitute for CMOS for high-performance digital arithmetic circuits at the nanoscale. Full article

By embedding an aluminum-laminated layer within La₂O₃ thin films and subjecting them to high-temperature rapid thermal annealing, a La₂O₃/LaAl_xO_y/La₂O₃ sandwich dielectric was formed. This structure enhances the interface properties with both the silicon substrate and the metal gate electrode, improving current conduction. Comprehensive analysis using X-ray Photoelectron Spectroscopy (XPS) revealed that this novel process not only facilitates the formation of a high-quality lanthanum aluminate layer, as indicated with Al 2p peak at 74.5 eV, but also effectively suppresses silicate layer growth, as supported by the weak Si-O signal from both the Si 2s (153.9 eV) and O 1s (533 eV) peaks at the dielectric/Si interface in the Al-laminated samples. Fourier Transform Infrared (FTIR) spectroscopy revealed a significant reduction in the OH absorption peak at 3608 cm⁻¹ OH-related band centered at 3433 cm⁻¹. These improvements are attributed to the aluminum-laminated layer, which blocks oxygen and hydroxyl diffusion, the LaAl_xO_y layer scavenging interface silicon oxide, and the consumption of oxygen during LaAl_xO_y formation under thermal annealing. Electrical measurements confirmed that the dielectric films exhibited significantly lower interface and oxide trap densities compared to native La₂O₃ samples. This approach provides a promising method for fabricating high-quality lanthanum-based gate dielectric films with controlled dielectric/substrate interactions, making it suitable for nano-CMOS and memristive device applications. Full article

In recent years, research on light-matter interactions in silicon-based micro/nano cavity optomechanical systems demonstrates high-resolution sensing capabilities (e.g., sub-fm-level displacement sensitivity). Conventional 2D photonic crystal (PhC) cavity optomechanical sensors face inherent limitations: thin silicon layers (200–300 nm) restrict both the mass block (critical for thermal noise suppression) and optical Q-factor. Enlarging the detection mass in such thin layers exacerbates in-plane height nonuniformity, severely limiting high-precision sensing. This study proposes a 500 nm thick silicon-based 2D slot-type PhC cavity design for advanced sensing applications, fabricated on a silicon-on-insulator (SOI) substrate with optimized air slot structures. Systematic parameter optimization via finite element simulations defines structural parameters for the 1550 nm band, followed by 6 × 6 × 6 combinatorial experiments on lattice constant, air hole radius, and line-defect waveguide width. Experimental results demonstrate a loaded Q-factor of 57,000 at 510 nm lattice constant, 175 nm air hole radius, and 883 nm line-defect waveguide width (measured sidewall angle: 88.4°). The thickened silicon layer delivers dual advantages: enhanced mass block for thermal noise reduction and high Q-factor for optomechanical coupling efficiency, alongside improved ridge waveguide compatibility. This work advances the practical development of CMOS-compatible micro-opto-electromechanical systems (MOEMS). Full article

It is vital to measure combustion temperature to define combustion models accurately. For single fuel particles in powder-fueled ramjets, their size distribution ranges from submicron to submillimeter, and their burn time is short to millisecond order. Moreover, the radiation intensity of different types of fuel particles significantly oscillated with several orders of magnitude. Current temperature measurement technology is facing this challenge. This paper proposes a highly spatiotemporal resolved pyrometry to measure the combustion temperature of fuel particles by coupling single-point photomultiplier tube (PMT)-based and two-dimensional complementary metal oxide semiconductor (CMOS)-based photoelectric devices. Both the offline calibration by blackbody furnace and online calibration by standard lamp confirmed the measurement accuracy of the pyrometry. Then, the pyrometry was used to measure the combustion temperature of fuel particles including micro-Al, nano-Al, micro-Mg, nano-B, and micro-B₄C. The temperature evolution and distribution of burning fuel particles were complementarily obtained, especially the interfacial flame temperature near the particle surface. Based on the obtained combustion temperature, the combustion characteristics and the energy release efficiencies among these fuels were evaluated and compared in detail, which are helpful to recognize, in depth, the combustion behavior and reveal the combustion mechanism of fuel particles in powder-fueled ramjets. Full article

This work presents a nano-watt digital output temperature sensor featuring a supply-insensitive, self-biased current source. Second-order temperature dependencies of the MOS diode are canceled to produce a stable reference and a linear temperature-sensitive voltage. The sensor integrates a sensing unit, voltage-controlled differential ring oscillators, and a low-power frequency-to-digital converter, utilizing a resistor-less design to minimize power and area. The delay element in the ring oscillator reduces stage count, improving noise performance and compactness. Fabricated in 65 nm CMOS, the sensor occupies 0.02 mm² and consumes 60 nW at 25 °C and 0.8 V. Measurements show an inaccuracy of +1.5/−1.6 °C from −20 °C to 120 °C after two-point calibration, with a resolution of 0.2 °C (rms) and a resolution FoM of 0.022 nJ·K⁻². Consuming 0.55 nJ per conversion with a 9.2 ms conversion time, the sensor was tested in a battery-less wireless sensor node, demonstrating its suitability for wireless sensing systems. Full article

Transcutaneous carbon dioxide (TcPCO2) monitoring provides a non-invasive alternative to measuring arterial carbon dioxide (PaCO2), making it valuable for various applications, such as sleep diagnostics and neonatal care. However, traditional transcutaneous monitors are bulky, expensive, and pose risks such as skin burns. To address these limitations, we have introduced a compact, cost-effective CMOS imager-based sensor for TcPCO2 detection by utilizing colorimetric reactions with metal–organic framework (MOF)-based nano-hybrid materials. The sensor, with a colorimetric sensing array fabricated on an ultrathin PDMS membrane and then adhered to the CMOS imager surface, can record real-time sensing data through image processing without the need for additional optical components, which significantly reduces the sensor’s size. Our system shows impressive sensitivity and selectivity, with a low detection limit of 26 ppm, a broad detection range of 0–2% CO₂, and strong resistance to interference from common skin gases. Feasibility tests on human subjects demonstrate the potential of this MOF-CMOS imager-based colorimetric sensor for clinical applications. Additionally, its compact design and responsiveness make it suitable for sports and exercise settings, offering valuable insights into respiratory function and performance. The sensing system’s compact size, low cost, and reversible and highly sensitive TcPCO2 monitoring capability make it ideal for integration into wearable devices for remote health tracking. Full article

This paper reports the successful application of a self-developed, miniaturized, low-power nano-star tracker for precise attitude measurement of a 5-m-long satellite extension boom. Such extension booms are widely used in space science missions to extend and support payloads like magnetometers. The nano-star tracker, based on a CMOS image sensor, weighs 150 g (including the baffle), has a total power consumption of approximately 0.85 W, and achieves a pointing accuracy of about 5 arcseconds. It is paired with a low-cost, commercial lens and utilizes automated calibration techniques for measurement correction of the collected data. This system has been successfully applied to the precise attitude measurement of the 5-m magnetometer boom on the Chinese Advanced Space Technology Demonstration Satellite (SATech-01). Analysis of the in-orbit measurement data shows that within shadowed regions, the extension boom remains stable relative to the satellite, with a standard deviation of 30′′ (1σ). The average Euler angles for the “X-Y-Z” rotation sequence from the extension boom to the satellite are [−89.49°, 0.08°, 90.11°]. In the transition zone from shadow to sunlight, influenced by vibrations and thermal factors during satellite attitude adjustments, the maximum angular fluctuation of the extension boom relative to the satellite is approximately ±2°. These data and the accuracy of the measurements can effectively correct magnetic field vector measurements. Full article

This paper presents recent results on CMOS integrated circuits for automotive radar sensor applications in the 77 GHz frequency band. It is well demonstrated that nano-scale CMOS technologies are the best solution for the implementation of low-cost and high-performance mm-wave radar sensors since they provide high integration level besides supporting high-speed digital processing. The present work is mainly focused on the RF front-end and summarizes the most stringent requirements of both short/medium- and long-range radar applications. After a brief introduction of the adopted technology, the paper addresses the critical building blocks of the receiver and transmitter chain while discussing crucial design aspects to meet the final performance. Specifically, effective circuit topologies are presented, which concern mixer, variable-gain amplifier, and filter for the receiver, as well as frequency doubler and power amplifier for the transmitter. Moreover, a voltage-controlled oscillator for a PLL efficiently covering the two radar bands is described. Finally, the circuit description is accompanied by experimental results of an integrated implementation in a 28 nm fully depleted silicon-on-insulator CMOS technology. Full article

Memristors are state-of-the-art, nano-sized, two-terminal, passive electronic elements with very good switching and memory characteristics. Owing to their very low power usage and a good compatibility to the existing CMOS ultra-high-density integrated circuits and chips, they are potentially applicable in artificial and spiking neural networks, memory arrays, and many other devices and circuits for artificial intelligence. In this paper, a complete electronic realization of an analog circuit model of the modified neural net with memristor-based synapses and transfer function with memristors and MOS transistors in LTSPICE is offered. Each synaptic weight is realized by only one memristor, providing enormously reduced circuit complexity. The summing and scaling implementation is founded on op-amps and memristors. The logarithmic-sigmoidal activation function is based on a simple scheme with MOS transistors and memristors. The functioning of the suggested memristor-based neural network for pulse input signals is evaluated both analytically in MATLAB-SIMULINK and in the LTSPICE environment. The obtained results are compared one to another and are successfully verified. The realized memristor-based neural network is an important step towards the forthcoming design of complex memristor-based neural networks for artificial intelligence, for implementation in very high-density integrated circuits and chips. Full article

Contact scaling is a major challenge in nano complementary metal–oxide–semiconductor (CMOS) technology, as the surface roughness, contact size, film thicknesses, and undoped substrate become more problematic as the technology shrinks to the nanometer range. These factors increase the contact resistance and the nonlinearity of the current–voltage characteristics, which could limit the benefits of the further downsizing of CMOS devices. This review discusses issues related to the contact size reduction of nano CMOS technology and the validity of the Schottky junction model at the nanoscale. The difficulties, such as the limited doping level and choices of metal for band alignment, Fermi-level pinning, and van der Waals gap, in achieving transparent ohmic contacts with emerging two-dimensional materials are also examined. Finally, various methods for improving ohmic contacts’ characteristics, such as two-dimensional/metal van der Waals contacts and hybrid contacts, junction doping technology, phase and bandgap modification effects, buffer layers, are highlighted. Full article

This paper presents a new low-voltage versatile mixed-mode filter which uses a multiple-input/output differential difference transconductance amplifier (MIMO-DDTA). The multiple-input of the DDTA is realized using a multiple-input bulk-driven MOS transistor (MI-BD-MOST) technique to maintain a single differential pair, thereby achieving simple structure with minimal power consumption. In a single topology, the proposed filter can provide five standard filtering functions (low-pass, high-pass, band-pass, band-stop, and all-pass) in four modes: voltage (VM), current (CM), transadmittance (TAM), and transimpedance (TIM). This provides the full capability of a mixed-mode filter (i.e., twenty filter functions). Moreover, the VM filter offers high-input and low-output impedances and the CM filter offers high-output impedance; therefore, no buffer circuit is needed. The natural frequency of all filtering functions can be electronically controlled by a setting current. The voltage supply is 0.5 V and for a 4 nA setting current, the power consumption of the filter was 281 nW. The filter is suitable for low-frequency biomedical and sensor applications that require extremely low supply voltages and nano-watt power consumption. For the VM low-pass filter, the dynamic range was 58.23 dB @ 1% total harmonic distortion. The proposed filter was designed and simulated in the Cadence Virtuoso System Design Platform using the 0.18 µm TSMC CMOS technology. Full article

The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm². These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field. Full article

This research presents a comparative analysis of design parameters in modern power amplifier (PA) architecture trends in various CMOS nano-meter technologies. The design parameters include the signal gain, linearity, output power, and output power back-off. The resultant parameters are compared using a table, and various parameters of various designs are visually shown for comparison. These comparative findings will provide any designer with practical information to choose the best CMOS PA design for a specific application. The most important RF CMOS PA integrated implementations are addressed in the conclusion section. Full article

Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions. Full article