Search Results (249)

This work presents a low-power photoplethysmography (PPG) readout integrated circuit (IC) that achieves a wide dynamic range (DR) through the direct integration of a voltage-controlled oscillator (VCO)-based quantizer into the photodiode driver. Conventional PPG readout circuits rely on either transimpedance amplifier (TIA) or light-to-digital converter (LDC) topologies, both of which require auxiliary DC suppression loops. These additional loops not only raise power consumption but also limit the achievable DR. The proposed design eliminates the need for such circuits by embedding a linear regulator with a mirroring scale calibrator and a time-domain quantizer. The quantizer provides first-order noise shaping, enabling accurate extraction of the AC PPG signal while the regulator directly handles the large DC current component. Post-layout simulations show that the proposed readout achieves a signal-to-noise-and-distortion ratio (SNDR) of 40.0 dB at 10 µA DC current while consuming only 0.80 µW from a 2.5 V supply. The circuit demonstrates excellent stability across process–voltage–temperature (PVT) corners and maintains high accuracy over a wide DC current range. These features, combined with a compact silicon area of 0.725 mm² using TSMC 250 nm bipolar–CMOS–DMOS (BCD) process, make the proposed IC an attractive candidate for next-generation wearable and biomedical sensing platforms. Full article

This paper presents a CMOS-based hybrid system capable of noninvasively quantifying the total hemoglobin (tHb), the oxygen saturation (SpO₂), and the heart rate (HR) by utilizing five-wavelength (670, 770, 810, 850, and 950 nm) photoplethysmography. Conventional pulse oximeters are limited to the measurements of SpO₂ and heart rate, therefore hindering the real-time estimation of tHb that is clinically essential for monitoring anemia, chronic diseases, and postoperative recovery. Therefore, the proposed hybrid system enables us to distinguish between the concentrations of oxygenated (HbO₂) and deoxygenated hemoglobin (Hb) by using the absorption characteristics of five wavelengths from the visible to near-infrared range. This CMOS hybrid mixed-signal architecture includes a light emitting diode (LED) driver as a transmitter and an optoelectronic receiver with on-chip avalanche photodiodes, followed by a field-programmable gate array (FPGA) for a real-time signal processing pipeline. The proposed hybrid system, validated through post-layout simulations and algorithmic verification, achieves high precision with ±0.3 g/dL accuracy for tHb and ±1.5% for SpO₂, while the heart rate is extracted via 1024-point Fast Fourier Transform (FFT) with an error below ±0.2%. These results demonstrate the potential of a CMOS-based hybrid system as a feasible solution to achieve real-time, low-power, and high-accuracy analysis of bio-signals for clinical and home-use applications. Full article

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems. Full article

This paper presents an advanced W-band bidirectional Power Amplifier–Low Noise Amplifier (PALNA) implemented using 130 nm SiGe BiCMOS technology. The proposed RF front-end eliminates the need for conventional transmit/receive (T/R) switches by employing a bidirectional architecture with a passive matching network. This approach minimizes area requirements and reduces signal losses. Post-layout simulation results demonstrate that the designed PALNA achieves a peak small-signal gain of 30 dB in Tx mode and 26 dB in Rx mode, with reverse isolation better than 40 dB. The 3 dB bandwidth spans from 94 to 106 GHz. In LNA mode, the design achieves a minimum noise figure of 6 dB at 100 GHz, remaining below 6.5 dB across the entire 3 dB bandwidth. In PA mode, the simulated saturated output power is 10.5 dBm, with a maximum power-added efficiency of 12% at 100 GHz. The chip size is 0.7 mm² including pads. It consumes 78 and 22 mW in the Tx and Rx modes, respectively. Full article

A ring-oscillator based voltage-controlled oscillator (VCO) architecture with reduced frequency drift across temperature and process variations is presented in this paper. The frequency stability is achieved through two dedicated compensation techniques: a temperature compensation circuit that generates a proportional-to-absolute-temperature (PTAT) current to mitigate frequency shifts due to temperature changes, and a process compensation circuit that dynamically adjusts the frequency based on detected process corners. The proposed design is implemented in a 22 nm CMOS technology with a 0.8 V supply voltage and targets a nominal oscillation frequency of 2.5 GHz. The post-layout simulation results demonstrate a significant improvement in frequency stability, reducing temperature-induced frequency drift from 23.9% to a range of 5.4% over the −40 °C to 125 °C temperature range for the typical corner. Combining temperature and process compensation, the frequency drift is improved from 47.3% to better than 7.2%. The VCO also achieves a phase noise value about −80 dBc/Hz at a 1 MHz offset with an average power consumption of 380 µW, including the tuning mechanism and the compensation circuits. Full article

This paper presents a 90–100 GHz wideband digital phase shifter with a fine resolution of 5.625°, implemented in a 0.13 μm SiGe BiCMOS process. A switch-type architecture with six cascaded units, including a novel 180° cell based on a broadband coupler, enables full 0–360° phase coverage while improving phase accuracy, bandwidth, and process robustness. Post-layout simulations demonstrate an insertion loss below 15.5 dB, an RMS phase error under 2.3°, and an RMS amplitude error better than 0.9 dB across the 90–100 GHz band. The total chip area, including test pads, is 0.39 mm², making the design compact and well suited for high-density phased-array applications. Full article

This paper presents a temperature-robust current-mode vertical-cavity surface-emitting laser (VCSEL) driver (or CMVD) fabricated in a standard 180 nm CMOS process. While prior art relies on conventional current-mirror circuits for bias generation, the proposed CMVD integrates a bandgap-based biasing architecture to achieve high thermal stability and process insensitivity. The bandgap core yields a temperature-compensated reference voltage and is then converted into both stable bias and modulation currents through a cascode current-mirror and switching logic. Post-layout simulations of the proposed CMVD show that the reference voltage variation remains within ±2%, and the bias current deviation is under 10% across full PVT conditions. Furthermore, the output current variation is limited to 7.4%, even under the worst-case corners (SS, 125 °C), demonstrating the reliability of the proposed architecture. The implemented chip occupies a compact core area of 0.0623 mm² and consumes an average power of 18 mW from a single 3.3 V supply, suggesting that the bandgap-stabilized CMVD is a promising candidate for compact, power-sensitive optical systems requiring reliable and temperature-stable performance. Full article

This paper presents a three-segment interpolating Digital-to-Analog Converter (DAC) that employs a redundancy-based interpolation scheme and digital calibration to enhance linearity. The proposed architecture consists of a Most Significant Bit (MSB) resistor string DAC, an Intermediate Significant Bit (ISB) resistor string DAC, and a Least Significant Bit (LSB) interpolating differential buffer. The MSB segment uses a split-unit resistor structure ($r_A,r_B$) to improve post-calibration differential nonlinearity (DNL) by minimizing voltage step errors. A fully digital calibration algorithm is implemented to compensate for process variations, component mismatches, and finite switch resistance, ensuring a highly linear DAC output. The proposed 16-bit DAC is implemented in a 180 nm CMOS process and is segmented into a 5-bit MSB stage, a 5-bit ISB stage, and a 6-bit LSB stage. The structure achieves post-calibration integral nonlinearity (INL) and differential nonlinearity (DNL) values of less than ±1 LSB. Simulation results validate the proposed design, demonstrating enhanced linearity and reduced area overhead compared with conventional segmented architectures. Full article

Electrochemical sensing arrays enable the spatial study of dopamine levels throughout brain slices, the diffusion of electroactive molecules, as well as neurotransmitter secretion from single cells. The integration of complementary metal-oxide semiconductor (CMOS) devices in the development of electrochemical sensing devices enables large-scale parallel recordings, providing beneficial high-throughput for drug screening studies, brain–machine interfaces, and single-cell electrophysiology. In this paper, an electrochemical sensor capable of recording at 40,000 frames per second using a CMOS sensor array with 1024 electrochemical detectors and a custom field-programmable gate array data acquisition system is detailed. A total of 1024 on-chip electrodes are monolithically integrated onto the designed CMOS chip through post-CMOS fabrication. Each electrode is paired with a dedicated transimpedance amplifier, providing 1024 parallel electrochemical sensors for high-throughput studies. To support the level of data generated by the electrochemical device, a powerful data acquisition system is designed to operate the sensor array as well as digitize and transmit the output of the CMOS chip. Using the presented electrochemical sensing system, both dopamine and hydrogen peroxide diffusions across the sensor array are successfully recorded at 40,000 frames per second across the 32 × 32 electrochemical detector array. Full article

This paper presents a disaster detection framework based on aerial imagery, utilizing a Branch Convolutional Neural Network (B-CNN) to enhance feature learning efficiency. The B-CNN architecture incorporates branch training, enabling effective training and inference with reduced model parameters. To further optimize resource usage, the framework integrates DoReFa-Net for weight quantization and fixed-point parameter representation. An early exit mechanism is introduced to support low-latency, energy-efficient predictions. The proposed B-CNN hardware accelerator is implemented using TSMC 16 nm CMOS technology, incorporating power gating techniques to manage memory power consumption. Post-layout simulations demonstrate that the proposed hardware accelerator operates at 500 MHz with a power consumption of 37.56 mW. The system achieves a disaster prediction accuracy of 88.18%, highlighting its effectiveness and suitability for low-power, real-time applications in aerial disaster monitoring. Full article

For high-voltage signal detection applications, an auto-zero and chopper operational amplifier (OPA) is proposed in this paper. With the auto-zero and chopper technique, the OPA adopts an eight-channel Ping-Pong mechanism to reduce the high-frequency ripple and glitch generated by chopper modulation. The main transconductor effectively suppresses low-frequency noise and offset by combining input coarse and output fine auto-zero. A common-mode voltage tracking circuit is presented to ensure constant gate-source and gate-substrate voltages of the chopper, which reduces the charge injection caused by threshold voltage drift of their transistors and improves output signal resolution. The OPA is implemented using CMOS 180 nm BCD process. The post-simulation results show that the unit gain bandwidth (UGB) is 2.5 MHz and common-mode rejection ratio (CMRR) is 137 dB when the power supply voltage is 5–55 V. The noise power spectral density (PSD) is 6.6 nV/√Hz, and the offset is about 47 µV. The overall circuit consumes current of 960 µA. Full article

This paper presents a wideband low-power/low-voltage 60-GHz low-noise amplifier (LNA) in a 28-nm bulk CMOS technology. The LNA has been designed for high-speed millimeter-wave (mm-wave) communications. It consists of two pseudo-differential amplifying stages and a buffer stage included for 50-Ohm on-wafer measurements. Two integrated input/output baluns guarantee both simultaneous 50-ohm input–noise/output matching at input/output radio frequency (RF) pads. A power-efficient design strategy is adopted to make the LNA suitable for low-power applications, while minimizing the noise figure (NF). Thanks to the adopted design strategy, the post-layout simulation results show an excellent trade-off between power gain and 3-dB bandwidth (BW_3dB) with 13.5 dB and 7 GHz centered at 60 GHz, respectively. The proposed LNA consumes only 11.6 mA from a 0.9-V supply voltage with an NF of 8.4 dB at 60 GHz, including the input transformer loss. The input 1 dB compression point (IP_1dB) of −15 dBm at 60 GHz confirms the first-rate linearity of the proposed amplifier. Human body model (HBM) electrostatic discharge (ESD) protection is guaranteed up to 2 kV at the RF input/output pads thanks to the input/output integrated transformers. Full article

Next-generation smart sensing devices necessitate on-chip integration of power-efficient reference circuits. The latters are required to provide other circuit blocks with highly reliable bias signals, even in the presence of temperature shifts and supply voltage disturbances, while draining a small fraction of the overall power budget. In particular, it is especially challenging to design current references with enhanced robustness and efficiency; hence, thorough exploration of novel architectures and design approaches is needed for this type of circuits. In this work, we propose a novel CMOS-only current reference, achieving temperature compensation by exploiting geometry dependences of the threshold voltage (specifically, the reverse short-channel effect and the narrow-channel effect). This allows reaching first-order temperature compensation within a single current reference core. Implemented in 0.18 µm CMOS, a version of the proposed current reference designed to deliver 141 nA (with 377 nW of total power consumption) achieved an average temperature coefficient equal to 194 ppm/°C (from −20 °C to 80 °C) and an average line sensitivity of −0.017%/V across post-layout statistical Monte Carlo simulations. Based on such findings, the newly proposed design methodology stands out as a noteworthy solution to design robust current references for power-constrained mixed-signal systems-on-chip. Full article

Based on the GSMC 180 nm SiGe BiCMOS process, a parallel-summation logarithmic amplifier is presented in this paper. The logarithmic amplifier adopts a cascaded structure of nine-stage fully-differential limiting amplifiers (LA) to achieve high dynamic range. The ten-stage rectifier completes the conversion of amplified voltage to a logarithmic current signal. A log slope adjuster is proposed. It can provide slopes of 17–30 mV/dB by configuring an off-chip resistor to meet the detection requirements of different input power. Meanwhile, a power-down control unit is designed to reduce the power consumption to only 162 μW in standby mode. The post-simulation results show that under 5 V power supply voltage, the dynamic range exceeds 80 dB and the 3 dB bandwidth is 20 MHz–4 GHz. It also has a fast response time of 42 ns with a power consumption of 109 mW in normal operation mode. Full article

This paper presents a CMOS-based optoelectronic receiver integrated circuit (CORIC) realized in a standard 180 nm CMOS technology for the applications of short-distance optical interconnects. The CORIC comprises a spatially modulated P⁺/N-well on-chip avalanche photodiode (P⁺/NW APD) for optical-to-electrical conversion, a dummy APD at the differential input for enhanced common-mode noise rejection, a cross-coupled differential transimpedance amplifier (CCD-TIA) for current-to-voltage conversion, a 3-bit continuous-time linear equalizer (CTLE) for adaptive equalization by using NMOS registers, and a $f_T$-doubler output buffer (OB). The CTLE and $f_T$-doubler OB combination not only compensates the frequency-dependent signal loss, but also provides symmetric differential output signals. Post-layout simulations of the proposed CORIC reveal a transimpedance gain of 53.2 dBΩ, a bandwidth of 4.83 GHz even with a 490 fF parasitic capacitance from the on-chip P⁺/NW APD, a dynamic range of 60 dB that handles the input photocurrents from 1 μA_pp to 1 mA_pp, and a DC power consumption of 33.7 mW from a 1.8 V supply. The CORIC chip core occupies an area of 260 × 101 μm². Full article