Search Results (1,363)

Graphene was directly grown on SiO₂/Si substrates using microwave plasma-enhanced chemical vapor deposition (PECVD) to investigate how synthesis-driven variations in structure and doping influence carrier transport. The effects of synthesis temperature, plasma power, deposition time, gas flow, and pressure on graphene’s structure and electronic properties were systematically studied. Raman spectroscopy revealed non-monotonic changes in layer number, defect density, and doping levels, reflecting the complex interplay between growth, etching, and self-doping mechanisms. The surface morphology and conductivity were assessed by atomic force microscopy (AFM). Charge carrier mobility, extracted from graphene-based field-effect transistors, showed strong correlations with Raman features, including the intensity ratios and positions of the 2D and G peaks. Importantly, mobility did not correlate with defect density but was linked to reduced self-doping and a weaker graphene–substrate interaction rather than intrinsic structural disorder. These findings suggest that charge transport in PECVD-grown graphene is predominantly limited by interfacial and doping effects. This study offers valuable insights into the synthesis–structure–property relationship, which is crucial for optimizing graphene for electronic and sensing applications. Full article

We systematically investigate the combined impact of process variation effects (PVEs), metal gate work function fluctuation (WKF), and random dopant fluctuation (RDF) on the key electrical characteristics of sub-1-nm technology node gate-all-around silicon nanosheet complementary field-effect transistors (GAA Si NS CFETs). Through comprehensive statistical analysis, we reveal that the interplay of these intrinsic and extrinsic sources of variability induces significant fluctuations in the off-state leakage current across both N-/P-FETs in GAA Si NS CFETs. The sensitivity to process-induced variability is found to be particularly pronounced in the P-FETs, primarily due to the enhanced parasitic conduction associated with the bottom nanosheet channel. Given the correlated nature of PVE, WKF, and RDF factors, the statistical sum (RSD) of the fluctuation for each factor is overestimated by less than 50% compared with the simultaneous fluctuations of PVE, WKF, and RDF factors. Furthermore, although the static power dissipation remains relatively small compared to dynamic and short-circuit power components, it exhibits the largest relative fluctuation (approximately 82.1%), posing critical challenges for low-power circuit applications. These findings provide valuable insights into the variability-aware design and optimization of GAA NS CFET device fabrication processes, as well as the development of robust and reliable CFET-based integrated circuits for next-generation technology nodes. Full article

In high-power insulated gate bipolar transistor (IGBT) module thermal management, the structural design of microchannel cooling plates plays a crucial role in determining heat dissipation efficiency and temperature uniformity. This study focuses on the effects of honeycomb-structured unit dimensions and arrangements, as well as inlet/outlet configurations of the cooling plate on its thermal and flow performance. Additionally, the influence of different coolant inlet velocities and temperatures is investigated. Under constant coolant flow rate and boundary conditions, four design configurations with varying pore widths and channel spacings were evaluated numerically. The results indicate that the optimized honeycomb structure can reduce the module’s peak temperature by approximately 8.7 K while significantly improving temperature uniformity and maintaining a moderate pressure drop. Moreover, increasing the number of inlets and outlets effectively lowers the pressure drop and enhances thermal uniformity. Although increasing the coolant flow rate and reducing the inlet temperature can further improve cooling performance, these measures also lead to notable increases in energy consumption and pressure loss. Therefore, a trade-off between thermal enhancement and system energy efficiency must be considered in practical applications. The findings of this study provide practical guidance for the design optimization of high-efficiency microchannel liquid cooling systems in power electronic applications. Full article

Discrete Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors (SiC MOSFETs) are characterized by their lower parasitic parameters and single-chip design, enabling them to achieve even faster switching speeds. However, the rapid rate of change in voltage (dv/dt) and current (di/dt) can lead to overshoot and oscillation in both voltage and current, ultimately limiting the performance of high-frequency operations. To address this issue, this paper presents a high-switching-frequency motor controller that utilizes discrete SiC MOSFETs. To achieve a high switching frequency for the controller while minimizing current oscillation and voltage overshoot, a novel electronic system architecture is proposed. Additionally, a passive driving circuit is designed to suppress gate oscillation without the need for additional control circuits. A new printed circuit board (PCB) laminate stack featuring low parasitic inductance, high current conduction capacity, and efficient heat dissipation is also developed using advanced wiring technology and a specialized heat dissipation structure. Compared to traditional methods, the proposed circuit and bus design features a simpler structure, a higher power density, and achieves a 13% reduction in current overshoot, along with a 15.7% decrease in switching loss. The silicon carbide (SiC) controller developed from this research has successfully undergone double-pulse and power testing. The results indicate that the designed controller can operate reliably over extended periods at a switching frequency of 50 kHz, achieving a maximum efficiency of 98.2% and a power density of 9 kW/kg (10 kW/L). The switching frequency and quality density achieved by the controller have not been observed in previous studies. This controller is suitable for use in the development of new energy electrical systems. Full article

This paper presents a novel literature survey on leveraging electrolysis for grid frequency stabilization in power systems with high penetration of renewable energy sources (RESs), uniquely integrating global research findings with specific insights into the Polish energy context—a region facing acute grid challenges due to rapid RES growth and infrastructure limitations. The intermittent nature of wind and solar power exacerbates frequency fluctuations, necessitating dynamic demand-side management solutions like hydrogen production via electrolysis. By synthesizing over 30 studies, the survey reveals key results: electrolysis systems, particularly PEM and alkaline electrolyzers, can reduce frequency deviations by up to 50% through fast frequency response (FFR) and primary reserve provision, as demonstrated in simulations and real-world pilots (e.g., in France and the Netherlands); however, economic viability requires enhanced compensation schemes, with current models showing unprofitability without subsidies. Technological advancements, such as transistor-based rectifiers, improve efficiency under partial loads, while integration with RES farms mitigates overproduction issues, as evidenced by Polish cases where 44 GWh of solar energy was curtailed in March 2024. The survey contributes actionable insights for policymakers and engineers, including recommendations for deploying electrolyzers to enhance grid resilience, support hydrogen-based transportation, and facilitate Poland’s target of 50.1% RESs by 2030, thereby advancing the green energy transition amid rising instability risks like blackouts in RES-heavy systems. Full article

The bulk linearization technique is a design strategy used to extend the linear region of a metal oxide semiconductor field effect transistor (MOSFET) by increasing its saturation voltage through a composite structure and a gate biasing circuit. This allows us to develop compact and flexible pseudo-resistor elements for integrated circuit designs. In this paper we propose a new simple yet effective design approach, focused on the biasing circuit, that optimizes area, offset, and power consumption without altering the design complexity of the original solution. Post-layout simulations verify the presented design strategy, which is then applied for designing a band-pass filter for neural action potential acquisition. Results of harmonic distortion and noise analysis strengthen the validity of the proposed strategy. Full article

We present a highly sensitive and selective gas sensor based on an advanced silicon-on-insulator tunnel field-effect transistor (SOI-TFET) architecture, enhanced through the integration of customized conducting polymers. In this design, traditional metal gates are replaced with distinct functional polymers—PPP-TOS/AcCN, PP-TOS/AcCN, PP-FE(CN)₆³⁻/H₂O, PPP-TCNQ-TOS/AcCN, and PPP-ClO₄/AcCN—which enable precise molecular recognition and discrimination of various target gases. To further enhance sensitivity, the device employs an oppositely doped source region, significantly improving gate control and promoting stronger band-to-band tunneling. This structural modification amplifies sensing signals and improves noise immunity, allowing reliable detection at trace concentrations. Additionally, optimization of the subthreshold swing contributes to faster switching and response times. Thermal stability is addressed by embedding a P-type buffer layer within the buried oxide, which increases thermal conductivity and reduces lattice temperature, further stabilizing device performance. Experimental results demonstrate that the proposed sensor outperforms conventional SOI-TFET designs, exhibiting superior sensitivity and selectivity toward analytes such as methanol, chloroform, isopropanol, and hexane. Beyond gas sensing, the unique polymer-functionalized gate design enables integration of microbial biosensing capabilities, making the platform highly versatile for biochemical detection. This work offers a promising pathway toward ultra-sensitive, low-power sensing technologies for environmental monitoring, industrial safety, and medical diagnostics. Full article

For high-voltage signal detection applications, an auto-zero and chopper operational amplifier (OPA) is proposed in this paper. With the auto-zero and chopper technique, the OPA adopts an eight-channel Ping-Pong mechanism to reduce the high-frequency ripple and glitch generated by chopper modulation. The main transconductor effectively suppresses low-frequency noise and offset by combining input coarse and output fine auto-zero. A common-mode voltage tracking circuit is presented to ensure constant gate-source and gate-substrate voltages of the chopper, which reduces the charge injection caused by threshold voltage drift of their transistors and improves output signal resolution. The OPA is implemented using CMOS 180 nm BCD process. The post-simulation results show that the unit gain bandwidth (UGB) is 2.5 MHz and common-mode rejection ratio (CMRR) is 137 dB when the power supply voltage is 5–55 V. The noise power spectral density (PSD) is 6.6 nV/√Hz, and the offset is about 47 µV. The overall circuit consumes current of 960 µA. Full article

Thermal management is an area of study in electronics focused on managing temperature to improve reliability and efficiency. When temperatures are too high, cooling systems are activated to prevent overheating, which can lead to reliability issues. To monitor the temperatures, sensors are often placed on-chip near hotspot locations. These sensors should be very small to allow them to be placed among compact, high-activity circuits. Often, they are connected to a central control circuit located far away from the hot spot locations where more area is available. This paper proposes sensing units for a novel temperature sensing architecture in the TSMC 180 nm process. This architecture functions by approximating the current through the sensing unit at a reference voltage, which is used to approximate the temperature in the digital back end using fitting functions. Sensing units are selected based on how well its temperature–current relationship can be modeled, sensing unit area, and power consumption. Many sensing units will be experimented with at different reference voltages. These temperature–current curves will be modeled with various fitting functions. The sensing unit selected is a diode-connected p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a size of W = 400 nm, L = 180 nm. This sensing unit is exceptionally small compared to existing work because it does not rely on multiple devices at the sensing unit location to generate a PTAT or IPTAT signal like most work in this area. The temperature–current relationship of this device can also be modeled using a 2nd order polynomial, requiring a minimal number of trim temperatures. Its temperature error is small, and the power consumption is low. The range of currents for this sensing unit could be reasonably made on an IDAC. Full article

This paper presents the first hybrid supply modulator (HSM) designed for envelope tracking power amplifiers (ET-PAs) in base station applications. The focus is on a rail-to-rail Class-AB linear amplifier (LA) optimized for high-voltage and wide-bandwidth operation. The LA is designed using 130 nm BCD technology, utilizing Laterally Diffused Metal-Oxide Semiconductor (LDMOS) transistors for high-voltage operation and incorporating shielding MOSFETs to protect the low-voltage devices. The circuit utilizes dual power supply domains (5 V and 30 V) to improve power efficiency. The proposed LA achieves a bandwidth of 100 MHz and a slew rate of +1003/−852 V/$\mathsf{\mu }\mathrm{s}$, with a quiescent power consumption of 0.89 W. Transient simulations using a 50 MHz bandwidth 5G NR envelope input demonstrate that the proposed HSM achieves a power efficiency of 83%. Consequently, the proposed HSM supports high-output (100 W) wideband 5G NR transmission with enhanced efficiency. Full article

The development of an integrated circuit faces the challenge of the physical limit of Moore’s Law. One of the most important “Beyond Moore” challenges is the scaling down of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) versus their increasing static power consumption. This is because, at room temperature, the thermal emission transportation mechanism will cause a physical limitation on subthreshold swing (SS), which is fundamentally limited to a minimum value of 60 mV/decade for MOSFETs, and accompanied by an increase in off-state leakage current with the process of scaling down. Moreover, the impacts of short-channel effects on device performance also become an increasingly severe problem with channel length scaling down. Due to the band-to-band tunneling mechanism, Tunnel Field-Effect Transistors (TFETs) can reach a far lower SS than MOSFETs. Recent research works indicated that TFETs are already becoming some of the promising candidates of conventional MOSFETs for ultra-low-power applications. This paper provides a review of some advances in materials and structures along the evolutionary process of TFETs. An in-depth discussion of both experimental works and simulation works is conducted. Furthermore, the performance of TFETs with different structures and materials is explored in detail as well, covering Si, Ge, III-V compounds and 2D materials, alongside different innovative device structures. Additionally, this work provides an outlook on the prospects of TFETs in future ultra-low-power electronics and biosensor applications. Full article

AlGaN-based high-electron-mobility transistors are critical for next-generation power electronics and radio-frequency applications, yet achieving stable enhancement-mode operation with a high threshold voltage remains a key challenge. In this work, we designed p-AlGaN superlattices with different structures and performed energy band structure simulations using the device simulation software Silvaco. The results demonstrate that thin barrier structures lead to reduced acceptor incorporation, thereby decreasing the number of ionized acceptors, while facilitating vertical hole transport. Superlattice samples with varying periodic thicknesses were grown via metal-organic chemical vapor deposition, and their crystalline quality and electrical properties were characterized. The findings reveal that although gradient-thickness barriers contribute to enhancing hole concentration, the presence of thick barrier layers restricts hole tunneling and induces stronger scattering, ultimately increasing resistivity. In addition, we simulated the structure of the enhancement-mode HEMT with p-AlGaN as the under-gate material. Analysis of its energy band structure and channel carrier concentration indicates that adopting p-AlGaN superlattices as the under-gate material facilitates achieving a higher threshold voltage in enhancement-mode HEMT devices, which is crucial for improving device reliability and reducing power loss in practical applications such as electric vehicles. Full article

In advanced Complementary Metal-Oxide-Semiconductor (CMOS) technologies, where diminished feature sizes amplify radiation-induced soft errors, the optimization of fault-tolerant circuit designs requires detailed transistor-level analysis of reliability–performance trade-offs. As a fundamental building block in digital systems and critical data paths, the 2:1 multiplexer, widely used in data-path routing, clock networks, and reconfigurable systems, provides a critical benchmark for assessing radiation-hardened design methodologies. In this context, this work aims to analyze the power consumption, area overhead, and delay of 2:1 multiplexer designs under transient fault conditions, employing the CMOS and Differential Cascode Voltage Switch Logic (DCVSL) logic styles and mitigation strategies. Electrical simulations were conducted using 32 nm high-performance predictive technology, evaluating both the original circuit versions and modified variants incorporating three mitigation strategies: transistor sizing, D-Cells, and C-Elements. Key metrics, including power consumption, delay, area, and radiation robustness, were analyzed. The C-Element and transistor sizing techniques ensure satisfactory robustness for all the circuits analyzed, with a significant impact on delay, power consumption, and area. Although the D-Cell technique alone provides significant improvements, it is not enough to achieve adequate levels of robustness. Full article

With their superior switching speed, GaN high-electron-mobility transistors (HEMTs) enable high power density, reduce energy losses, and increase power efficiency in a wide range of applications, such as power electronics, due to their high breakdown voltage. GaN-HEMT devices are subject to long-term reliability due to the self-heating effect and lattice mismatch between the SiC substrate and the GaN. Depletion-mode GaN HEMTs are utilized for radio frequency applications, and this work investigates three wide-bandgap (WBG) GaN HEMT fixed-frequency oscillators with output buffers. The first GaN-on-SiC HEMT oscillator consists of an HEMT amplifier with an LC feedback network. With the supply voltage of 0.8 V, the single-ended GaN oscillator can generate a signal at 8.85 GHz, and it also supplies output power of 2.4 dBm with a buffer supply of 3.0 V. At 1 MHz frequency offset from the carrier, the phase noise is −124.8 dBc/Hz, and the figure of merit (FOM) of the oscillator is −199.8 dBc/Hz. After the previous study, the hot-carrier stressed RF performance of the GaN oscillator is studied, and the oscillator was subject to a drain supply of 8 V for a stressing step time equal to 30 min and measured at the supply voltage of 0.8 V after the step operation for performance benchmark. Stress study indicates the power oscillator with buffer is a good structure for a reliable structure by operating the oscillator core at low supply and the buffer at high supply. The second balanced oscillator can generate a differential signal. The feedback filter consists of a left-handed transmission-line LC network by cascading three unit cells. At a 1 MHz frequency offset from the carrier of 3.818 GHz, the phase noise is −131.73 dBc/Hz, and the FOM of the 2nd oscillator is −188.4 dBc/Hz. High supply voltage operation shows phase noise degradation. The third GaN cross-coupled VCO uses 8-shaped inductors. The VCO uses a pair of drain inductors to improve the Q-factor of the LC tank, and it uses 8-shaped inductors for magnetic coupling noise suppression. At the VCO-core supply of 1.3 V and high buffer supply, the FOM at 6.397 GHz is −190.09 dBc/Hz. This work enhances the design techniques for reliable GaN HEMT oscillators and knowledge to design high-performance circuits. Full article

A broadband, efficient monolithic microwave integrated circuit power amplifier (MMIC PA) in OMMIC’s 0.1 μm GaN-on-Si technology for 5G millimeter-wave communication is presented. This study concentrates on the output matching design, which has an important influence on the PA’s performance. A compact one-order synthesized transformer network (STN) is adopted to match the 50 Ω load to the extracted large-signal output model of the transistor. A dual-objective strategy is developed for parameter optimization, incorporating the impedance transformation trajectory inside the predefined optimal impedance domain (OID) that satisfies the required specifications, with approximation to selected optimal load impedances. By introducing a custom adjustment factor β into the error function, coupled with an automated iterative tuning process based on S-parameter simulations, desired broadband matching results can be rapidly achieved. The proposed two-stage PA occupies a small chip area of only 1.23 mm² and demonstrates good frequency consistency over the 24–31 GHz band. Continuous-wave characterization shows a flat small-signal gain of 19.7 ± 0.5 dB; both the output power (P_out) and the power-added efficiency (PAE) at the 4 dB compression point remain smooth, ranging from 32.3 to 32.7 dBm and 35.5% to 37.8%, respectively. The peak PAE reaches up to nearly 40% at the center frequency. Full article