III–V Compound Semiconductors and Devices, 2nd Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: 15 April 2025 | Viewed by 3105

Special Issue Editors


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Institute of Microelectronics, National Cheng Kung University, Tainan 70101, Taiwan
Interests: semiconductor devices and physics
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Guest Editor
Department of Electronic Engineering, I-Shou University, Kaohsiung 84001, Taiwan
Interests: metal-oxide-semiconductor technology; high-speed semiconductor devices; semiconductor manufacturing technology
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Special Issue Information

Dear Colleagues,

Compared to silicon technology, III-V compound semiconductors and their applications have attracted considerable attention for use in many different circuits such as power amplifiers, low-noise amplifiers, mixers, frequency converters, phase shifters, and optoelectronics.

This Special Issue of Micromachines aims to present recent advantages in the fabrication, characterization, and modeling of electron devices based on III-V compound semiconductors and devices. The scope of this Special Issue includes, but is not limited to:

  • Characterization techniques for defects in high-k dielectrics/III-V semiconductors.
  • Novel methods or concepts for III-V devices (e.g., HBT, field-effect transistors, nanowires, or gate-all-around).
  • Electronic or optoelectronic applications for III-V devices (including physical, chemical, and electronic properties).
  • Advanced fabrication processes for III-V on insulator (e.g., GaN on silicon or III-V on silicon).
  • Advanced simulation or modeling of III-V devices.

Prof. Dr. Yeong-Her Wang
Prof. Dr. Kuan-Wei Lee
Guest Editors

Manuscript Submission Information

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Keywords

  • compound semiconductor
  • high-k dielectric
  • insulator
  • frequency
  • optoelectronic

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Related Special Issue

Published Papers (2 papers)

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Research

13 pages, 2510 KiB  
Article
A High-Performance InGaAs Vertical Electron–Hole Bilayer Tunnel Field Effect Transistor with P+-Pocket and InAlAs-Block
by Hu Liu, Peifeng Li, Xiaoyu Zhou, Pengyu Wang, Yubin Li, Lei Pan, Wenting Zhang and Yao Li
Micromachines 2023, 14(11), 2049; https://doi.org/10.3390/mi14112049 - 31 Oct 2023
Cited by 3 | Viewed by 1169
Abstract
To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron–hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by [...] Read more.
To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron–hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P+-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In0.52Al0.48As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P+-pocket as well as the length and width of the In0.52Al0.48As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10−19 A/μm, on-state current of 1.04 × 10−4 A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs. Full article
(This article belongs to the Special Issue III–V Compound Semiconductors and Devices, 2nd Edition)
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16 pages, 4084 KiB  
Article
An Aging Small-Signal Model for Degradation Prediction of Microwave Heterojunction Bipolar Transistor S-Parameters Based on Prior Knowledge Neural Network
by Lin Cheng, Hongliang Lu, Silu Yan, Chen Liu, Jiantao Qiao, Junjun Qi, Wei Cheng, Yimen Zhang and Yuming Zhang
Micromachines 2023, 14(11), 2023; https://doi.org/10.3390/mi14112023 - 30 Oct 2023
Viewed by 1320
Abstract
In this paper, an aging small-signal model for degradation prediction of microwave heterojunction bipolar transistor (HBT) S-parameters based on prior knowledge neural networks (PKNNs) is explored. A dual-extreme learning machine (D-ELM) structure with an adaptive genetic algorithm (AGA) optimization process is used [...] Read more.
In this paper, an aging small-signal model for degradation prediction of microwave heterojunction bipolar transistor (HBT) S-parameters based on prior knowledge neural networks (PKNNs) is explored. A dual-extreme learning machine (D-ELM) structure with an adaptive genetic algorithm (AGA) optimization process is used to simulate the fresh S-parameters of InP HBT devices and the degradation of S-parameters after accelerated aging, respectively. In addition to the reliability parametric inputs of the original aging problem, the S-parameter degradation trend obtained from the aging small-signal equivalent circuit is used as additional information to inject into the D-ELM structure. Good agreement was achieved between measured and predicted results of the degradation of S-parameters within a frequency range of 0.1 to 40 GHz. Full article
(This article belongs to the Special Issue III–V Compound Semiconductors and Devices, 2nd Edition)
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