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12 pages, 2049 KiB

Open AccessArticle

An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers

by Xirui Hao, Yidong Yuan, Jie Pan, Zhaonan Lu, Shuang Song, Xiaopeng Yu and Menglian Zhao

Electronics 2024, 13(19), 3865; https://doi.org/10.3390/electronics13193865 - 29 Sep 2024

Viewed by 1132

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs. Full article

(This article belongs to the Special Issue Analog and Mixed Circuit: Design and Applications)

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17 pages, 6783 KiB

Open AccessArticle

A New Noise Shaping Approach for Sigma-Delta Modulators Using Two-Stage Feed-Forward Delays and Hybrid MASH-EFM

by Khalid Ijaz, Muhammad Adnan, Waqas Tariq Toor, Muhammad Asim Butt, Muhammad Idrees, Usman Ali, Izaz Hassan, Yazeed Yasin Ghadi, Fuad A. Awwad, Mohamed R. Abonazel and Syed Rehan Ashraf

Electronics 2023, 12(3), 740; https://doi.org/10.3390/electronics12030740 - 1 Feb 2023

Cited by 1 | Viewed by 3446

Abstract

Sigma-delta modulators use a noise-shaping technique to curtail the noise power in the band of interest during digital-to-analog conversion. Error feedback modulator employs an efficient noise transfer function for time varying inputs than any other sigma-delta modulators. However, the efficiency of the conventional noise transfer function degrades and the quantizer saturation issue provokes when the input signal reaches to full scale. This work proposes a new noise transfer function which is a combination of transfer functions of two-stage Feed-forward delays and a novel Hybrid multi-stage noise shaping-error feedback sigma-delta modulator. The noise transfer function of two-stage Feed-forward delays mitigates the concern of quantizer saturation. The noise transfer function offered by the Hybrid multi-stage noise shaping-error feedback architecture provides sustainable solutions to limit cycles and idle tones. The simulation concludes that the proposed noise-shaping approach obtains comparatively high signal-to-quantization noise ratio than the conventional error feedback modulators. Other performance parameters like spurious-free dynamic range, effective number of bits and signal-to-noise plus distortion ratio are also significantly improved. Full article

(This article belongs to the Special Issue Deep Learning and Its Applications in Image Reconstruction)

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20 pages, 2387 KiB

Open AccessArticle

A 121 dB SNDR Zoom ADC Using Dynamic Amplifier and Asynchronous SAR Quantizer

by Yangchen Jia, Jiangfei Guo and Guiliang Guo

Electronics 2023, 12(2), 313; https://doi.org/10.3390/electronics12020313 - 7 Jan 2023

Cited by 4 | Viewed by 3749

Abstract

This paper presents a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It uses a coarse-conversion 5-bit asynchronous self-timed SAR ADC combined with a fine-conversion second-order delta-sigma modulator to efficiently obtain a high signal-to-noise distortion ratio (SNDR). An integrator circuit using a high-gain dynamic amplifier is proposed to achieve higher SNDR. The dynamic amplifier uses a switched tail current source to operate periodically, simplifying the common-mode feedback circuit, reducing unnecessary static current, and improving the PVT robustness. Dynamic error correction techniques, such as redundancy, chopping, and dynamic element matching (DEM) are used to achieve low offset and high linearity. And a 2-bit asynchronous SAR quantizer with an embedded feed-forward adder is used in the second-order delta-sigma modulator to reduce the quantization noise caused by redundancy, and further achieve higher energy efficiency. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth at a 200 kHz sampling clock while consuming only 170

$μ$ W from a 2.5 V supply and the core area is 0.55 mm

$^{2}$ . This results in a Schreier figure of merit (FoM) of 184.7 dB. Full article

(This article belongs to the Section Circuit and Signal Processing)

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17 pages, 2718 KiB

Open AccessArticle

Frequency-Modulated Signal Measurement Using Closed-Loop Methodology

by Xinglin Sun, Haojie Wu, Xinyue Tan, Wenrui Wang, Lingyun Ye and Kaichen Song

Sensors 2022, 22(20), 7822; https://doi.org/10.3390/s22207822 - 14 Oct 2022

Cited by 7 | Viewed by 2174

Abstract

Frequency-modulated (FM) signals are widely used in sensing, measurement, and signal detection due to their strong anti-interference and easy transmission characteristics. Although the high-precision measurement methods for static signals are quite complete, the high-precision measurement methods for dynamic FM signals still need to be studied, and the measurement accuracy in the high-sampling system still has room for improvement. Traditionally, the equal-precision measurement method is widely applied in most scenarios. However, its accuracy is limited by the quantization error of ±1 word and the sampling gate time, making it difficult to improve the frequency measurement accuracy while ensuring a high sampling rate at the same time. In this paper, a high-precision feedback frequency measurement system with the capability to eliminate the quantization error of ±1 word is proposed. The proposed system consists of two stages, the rough measurement stage based on the equal-precision measurement method and the precise measurement stage based on the negative feedback tracking architecture using the phase–frequency detector (PFD) and direct digital synthesizer (DDS). The effectiveness and feasibility of the system are verified by both simulation and experiment. At the sampling rate of 2 kHz, the frequency measurement accuracy is improved by more than 30 dB. Full article

(This article belongs to the Special Issue Electronic Test and Measurement Instrumentation: Design and Applications)

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18 pages, 5934 KiB

Open AccessArticle

A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes

by Risheng Lv, Weiping Chen and Xiaowei Liu

Micromachines 2018, 9(8), 372; https://doi.org/10.3390/mi9080372 - 27 Jul 2018

Cited by 8 | Viewed by 4649

Abstract

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm². Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB. Full article

(This article belongs to the Section A：Physics)

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