Search Results (4)

Magnetoresistive random-access memory (MRAM), as a promising non-volatile memory technology, has attracted extensive research interest owing to its unique combination of high operating speed, exceptional endurance, low standby power consumption, and CMOS process compatibility. In this review, we provide a comprehensive overview of the technological evolution of MRAM, spanning from Toggle-MRAM to spin-transfer torque (STT)-MRAM and then to spin–orbit torque (SOT)-MRAM. The working mechanisms, performance trade-offs, and integration potential of each generation are systematically summarized. Furthermore, the diverse applications of MRAM—including embedded systems-on-chip (SoCs), edge computing, aerospace and automotive electronics, artificial intelligence accelerators, neuromorphic computing, and hardware-level security—are thoroughly discussed. We also identify key challenges hindering large-scale commercialization, such as the trade-off between write energy and speed, process complexity, storage density constraints, and cost competitiveness. Finally, emerging research directions are proposed, emphasizing short-term priorities such as write current reduction and yield improvement, as well as long-term development strategies focusing on material–device–algorithm co-optimization and ecosystem establishment. Full article

As an emerging type of non-volatile memory, magneto-resistive random access memory (MRAM) stands out for its exceptional reliability and rapid read–write speeds, thereby garnering considerable attention within the industry. The memory cell architecture of MRAM is centered around the magnetic tunnel junction (MTJ), which, however, is prone to interference from external magnetic fields—a limitation that restricts its application in demanding environments. To address this challenge, we propose an innovative open magnetic shielding structure. This design demonstrates remarkable shielding efficacy against both in-plane and perpendicular magnetic fields, effectively catering to the magnetic shielding demands of both spin-transfer torque (STT) and spin–orbit torque (SOT) MRAM. Finite element magnetic simulations reveal that when subjected to an in-plane magnetic field of 40 mT, the magnetic field intensity at the chip level is reduced to nearly 1‰ of its original value. Similarly, under a perpendicular magnetic field of 40 mT, the magnetic field at the chip is reduced to 2‰ of its initial strength. Such reductions significantly enhance the anti-magnetic capabilities of MRAM. Moreover, the magnetic shielding performance remains unaffected by the height of the packaging structure, ensuring compatibility with various chip stack packaging requirements across different layers. The research presented in this paper holds immense significance for the realization of highly reliable magnetic shielding packaging solutions for MRAM. Full article

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (V_DD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal V_DD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75× sensing time. Full article

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) technology is considered to be the most promising nonvolatile memory (NVM) solution for high-speed and low power applications. Dual MgO-based composite free layers (FL) have driven the development of STT-MRAMs over the past decade, achieving data retention of 10 years at the cost of higher write power consumption. In addition, the need for tunnel magnetoresistance (TMR)-based read schemes limits the flexibility in materials beyond the typical CoFeB/MgO interfaces. In this study, we propose a novel spacerless FL stack comprised of CoFeB alloyed with heavy metals such as tungsten (W) which allows effective modulation of the magnet properties (M_s, H_k) while retaining compatibility with MgO layers. The addition of W results favours a delayed crystallization process, in turn enabling higher thermal budgets up to 180 min at 400 °C. The presence of tungsten reduces the total FL magnetization (M_s) but simultaneously increasing its temperature dependence, thus, enabling a dynamic write current reduction of ~15% at 2 ns pulse widths. Reliable operation is demonstrated with a WER of 1 ppm and endurance >10¹⁰ cycles. These results pave the way for alternative designs of STT-MRAMs for low power electronics. Full article