A Single-Stage Asymmetrical Half-Bridge Flyback Converter with Resonant Operation

Abstract

This paper proposes a single-stage asymmetrical half-bridge fly-back (AHBF) converter with resonant mode using dual-mode control. The presented converter has an integrated boost converter and asymmetrical half-bridge fly-back converter and operates in resonant mode. The boost-cell always operates in discontinuous conduction mode (DCM) to achieve high power factor. The presented converter operates simultaneously using a variable-frequency-controller (VFC) and pulse-width-modulation (PWM) controller. Unlike the conventional single-stage design, the intermediate bus voltage of this controller can be regulated depending on the main power switch duty ratio. The asymmetrical half-bridge fly-back converter utilizes a variable switching frequency controller to achieve the output voltage regulation. The asymmetrical half-bridge fly-back converter can achieve zero-voltage-switching (ZVS) operation and significantly reduce the switching losses. Detailed analysis and design of this single-stage asymmetrical half-bridge fly-back converter with resonant mode is described. A wide AC input voltage ranging from 90 to 264 V_rms and output 19 V/120 W prototype converter was built to verify the theoretical analysis and performance of the presented converter.

1. Introduction

A conventional power supply was designed with a two-stage scheme that can be divided into two parts. The first stage achieves power-factor-correction (PFC) to reduce the input current harmonics. The second stage is a DC/DC converter that regulates the output voltage. However, the two-stage scheme has several defects, such as high cost and power supply system complexity. In recent years, a single-stage scheme was proposed [1,2,3,4,5] that integrates a boost stage and a DC/DC stage to share a common switch. The boost-cell stage operates in discontinuous conduction mode (DCM) to provide high power factor while the DC/DC stage can be responsible for output voltage regulation. Unfortunately, the single-stage scheme presents major problems in which the intermediate bus voltage cannot be regulated, such as the boost integrated flyback rectifier energy DC/DC (BIFRED) converter, single-stage fly-back converter and single-stage LLC resonant converter [6,7,8,9,10]. When voltage is input for universal applications, the intermediate bus voltage could be as high as 1000 V, causing difficulty in selecting converter components, with voltage stress issues throughout the capacitors and switches. The wide intermediate bus voltage variation will cause output voltage regulation design difficulty and also cause lower conversion efficiency though the DC/DC stage. The single-stage scheme intermediate bus voltage cannot be regulated at light loads and universal input voltage. The zero-voltage-switching (ZVS) fly-back converters have been used widely in industry and are suitable for low-to-medium power applications, such as LED-driver and desktop computer power supplies. Various kinds of ZVS schemes have been proposed, such as the active-clamp network and asymmetrical half-bridge circuit [11,12]. The active-clamp fly-back converter [13] employs the active clamp network to achieve ZVS operation; however, the voltage stresses on the switches are greater than input voltage which will cause high conduction losses in the power switches. The asymmetrical half-bridge fly-back converter (AHBF) with resonant mode [14,15,16,17,18,19,20] was developed to achieve ZVS and reduce the voltage stresses on the switches to less than that of the active-clamp fly-back converter, so the power density and conversion efficiency can be effectively increased. Furthermore, it can operate under changed duty cycles or variable switching frequencies for regulated output voltage.

This paper proposes a new single-stage asymmetrical half-bridge fly-back converter with resonant mode. The proposed converter integrates a boost converter and an asymmetrical half-bridge fly-back converter with resonant mode using dual-mode control. The converter intermediate bus voltage can be regulated by the pulse-width-modulation control (PWM). The variable-frequency-controller (VFC) can regulate the converter output voltage. Therefore, this proposed converter can operate in universal input voltage and solves the voltage stress issues throughout the capacitors and switches. The proposed converter utilizes the ZVS technique to decrease the switching losses, resulting in high conversion efficiency. The operational principle for the proposed converter is analyzed, a prototype converter with AC input voltage of 90–264 V_rms and output voltage/current of 19 V/8 A is built to verify the analytical results.

2. Circuit Description and Principle Operation of Proposed Converter

Figure 1 shows the circuit configuration for the single-stage asymmetrical half-bridge fly-back converter with resonant mode. The primary switches Q₁ and Q₂ operate at asymmetrical duty ratio. D_b1 and D_b2 are the anti-paralleled power MOSFETs. The primary side diode D_in is a braking diode. The L_boost is a boost-cell inductor. The resonant inductor L_r, resonant capacitor C_r and magnetizing inductor L_m for are the resonant tank for the asymmetrical half-bridge fly-back converter. The secondary diode D_r is a rectifier diode, the C_bus is boost cell output capacitor and C_O is the asymmetrical half-bridge fly-back converter output capacitor.

The following assumptions were made to analyze the proposed single-stage asymmetrical half-bridge fly-back converter:

-

These conduction losses of all switches, diodes and layout traces, and the copper losses of the transformer are neglected.

-

The turn ratio of the transformer windings is n = N₁/N₂.

-

The resonant inductor L_r is composed of a leakage inductor and external inductor, where L_r = L_eakage + L_ex.

-

The conduction times for Q₁ are (1 − D)T_s and Q₂ is DT_s, respectively, where D is the duty cycle for Q₂, and T_s denotes the switching period. In addition, the dead time is much smaller than that other of conduction times.

-

In the steady state the bus capacitance C_bus and output capacitance C_O are large enough so that the bus voltage V_bus and output voltage V_O are a constant value.

Both the boost-cell stage and asymmetrical half-bridge fly-back converter stage share the common switches Q₁ and Q₂, and furthermore there is bus capacitor C_bus between the two stages. The boost-cell stage was presented in [21]. When the switch Q₂ is turned on and the switch Q₁ is turned off, this results in a positive voltage V_Lboost = V_IN across the inductor L_boost causing a linear increase in the inductor current i_Lboost. Conversely, when the switch Q₁ is turned on and the switch Q₂ is turned off, the inductor L_boost is releases energy to the bus capacitor C_bus. Therefore, from the flux-balance of L_boost under the steady-state, V_bus can be determined as:

$$\frac{V_{bus}}{V_{IN}}=\frac{1}{2}+\frac{\sqrt{1+2\cdot \frac{D^2\cdot R_{Lbus}}{L\cdot f_s}}}{2}$$

(1)

In the DC/DC stage, when the switch Q₁ is turned on, the intermediate bus voltage V_bus will charge C_r, L_r and L_m. Conversely, when the switch Q₂ is turned on, the secondary diode D_r conducts and L_m is releases energy to the output load. When the asymmetrical half-bridge fly-back converter operates in resonant mode, the voltage transfer ratio can be expressed as:

$$M=\frac{n{V}_O}{V_{bus}}=\frac{\left(1-D\right)\cdot \frac{1-\cos \left[{\omega }_r\cdot \left(\frac{D}{f_s}\right)\right]}{Z_r\cdot {\omega }_r}}{\frac{1-D}{{\omega }_r}\left[\frac{1}{n^2{R}_o}+\frac{D}{2L_m{f}_s}\right]\cdot \sin \left[{\omega }_r\cdot \left(\frac{D}{f_s}\right)\right]+\frac{{\left(1-D\right)}^2}{n^2{R}_o{f}_s}+\frac{1-\cos \left[{\omega }_r\cdot \left(\frac{D}{f_s}\right)\right]}{Z_r\cdot {\omega }_r}}$$

(2)

where:

$${\omega }_r=\frac{1}{\sqrt{C_r\cdot L_r}}$$

(3)

$$Z_r=\sqrt{\frac{L_r}{C_r}}$$

(4)

From Equation (2), the voltage transfer ratio of the asymmetrical half-bridge fly-back converter includes relation between the duty ratio D and switching frequency f_s simultaneously. Figure 2 shows the relation between the duty ratio D, switching frequency f_s and voltage transfer ratio. It shows that when the duty-ratio D is decreased from 0.35 to 0.65, to maintain fixed voltage gain, the switching frequency can shift from f_c to f_a correspondingly. However, Figure 2 also shows that when the switching frequency f_s or duty ratio D decreases the voltage gain will be increased. In contrast, when the switching frequency f_s or duty ratio D increase, the voltage gain will be decreased.

From Figure 1, the resistors R₃ and R₄ can measure output voltage V_bus and it can be to through the compensator, which is composed of C₂, R₆ and operational amplifier (OPA). The output voltage of compensator can provide a DC level for PWM + VFC controller, so that the duty ratio can be changed according to V_bus. On the other hand, the Q₂ is the boost-cell stage main switch, therefore the intermediate bus voltage V_bus is regulated by the D to Q₂ duty ratio. Unfortunately, changing the D to Q₂ duty ratio will affect the asymmetrical half-bridge fly-back converter output voltage. For example, when the D to Q₂ duty ratio is increased, the asymmetrical half-bridge fly-back converter output voltage will decrease. Conversely, when the D to Q₂ duty ratio is decreased, the asymmetrical half-bridge fly-back converter output voltage will increase. To overcome the change in D to Q₂ duty ratio causing unstable asymmetrical half-bridge fly-back converter output voltage, a VFC has been added to the feedback control loop.

From the section of V_O-feedback of Figure 1, the resistors R₁ and R₂ can measure output voltage V_O, and the feedback-voltage can be to through the compensator, which is composed of C₁, R₅ and OPA. Therefore, the output of OPA will adjust Q_SW at basis-terminal voltage, so that the oscillator can be changed the frequency of saw-tooth wave in output-terminal. When the asymmetrical half-bridge fly-back converter output voltage is decreased, the switching frequency f_s will decrease to provide larger voltage gain for regulated output voltage. Conversely, when the output voltage is increased, the switching frequency f_s will be increased to provide lower voltage gain. According to the above analysis, the intermediate bus voltage V_bus and output voltage V_O of the proposed converter can be regulated simultaneously from the PWM control and VFC.

Figure 3 depicts the key waveforms of the proposed single-stage asymmetrical half-bridge fly-back converter with resonant mode. Six states are required to complete a switching cycle. The conduction paths for each operating state are illustrated in Figure 4.

Mode 1 [t₀, t₁]:

As shown in Figure 4, Q₂ is turned on with the ZVS operating condition. In the meantime the rectifier diode D_r is conducted and the energies stored in the transformer magnetizing inductors are transferred to the output load. The output voltage is reflected to the primary side, therefore, the primary transformer is clamped to −nV_O, and i_Lm decreases linearly. During this period, the resonant inductor L_r and resonant capacitor C_r begin to resonate. On the other hand, the diode D_in is conducted and the voltage across the input inductor L_boost is equal to the input voltage V_IN so the input inductor current i_Lboost increases linearly. The input current i_Lboost can be expressed as:

$$i_{Lboost}\left(t\right)=\frac{V_{bus}}{L_{boost}}\left(t-t_0\right)$$

(5)

The resonant inductor current i_Lr and the resonant capacitor voltage v_Cr are given as:

$$i_{Lr}\left(t\right)=i_{Lr}\left(t_0\right)\cdot \cos \left[{\omega }_r\left(t-t_0\right)\right]-\frac{v_{Cr}\left(t_0\right)+n{V}_o}{Z_r}\cdot \sin \left[{\omega }_r\left(t-t_0\right)\right]$$

(6)

$$v_{Cr}\left(t\right)=n{V}_O+\left[v_{Cr}\left(t_0\right)+n{V}_O\right]\cdot \cos \left[{\omega }_r\left(t-t_0\right)\right]+Z_r{i}_{Lr}\left(t_0\right)\cdot \sin \left[{\omega }_r\left(t-t_0\right)\right]$$

(7)

The magnetizing current i_Lm of transformer can be expressed as

$$i_{Lm}\left(t\right)=i_{Lm}\left(t_0\right)-\frac{n{V}_O\left(t-t_0\right)}{L_m}$$

(8)

This interval is ended when i_Lr equals i_Lm at t₁.

Mode 2 [t₁, t₂]:

At time t₁ the input inductor current i_Lboost increases linearly. The resonant inductor current i_Lr is the same as the magnetizing current i_Lm therefore, no current is transferred to the secondary side so the rectifier diode D_r is turned off. During this mode, the resonant circuit is composed of C_r, L_r and L_m. Moreover, L_m is equal to series with L_r and L_m is much larger than L_r, so that the resonant cycle is much longer than the previous state. The i_Lm, i_Lr and v_Cr are expressed as:

$$i_{Lr}\left(t\right)=i_{Lr}\left(t_1\right)\cdot \cos \left[{\omega }_{r2}\left(t-t_1\right)\right]-{\omega }_{r2}{C}_r{v}_{cr}\left(t_1\right)\cdot \sin \left[{\omega }_{r2}\left(t-t_1\right)\right]$$

(9)

$$\begin{array}{ll}{v}_{Cr}\left(t\right)=& v_{Cr}\left(t_1\right)\cdot \cos \left[{\omega }_{r2}\left(t-t_1\right)\right]+L_m{i}_{Lr}\left(t_1\right){\omega }_{r2}\cdot \sin \left[{\omega }_{r2}\left(t-t_1\right)\right]\\ & +L_r{i}_{Lr}\left(t_1\right){\omega }_{r2}\cdot \sin \left[{\omega }_{r2}\left(t-t_1\right)\right]\end{array}$$

(10)

$$i_{Lm}\left(t\right)=i_{Lr}\left(t\right)$$

(11)

here:

$${\omega }_{r2}=\frac{1}{\sqrt{C_r\cdot \left(L_m+L_r\right)}}$$

(12)

When Q₂ is turned off this interval is ended.

Mode 3 [t₂, t₃]:

The mode begins when Q₂ is turned off at t = t₂. The magnetizing current i_Lm charges the Q₂ junction capacitors and discharges the Q₁ junction capacitors until the Q₂ junction capacitors equal V_bus and the Q₁ body diode conducts. Therefore, at time t₃, Q₁ can be turned on to achieve ZVS. During this period, which is used to allow enough time to achieve ZVS, as well as prevent shoot through in the two switches, the i_Lr and v_Cr are expressed as

$$i_{Lr}\left(t\right)=i_{Lr}\left(t_2\right)\cdot \cos \left[{\omega }_{r1}\left(t-t_2\right)\right]-{\omega }_{r2}{C}_r{v}_{cr}\left(t_1\right)\cdot \sin \left[{\omega }_{r1}\left(t-t_2\right)\right]$$

(13)

$$v_{Cr}\left(t\right)=\frac{i_{Lr}\left(t_2\right)}{{\omega }_{r1}{C}_r}\cdot \sin \left[{\omega }_{r1}\left(t-t_2\right)\right]+v_{cr}\left(t_2\right)\cdot \cos \left[{\omega }_{r1}\left(t-t_2\right)\right]$$

(14)

where:

$${\omega }_{r1}=\frac{1}{\sqrt{\left(L_m+L_r\right)\cdot \left(C_{eq}\left|\right|C_r\right)}}{C}_{oss1}=C_{oss2};C_{eq}=C_{oss1}=C_{oss2}$$

(15)

The input current i_Lboost can be expressed as:

$$i_{Lboost}\left(t\right)=-\frac{V_{IN}-V_{bus}}{L_{boost}}\left(t-t_2\right)$$

(16)

Mode 4 [t₃, t₄]:

In this state, Q₁ is turned on which carries the resonant inductor current i_Lr and input inductor current i_Lboost. The voltage across the input inductor L_boost is about (V_IN − V_bus) so the input inductor current i_Lboost linearly decreasing. Referring to Figure 4d, the rectifier diode D_r is reverse-biased and in the meantime the input energy is stored in the primary magnetizing inductance L_m, while the output capacitors C_O provide energy to the output load. The resonant inductor current i_Lr, magnetizing inductance current i_Lm and resonant capacitors voltage v_Cr can be expressed as:

$$\begin{array}{ll}{i}_{Lr}\left(t\right)=& i_{Lr}\left(t_3\right)\cdot \cos \left[{\omega }_{r2}\left(t-t_3\right)\right]+{\omega }_{r2}{C}_r{v}_{bus}\cdot \sin \left[{\omega }_{r2}\left(t-t_3\right)\right]\\ & -{\omega }_{r2}{C}_r{v}_{cr}\left(t_3\right)\cdot \sin \left[{\omega }_{r2}\left(t-t_3\right)\right]\end{array}$$

(17)

$$\begin{array}{ll}{v}_{Cr}\left(t\right)=& v_{cr}\left(t_3\right)+i_{Lr}\left(t_3\right)\cdot \cos \left[{\omega }_{r2}\left(t-t_3\right)\right]+{\omega }_{r2}{C}_r{v}_{bus}\cdot \sin \left[{\omega }_{r2}\left(t-t_3\right)\right]\\ & -{\omega }_{r2}{C}_r{v}_{cr}\left(t_3\right)\cdot \sin \left[{\omega }_{r2}\left(t-t_3\right)\right]\end{array}$$

(18)

$$i_{Lm}\left(t\right)=i_{Lr}\left(t\right)$$

(19)

The input current i_Lboost are given as:

$$i_{Lboost}\left(t\right)=-\frac{V_{IN}-V_{bus}}{L_{boost}}\left(t-t_3\right)$$

(20)

When input current i_Lboost reach zero level, this interval is ended.

Mode 5 [t₄, t₅]:

During this stage, Q₁ remains turned on so that the direction of i_Lr is reversed. As with Stage 4 the primary magnetizing inductance L_m stores energy and the output capacitors C_O continue to provide energy through the output load. The current in L_boost stays at zero (DCM operation) so the PFC feature can be achieved. In the meantime, diode D_in is in reverse bias. The resonant inductor current i_Lr, magnetizing inductance current i_Lm and the resonant capacitor voltage v_Cr are given as:

$$\begin{array}{ll}{i}_{Lr}\left(t\right)=& i_{Lr}\left(t_4\right)\cdot \cos \left[{\omega }_{r2}\left(t-t_4\right)\right]+{\omega }_{r2}{C}_r{v}_{bus}\cdot \sin \left[{\omega }_{r2}\left(t-t_4\right)\right]\\ & -{\omega }_{r2}{C}_r{v}_{cr}\left(t_4\right)\cdot \sin \left[{\omega }_{r2}\left(t-t_4\right)\right]\end{array}$$

(21)

$$\begin{array}{ll}{v}_{Cr}\left(t\right)=& v_{cr}\left(t_4\right)+i_{Lr}\left(t_4\right)\cdot \cos \left[{\omega }_{r2}\left(t-t_4\right)\right]+{\omega }_{r2}{C}_r{v}_{bus}\cdot \sin \left[{\omega }_{r2}\left(t-t_4\right)\right]\\ & -{\omega }_{r2}{C}_r{v}_{cr}\left(t_4\right)\cdot \sin \left[{\omega }_{r2}\left(t-t_4\right)\right]\end{array}$$

(22)

$$i_{Lm}\left(t\right)=i_{Lr}\left(t\right)$$

(23)

where:

$${\omega }_{r2}=\frac{1}{\sqrt{C_r\cdot \left(L_m+L_r\right)}}$$

(24)

When Q₁ turned off, this interval is ended.

Mode 6 [t₅, t₆]:

In this stage, Q₁ and Q₂ are turned off and the input current i_Lboost remains at zero, while the output capacitors continue to provide energy through the output load. At this interval, the resonant current i_Lr charges the Q₁ junction capacitors and discharges the Q₂ junction capacitors. When Q₁ equals V_bus and the body diode across Q₂ conducts, this interval is ended and the operating state returns to Stage 1 to begin the next switching cycle. The resonant inductor current i_Lr, magnetizing inductance current i_Lm and resonant capacitor voltage v_Cr can be expressed as:

$$i_{Lr}\left(t\right)=i_{Lr}\left(t_5\right)\cdot \cos \left[{\omega }_{r1}\left(t-t_5\right)\right]+{\omega }_{r1}{C}_r{v}_{Cr}\left(t_5\right)\cdot \sin \left[{\omega }_{r1}\left(t-t_5\right)\right]$$

(25)

$$v_{Cr}\left(t\right)=\frac{I_{Lr}\left(t_5\right)}{{\omega }_{r1}{C}_r}\cdot \sin \left[{\omega }_{r1}\left(t-t_5\right)\right]+v_{Cr}\left(t_5\right)\cdot \cos \left[{\omega }_{r2}\left(t-t_5\right)\right]$$

(26)

$$i_{Lm}\left(t\right)=i_{Lr}\left(t\right)$$

(27)

When Stage 6 ends the operating state returns to Stage 1 and the next switching cycle begins.

3. Circuit Design for the Proposed Converter

D_max is the maximum duty cycle for the proposed converter. For to achieve high power-factor the input inductor current must be operated in DCM so the input inductor L_boost can be expressed as:

$$L_{boos}<\frac{V_{bus}{T}_s}{2\cdot i_{IN\mathrm{peak}}{f}_{s\min }}\cdot (D_{\max })\cdot {\left(1-D_{\max }\right)}^2$$

(28)

where i_{IN peak} is the maximum peak-current of the input inductor L_boost, and f_smin is the lowest switching frequency for the proposed converter. From Equation (25), when L_m is greater than the resonant inductor L_r, the voltage gain can be approximated as:

$$V_O=\frac{1}{n}{V}_{bus}\cdot \left(1-D\right)$$

(29)

Therefore, the turn ratio of the transformer primary winding to secondary winding can be equal to:

$$n=\frac{V_{bus}}{V_O}\cdot \left(1-D\right)$$

(30)

At t = t₃, to ensure the ZVS operation for Q₁, the magnetizing inductance current i_Lm must discharge the C_oss1 until the voltage is equal to zero so the minimum i_Lm at t₃ can be given as

$$i_{Lm\left(t_3\right)\min }=\frac{n{V}_O}{2L_m}\cdot D_{\min }{T}_s$$

(31)

According to Equation (28), the maximum magnetizing inductance L_m can be expressed as:

$$L_{m\left(t_3\right)\max }=\frac{n{V}_O\cdot t_{dead}}{2\cdot V_{bus}\left(C_{oss1}+C_{oss2}\right)\cdot f_s}\cdot D_{\min }$$

(32)

On the other hand, at t = t₆, to ensure ZVS operation for Q₂, the magnetizing inductance current i_Lm must discharge C_oss2 until the voltage is equal to zero so the minimum i_Lm at t₆ can be given as:

$$i_{Lm\left(t_6\right)\min }=\frac{n{V}_O}{2\cdot L_m\cdot f_s}\cdot (1-D_{\max })$$

(33)

According to Equation (30), the maximum magnetizing inductance L_m can be expressed as:

$$L_{m\left(t_6\right)\max }=\frac{n{V}_O\cdot t_{dead}}{2\cdot V_{bus}\left(C_{oss1}+C_{oss2}\right)\cdot f_s}\cdot (1-D_{\max })$$

(34)

From Figure 4a, the resonant capacitor C_r and the resonant inductor L_r are resonating from t₀ to t₁, this time interval is during the Q₂ turn-on time, which is about half the resonant period and can be approximately expressed as:

$$C_r\le \frac{{\left(\frac{2\cdot D_{\max }}{{\omega }_r}\right)}^2}{L_r}$$

(35)

The output filter capacitance C_O can be calculated as:

$$C_O\ge \frac{\frac{P_O}{V_O}\cdot \left(1-D_{\max }\right)}{\mathsf{\Delta }{V}_O\cdot f_s}$$

(36)

where f_s is the switching frequency and △V_O is the output voltage ripple. The voltage stresses of Q₁ and Q₂ are equal to V_bus. The voltage stresses of the secondary diode D_r is:

$$D_r=\frac{D_{\max }\cdot V_{bus}}{n}+V_O$$

(37)

The peak secondary diode current is expressed as:

$$I_{Dr,\max }=\frac{\pi }{2\cdot \left(1-D_{\max }\right)}\cdot I_O$$

(38)

4. Experimental Results

In order to verify the feasibility of the proposed converter, a 120 W prototype converter is built in the laboratory. Figure 5 shows the proposed converter and the experimental parameters are designed in

Table 1. Experimental parameters of the proposed converter.

Parameters	Value
Input ac voltage range:	85–264 Vrms
Output voltage:	VO = 19 V
Output voltage ripple:	△VO = 0.95 V
Intermediate bus voltage:	Vbus = 420 V
Maximum output current:	IO = 6.32 A
Input inductor:	Lboost = 200 µH
Magnetizing inductance:	Lm = 450 µH
Turns ratio:	n = Np/Ns = 3T
Resonant inductor:	Lr = 100 µH
Maximum duty cycle:	Dmax = 0.75
Resonant capacitors:	Cr = 40 nF
Switching frequency:	fs = 60–150 kHz
Output capacitor:	CO = 1200 µF

.

A PQ26/20 TDK core is used for the input inductor. The PQ32/30 core is used for the isolation transformer and the transformer turn ratio is calculated from Equation (26). The magnetizing inductance L_m is designed from Equation (29) at approximately 450 µH. The IPP60R99 MOSFET is used producing output capacitance C_OSS of about 130 pF at a 430 V drain-to-source voltage, including the output capacitances of Q₁ and Q₂ it is about 260 pF. Therefore, to ensure ZVS operations, 330 ns dead time was inserted between the Q₁ and Q₂ gate signals. The resonant frequency f_r is placed at about 80 kHz so the resonant capacitor C_r and resonant inductor L_r can be calculated from Equation (32). The output voltage ripple △V_O is required to be smaller than 0.95 V. The output capacitor C_O is calculated to be greater than 474 µF from Equation (33). Therefore, a 1200 µF output capacitor is used.

Figure 6 shows the experimental results for v_GS1, v_GS2, i_Lboost and i_Lr at different output currents and at V_In,main. Referring to Figure 3, six operation states can be observed in Figure 6. When Q₁ is turned on and Q₂ is turned off, the i_Lboost linearly decreases and i_Lr linearly increases. When Q₁ and Q₂ are turned off, ZVS operation can be achieved. During the Q₁ turned off and Q₂ turned on period, the i_Lboost increases linearly and the resonant inductor L_r and resonant capacitor begin to resonate. On the other hand, Figure 6 also shows that when the output load increases from light load to full load, the duty ratio of Q₂ increases from 0.5 to 0.75 for regulated bus voltage V_bus, and the switching frequency decreases from about 125 kHz to 62 kHz for regulated output voltage V_O. Figure 7 shows the measured input voltage v_ac, input current i_ac and input inductor current i_Lboost under full load conditions. The input current near sinusoidal waveform and input inductor current are shown operated in DCM so that high power factor can be achieved.

Figure 8 shows the gate-to-source waveforms and drain-to-source voltages for primary switches Q₁ and Q₂ at the full-load. The waveform shows that V_DS1 and V_DS2 reach zero levels after Q₁ and Q₂ are turned on. Therefore, ZVS conduction is achieved so that overall conversion efficiency is increased. The transient output voltage V_O during a step load current from 1.6 to 6.3 A and from 6.3 to 1.6 A are shown in Figure 9 when input voltage of 230 V_rms, which shows that V_O can still be regulated. Figure 10 depicts the bus voltage variation under 25%, 50%, 75% and 100% load condition and the bus voltage is regulated around 430 V. Figure 11 also depicts the input current power factor. It indicates that the power factor is greater than 0.9 at different load conditions. Figure 12 shows the measured efficiencies of the proposed single stage asymmetrical half-bridge fly-back converter through different outputs. The average efficiency is around 86% above which the rated full load efficiency is about 90%.

Table 2. Comparison to the other published methods.

	Proposed Converter	2005 [14]	2012 [15]	2014 [17]
Input Voltage	90–264 Vrms	180–265 Vrms	180–270 Vrms	180–265 Vrms
Output Voltage	19 V	24 V	24 V	24 V
Switching Frequency	60–150 kHz	100 kHz	99–119 kHz	100 kHz
Efficiency	90%	91%	91.5%	92%
Power Factor	98%	99%	None	99%
ZVS/ZCS	Yes	Yes	Yes	Yes
Control Techniques for power factor	VCF and PWM	Coupled Inductor	Frequency Compensator	PWM
Cost	Low	High	Middle	High

shows the comparison among the converters proposed in [14,15,17]. Compared with the input voltage range, this presented converter can be operated in universal-voltage, and other converter just can operate in high-line voltage situations. Moreover, this proposed converter has the lowest component cost because it does not need an additional power-device or inductor for a high PF. Figure 13 shows the prototype of the proposed converter.

5. Conclusions

This paper presented a single stage asymmetrical half-bridge fly-back converter with resonant mode. The switches operate simultaneously in the variable-frequency-controller (VFC) and pulse-width-modulation (PWM) control to regulate the bus voltage and output voltage. The operating modes in a complete switching cycle were analyzed and discussed in detail. The key equations were derived and the design procedures formulated. The experimental results on an AC input voltage 90 to 264 V_rms with output 120 W prototype were recorded to verify the theoretical scheme. The measured results show that the power factor is above 0.9, the average efficiency is around 86% and the highest conversion efficiency is about 90%. The proposed single stage asymmetrical half-bridge fly-back converter is especially suitable for low-to-medium power level applications.