Development and Application of New CMOS Devices

Dear Colleagues,

The development of complementary metal–oxide semiconductor (CMOS) technology enabled the very wide use of advanced technology devices for a number of various applications: mm-Wave circuits, front end 60 GHz receivers, 5G communication circuits, low-noise amplifiers (LNAs), including cryogenics for deep space antenna areas, stacked transistor power amplifiers (PAs), nano-electro-mechanical switches for computing applications, artificial intelligence applications, biosensors for environmental sensing, safety monitoring and clinical diagnosis, temperature sensing, CMOS–memristor hybrid circuits, RF cryogenic oscillators, THz frequency signal detection sensors, W-band ring oscillators and others. All those applications require an advanced CMOS technology in particular down-scaled nodes. CMOS with scaled gate length down to 26 nm already results in a cut-off frequency increase beyond 450 GHz, reduced flicker noise and increased drive current. Further scaling down to 5 nm was reported by TSMC, enabling a 15% speed improvement with 30% power consumption reduction compared to 7 nm nodes. Such downscaled devices to minimize the impact of parasitic capacitances and resistances require optimized architectures (FinFET, nanosheet FET, forksheet FET, complementary FET). An optimized 5 nm CMOS device architecture was reported in. Downscaling results in higher parasitic capacitances and higher series resistances, setting a limitation for analog high-frequency applications, where f_T and f_max matter. For deeply scaled CMOS devices, maintaining high f_T or transconductance over the gate capacitance (g_m/C_g) is difficult due to g_m limitations and simultaneous C_g increase with gate node decrease. Another drawback of downscaled CMOS is an increase of gate resistance, R_g, implying RF noise degradation. Scaled CMOS technology exploits low-voltage supply and features a high level of parasitics. Circuits such as ADC will benefit from analog design downscaling, while mm-Wave front-end modules suffer from the low power levels that CMOS can deliver. An increasing demand of higher-speed computing and lower power consumption will continue the further development of CMOS technology. Optimized for high-frequency performance, FinFETs with a 22 nm technology node with f_t/f_max of 280/460 GHz were used to fabricate a 60–90 GHz LNA with a gain of 20 dB and noise figure NF = 3.7dB and a power amplifier (PA) with 17dB of power gain G_P at 75 GHz.

We call for papers covering CMOS technology development, as well as circuit design solutions (analog/digital) using advanced CMOS technology.

Dr. Paulius Sakalas
Guest Editor

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• CMOS
• FinFET
• complementary FET
• nanosheet FET
• forksheet FET downscaling
• millimeter-wave circuits
• optical communication
• automotive radar
• ADC