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Novel Materials and Processes for Electronic Packaging

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A special issue of Materials (ISSN 1996-1944). This special issue belongs to the section "Electronic Materials".

Deadline for manuscript submissions: closed (10 December 2022) | Viewed by 7552

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Special Issue Editor

Prof. Dr. Shih-Kang Lin

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Guest Editor

Department of Materials Science and Engineering, National Cheng Kung University, Tainan 70101, Taiwan
Interests: electronic interconnection technologies; Li ion batteries; alloy design; ironmaking and steelmaking; computational materials thermodynamics

Special Issue Information

Dear Colleagues,

Driven by new applications ranging from super-computing and fifth/sixth-generation (5G/6G) communications to electric vehicles (EVs) and green energy, advanced high-density electronic packaging technologies, as well as high-power electronic interconnection are in great demand in the electronic industry. Meanwhile, sustainable materials and manufacturing technologies are also needed to meet the low-emission requirements for carbon neutrality. To achieve high-density and high-reliable electronic devices with low energy consumption, innovative materials and processes for electronic packaging play key roles. For high-density packaging, three-dimensional (3D) integration is an emerging technology, while for sustainable processes, low-temperature processes are desired. The 3D structures involve through-silicon-via (TSV), advanced ceramic substrates, and metal-to-metal or metal-to-ceramics bonding, which require various kinds of electronic interconnection technologies, e.g., solder bumping, transient-liquid-phase (TLP) bonding, thermal compression bonding, adhesive bonding, and active metal brazing (ABM). The reliability of heterogeneous interfaces such as warpage and the formation of brittle intermetallic compounds (IMCs) is the major concern for evaluating the materials and processes.

This Special Issue will cover current challenges, progresses, and outlooks of novel materials and processes for electronic packaging based on advanced simulation and characterizations. Research papers and critical reviews on these fields are both highly welcome.

Prof. Dr. Shih-Kang Lin
Guest Editor

Manuscript Submission Information

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Keywords

3D integration
heterogeneous integration
Cu-to-Cu bonding
through-silicon-via (TSV)
low-temperature Pb-fee solders
transient liquid phase (TLP) bonding
thermal compression bonding
adhesive bonding
active metal brazing
metal-ceramics bonding
metallic pastes
powder sintering
warpage
electronic packaging and reliability
computer simulation for electronic packaging
advanced characterizations for electronic packing

Published Papers (3 papers)

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Research

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20 pages, 1967 KiB

Open AccessArticle

Laser-Assisted Micro-Solder Bumping for Copper and Nickel–Gold Pad Finish

by Sumera Kousar, Karsten Hansen and Thomas Florian Keller

Materials 2022, 15(20), 7349; https://doi.org/10.3390/ma15207349 - 20 Oct 2022

Cited by 2 | Viewed by 2883

Abstract

Flip-chip bonding is a key packaging technology to achieve the smallest form factor possible. Using copper as a direct under-bump metal and performing bonding under little force and at a low temperature eliminates the processing step for the deposition of a suitable wetting metal and offers an economical solution for electronic chip packaging. In this paper, various samples with copper and nickel–gold surface finishes are used to apply an in-house solder bumping, flip-chip bonding and reflow process to exhibit the bump-bond feasibility. Native oxides are reduced using process gases, and copper surface protection and solder wetting are achieved using copper formate. Lead-free 40 µm solder balls were bumped on 80 µm copper pads and 120 µm copper pillars to demonstrate a full intermetallic Cu–Cu bond as a base study for stacking applications. Using a low-force bonding technique, various chips with different dimensions were bonded at 0.5–16 MPa, followed by a reflow step at a maximum temperature of 270 °C. Then, 30 µm solder balls are utilized to bump the samples with NiAu and Cu bond pads at 50 µm pitch. A mean shear strength of 44 MPa was obtained for the 30 µm Cu samples. To the best of our knowledge, 30 µm solder bumping directly on the copper pads by producing copper formate is a novel research contribution. Full article

(This article belongs to the Special Issue Novel Materials and Processes for Electronic Packaging)

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11 pages, 5856 KiB

Open AccessArticle

Effects of Initial Morphology on Growth Kinetics of Cu₆Sn₅ at SAC305/Cu Interface during Isothermal Aging

by Jia-Yi Lee and Chih-Ming Chen

Materials 2022, 15(14), 4751; https://doi.org/10.3390/ma15144751 - 7 Jul 2022

Cited by 3 | Viewed by 1618

Abstract

Solder/Cu joints are important components responsible for interconnection in microelectronics. Construction of the solder/Cu joints through liquid/solid (L/S) reactions accompanies the formation of the Cu–Sn intermetallic compounds (IMCs) at the joint interface. The Cu₆Sn₅ IMC exhibits remarkable distinctions in thickness and morphology upon increasing the L/S reaction time. Effects of the initial characteristics of thickness and morphology on the growth kinetics of Cu₆Sn₅ during subsequent isothermal aging were investigated. SAC305 solder was reflowed on a Cu electroplated layer at 265 °C for 1 to 60 min to produce the Cu₆Sn₅ IMC with different thickness and morphology at the SAC305/Cu interface. The as-fabricated SAC305/Cu joint samples were aged at 200 °C for 72 to 360 h to investigate the growth kinetics of Cu₆Sn₅. The results show that the initial characteristics of thickness and morphology significantly influenced the growth kinetics of Cu₆Sn₅ during the subsequent solid/solid (S/S) reaction. A prolonged L/S reaction time of 60 min (L/S-60) produced a scallop-type Cu₆Sn₅ IMC with a larger grain size and a thicker thickness, which reduced the quantity of fast diffusion path (grain boundary) and the magnitude of concentration gradient, thus slowing down the growth rate of Cu₆Sn₅. According to the growth kinetics analysis, the growth rate constant of Cu₆Sn₅ could be remarkably reduced to 0.151 µm/h^0.5 for the L/S-60 sample, representing a significant reduction of 70 % compared to that of the L/S-1 sample (0.508 µm/h^0.5 for L/S reaction time of 1 min). Full article

(This article belongs to the Special Issue Novel Materials and Processes for Electronic Packaging)

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Review

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20 pages, 9407 KiB

Open AccessReview

Effect of Sn Grain Orientation on Reliability Issues of Sn-Rich Solder Joints

by Yu-An Shen and John A. Wu

Materials 2022, 15(14), 5086; https://doi.org/10.3390/ma15145086 - 21 Jul 2022

Cited by 10 | Viewed by 2472

Abstract

Sn-rich solder joints in three-dimensional integrated circuits and their reliability issues, such as the electromigration (EM), thermomigration (TM), and thermomechanical fatigue (TMF), have drawn attention related to their use in electronic packaging. The Sn grain orientation is recognized as playing an important role in reliability issues due to its anisotropic diffusivity, mechanical properties, and coefficient of thermal expansion. This study reviews the effects of the Sn grain orientation on the EM, TM, and TMF in Sn-rich solder joints. The findings indicate that in spite of the failure modes dominated by the Sn grain orientation, the size and shape of the solder joint, as well as the Sn microstructures, such as the cycling twining boundary (CTB), single crystals, and misorientations of the Sn grain boundary, should be considered in more detail. In addition, we show that two methods, involving a strong magnetic field and seed crystal layers, can control the Sn grain orientations during the solidification of Sn-rich solder joints. Full article

(This article belongs to the Special Issue Novel Materials and Processes for Electronic Packaging)

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