Low-Power Energy-Efficient Hetero-Dielectric Gate-All-Around MOSFETs: Enablers for Sustainable Smart City Technology

Abstract

In the context of increasing digitalization and the emergence of applications such as smart cities, embedded devices are becoming ever more pervasive, mobile, and ubiquitous. Due to increasing concerns around energy efficiency, gate density, and scalability in the semiconductor industry, there has been much interest recently in the fabrication of viable low-power energy-efficient devices. The Hetero-Dielectric Gate-All-Around (HD-GAA) MOSFET represents a cutting-edge transistor architecture designed for superior sustainability and energy efficiency, improving the overall efficiency of the system by reducing leakage and enhancing gate control; therefore, as part of the transition to a sustainable future, several semiconductor industries, including Intel, Samsung, Texas Instruments, and IBM, are using this technology. In this study, Hetero-Dielectric Single-Metal Gate-All-Around MOSFET (HD-SM-GAA MOSFET) devices and circuits were designed using Schottky source/drain contacts and tunable high-k dielectric Hf_xTi_1−xO₂ in the TCAD simulator using the following specifications: N-Channel HD-SM-GAA MOSFET (‘Device-I’) with a 5 nm radius and a 21 nm channel length alongside two P-Channel HD-SM-GAA MOSFETs (‘Device-II’ and ‘Device-III’) with radii of 5 nm and 8 nm, respectively, maintaining the same channel length. Thereafter, the inverters were implemented using these devices in the COGENDA TCAD simulator. The results demonstrated significant reductions in short-channel effects: subthreshold swing (SS) (‘Device-I’ = 61.5 mV/dec, ‘Device-II’ = 61.8 mV/dec) and drain-induced barrier lowering (DIBL) (‘Device-I’ = 8.2 mV/V, ‘Device-II’ = 8.0 mV/V) in comparison to the existing literature. Furthermore, the optimized inverters demonstrated significant improvements in noise margin values such as Noise Margin High (NM_H) and Noise Margin Low (NM_L), with Inverter-1 showing 38% and 44% enhancements and Inverter-2 showing 40% and 37% enhancements, respectively, compared to the existing literature. The results achieved illustrate the potential of using this technology (e.g., for power inverters) in embedded power control applications where energy efficiency and scalability are important, such as sustainable smart cities.

1. Introduction

The increasing digitalization and penetration of intelligent embedded power control devices in applications such as smart grids and smart cities drive a growing need for sustainable, energy-efficient, and reliable electronics. This, in turn, has fueled research and transistor technology development. Transistors, the foundation of contemporary electronics, must provide exceptional switching performance coupled with low-parasitic power or signal losses, ideally with a size/density and manufacturing footprint that is favorable in terms of economic costs and harm to the environment [1,2,3]. The energy efficiency, scalability, and leakage control of conventional planar and Fin Field-Effect Transistor (FinFET) designs are constrained, especially in advanced technological nodes (sub-5 nm). Many innovative technologies have been invented and created over the past decades to enhance the functionality of devices and alleviate short-channel effects (SCEs), including strained silicon, high-metal gates, and three-dimensional (3D) device architectures [4,5,6,7]. The advancement of 3D designs and multiple gate field-effect transistors, such as multifaceted gate, Omega, Fin, and GAA FETs, demonstrates their supremacy beyond planner devices with aggressive complementary metal-oxide semiconductor (CMOS) scaling. Despite the higher process complexity and cost, GAA FETs offer better performance, lower leakage, and improved scalability, making them a necessary evolution beyond FinFETs. Over time, as fabrication techniques mature, costs may reduce, making GAAFETs more economically viable for large-scale production. Although more complex and costly at this stage compared to conventional FETs, cost and complexity are expected to reduce considerably due to miniaturization. Since FinFETs provide better electrostatic control of the channel than planar MOSFETs, they are the favored device design for the mass manufacturing of electronic components beyond the 32 nm technology node [8].

However, the performance, layout, and cost of FinFETs are now quite problematic, making future scaling of the transistors a tedious operation necessitating unique architectural designs. This is a barrier to their application in smart cities, where size/density, energy footprint, and development times and costs are critical. Without a doubt, among the many device structures employed, the ultimate scaled transistor structure GAA has shown promise for designing nano-scale devices because it provides electrostatic controllability by completely controlling the channel’s carriers via the gate with immunity to short channel effects and high current drivability, providing higher chip-packing density because of the perfectly circular configuration, negligible corner effects, huge transconductance, and a desirable sub-threshold slope [9,10,11]. Shorter channel lengths produce faster operating speeds and more components per chip [12]. A noteworthy property of GAA transistors is that their speed improves, and their cost drops as their size shrinks, driving the rapid expansion of the electronic technology sector [13]. According to IBM, a 150 mm² device with a compact architecture employing GAAFET 2 nm technology may fit 50 billion transistors [14]. Due to the improved channel transport control provided entirely by the surrounding gates in GAAFETs, FinFETs are likely to be phased out in future technological nodes. In order to continue logical growth beyond the 5 nm technology node and beyond FinFETs, the industry has widely embraced GAAFETs, a novel next-generation transistor device [15]. The exceptional gate control and decrease in SCEs have also greatly improved the performance of analog and radio frequency (RF) devices [16]. However, the main disadvantage of these massively scaled devices is elevated series resistance as a result of the origination of unanticipated source/drain intersections. These shortcomings have led to the replacement of doped source/drain regions with novel approaches like the Schottky barrier/contact source and drain, enabling a greater ON-current and enhanced transconductance. Moreover, not only do Schottky barrier metal-oxide semiconductors have drain and source divisions made of aluminum that are likely to find numerous applications in deep micron-sized devices, but they also offer advantages in terms of cultivation [11]. To enhance these devices’ capabilities, many engineering approaches, such as bandgap engineering with hetero-junction devices and gate and work function engineering, have been investigated in the literature work [17]. High-k gate dielectric material such as Hf_xTi_1−xO₂ with a permittivity value above 40 has been preferred for sub-22 nm multi-gate FinFET devices. It allows the controllability of electrostatics and creates an effective link between the gate and the channel, which helps to reduce leakage current and other problems like SCEs [9]. Major semiconductor companies, including Intel, IBM, Samsung, and TSMC, have started employing high-k gate oxide and metallic gate materials in the manufacture of transistors for scaled devices [18,19,20,21]. The key characteristics of high-k gate dielectric include a high-energy bandgap and thermal and chemical stability with silicon and high crystallization temperatures [22].

To extend previous work and explore further developments in this area, in this article, we consider both N-Channel and P-Channel Hetero-Dielectric Single-Metal Gate-All-Around MOSFETs with Schottky source/drain contact, which were created in combination with device specifications such a tunable high-k dielectric (k) of Hf_xTi_1−xO₂, a 5 nm radius, and a 21 nm channel length. The same structures were used to construct the CMOS inverter. The remainder of this article has been organized as follows: In Section 2, the device design structures and simulation methodology of N-Channel and P-Channel HD-SM-GAA MOSFETs with Schottky source/drain contact are discussed. The design and structural arrangement of an inverter utilizing an HD-SM-GAA MOSFET with a Schottky source/drain contact is described in Section 3. The performance analysis and comparison of proposed devices and circuits are given in Section 4. Following that, the conclusion and future scope are explained and exposited in Section 5.

2. Device Structure and Simulation Methodology

Using the COGENDA TCAD simulator, the following devices with a channel length of 21 nm were created: (1) ‘Device-I’, i.e., an N-Channel HD-SM-GAA MOSFET (radius 5 nm); (2) ‘Device-II’, i.e., a P-Channel HD-SM-GAA MOSFET of 5 nm radius; and (3) ‘Device-III’, i.e., a P-Channel HD-SM-GAA MOSFET of 8 nm radius. The design specifications used for the proposed structures are shown in

Table 1. Design description of proposed structures (‘Device-I’, ‘Device-II’ and ‘Device-III’).

Parameters	Device-I	Device-II and Device-III
Silicon-Body Radius (nm)	5	5, 8
Oxide Thickness (nm)	2	2
Length of Source/Drain (nm)	10	10
Si Channel Length (nm)	21	21
Doping Concentration of Channel (cm−3)	1 × 1016	1 × 1016
Gate Work Function (eV)	4.8	4.67
Work Function of Source/Drain (eV)	4.2	5.3
Dielectric Constant of Gate Oxide (k)	HfxTi1−xO2 (k1 = 50, k2 = 80, k3 = 50)	HfxTi1−xO2 (k1 = 50, k2 = 80, k3 = 50)

. The design parameters of GAA transistors were selected according to Intel dimensions [23]. Figure 1 shows the 2D structures of the proposed devices (a) ‘Device-I’ and (b) ‘Device-II’ of 5 nm radius, 21 nm channel length (L1 = 7 nm + L2 = 7 nm + L3 = 7 nm), and tunable compound (high-k) gate dielectric Hf_xTi_1−xO₂ material (k1 = 50, k2 = 80, and k3 = 50). The amalgamation of two oxide materials (HfO₂ and TiO₂) was chosen to increase the permittivity value to greater than 50. The potential of an insulator is increased by a greater dielectric constant value. Chemical vapor deposition (CVD) is often used to deposit the chosen compound dielectric material, such as Hf_xTi_1−xO₂ film, on silicon at temperatures as high as 1000 °C. Unwavering coverage over intricate layouts and fast, flexible growth rates are two benefits of the CVD process [24]. Leakage current and static power consumption are greatly reduced using the high-k gate dielectric because it increases gate capacitance in the structure [22]. Schottky source/drain regions made with aluminum metal and spacer regions and developed with silicon dioxide (SiO₂) provide low parasitic effects in proposed devices [25,26].

The structural description of ‘Device-III’ with a channel length of 21 nm, variable high-k gate dielectric values, and an 8 nm radius is presented in Figure 2. Figure 3a,b show the 3D cubic depiction of ‘Device-I’ and ‘Device-II’. The 3D cubic depiction of ‘Device-III’ is displayed in Figure 4. For the proposed devices (‘Device-I’, ‘Device-II’, and ‘Device-III’), the metal work function of the gate was maintained at 4.8 eV and 4.67 eV, respectively. Due to the employment of Schottky metal contacts with permissible work functions, such as 4.2 eV for ‘Device-I’ and 5.3 eV for ‘Device-II’ and ‘Device-III’, the proposed device became a single mask device, eliminating the need for a mask in the source/drain area [22]. The simulation parameters of the proposed ‘Device-I’ were calibrated at room temperature (300 K). Figure 5 outlines the comparison of the simulated work with the existing work to inspect the validity of the TCAD simulator [27]. Figure 6a displays the transfer characteristics of ‘Device-I’ and ‘Device-II’ at different V_d voltages as the gate voltage (V_g) varied from −1.0 V to 1.0 V. Figure 6b outlines the transfer characteristics of ‘Device-I’ and ‘Device-III’ at V_d = 0.1 V, 0.5 V, 0.8 V, and 1.0 V as the gate voltage (V_g) varied from −1.0 V to 1.0 V. It has been noted that ‘Device-I’ has a larger drain current compared to ‘Device-II’ because holes have lower mobility compared to electrons [28]. It can be observed in Figure 6b that ‘Device-III’ produces the same drain current as ‘Device-I’ because of the larger area of ‘Device-III’ compared to ‘Device-I’. The output curves for ‘Device-I’, ‘Device-II’, and ‘Device-III’ are displayed in Figure 7.

Device Physics

The following approved models were used to create the proposed structures:

• The Drift-Diffusion Model (DDML) is used to create a sequence of Poisson equations. It is strong and works instantly for the created structures.

  $$\nabla .\epsilon \mathsf{\nabla }\phi =\mathrm{q}(\mathrm{p}-\mathrm{n}+N_D^{+}-N_A^{-})$$

  (1)
• The ‘φ’ symbol represents the electron charge, the ‘q’ symbol indicates the electrostatic charge of the vacuum level and ${\mathrm{N}}_{\mathrm{A}}^{-}$ and ${\mathrm{N}}_{\mathrm{D}}^{+}$ represent the doping ionized proportion. The number of holes is denoted by ‘p’ and the number of electrons is indicated by ‘n’.
• Monitoring the carrier’s motion in the device’s inverted layer serves as a role model for Lombardi’s mobility. The combined mobility of doped carriers is outlined below:

  $${\mu }_S^{-1}={\mu }_B^{-1}{+\mu }_{AC}^{-1}+{\mu }_{SR}^{-1}$$

  (2)

The phrase ‘µ_B’ represents “bulk mobility”, ‘µ_AC’ indicates “degradation/scattering mobility” and “Surface roughness” is represented by the symbol ‘µ_SR’.

• Kane’s model for band-to-band tunneling-based carrier generation is represented in Equation (3).

  $$G^{BB}=A.BBT.{\displaystyle \frac{E^2}{\sqrt{E_G}}}exp(-B.BBT{\displaystyle \frac{E_G^{\frac{3}{2}}}{E}})$$

  (3)

The factors ‘A.BBT’ and ‘B.BBT’ represent experimentally measured fitting elements, and the ‘E_G’ parameter represents a bandgap energy that follows an electric field (‘E’).

• The aforementioned process for the Shockley Read Hall (SRH) recombination with carriers examines the mutation rate and is shown below:

  $$U_{SRH}={\displaystyle \frac{pn-n_{ie}^2}{{\tau }_p[n+n_i{e}^{\frac{E_T}{K{T}_L}}]+{\tau }_n[p+n_i{e}^{\frac{-E_T}{K{T}_L}}]}}$$

  (4)

Here, ‘$n_i$’ represents the intrinsic density of the carriers; ‘E_T’ represents the captured energy level and the carrier longevity, and the lattice thermal is indicated by ‘${\tau }_n$’, and ‘T_L’ respectively [17,22].

3. Inverters Design Structure and Simulation

Table 2. Specifications of proposed inverters.

Parameters	Inverter-1	Inverter-2
Device Radius (nm)	5 (Device-I), 5 (Device-II)	5 (Device-I), 8 (Device-III)
Oxide Thickness (nm)	2	2
Length of Source/Drain (nm)	10	10
Si Channel Length (nm)	21	21
Work Function of Gate (eV)	4.8 (Device-I), 4.67 (Device-II)	4.8 (Device-I), 4.67 (Device-III)
Work Function of Source/Drain (eV)	4.2 (Device-I), 5.3 (Device-II)	4.2 (Device-I), 5.3 (Device-III)
Length of Spacer (nm)	10	13
High-k Value (k)	k1 = 50, k2 = 80, k3 = 50	k1 = 50, k2 = 80, k3 = 50

displays the design parameters used for the proposed inverters. The two CMOS inverters, i.e., Inverter-1 and Inverter-2, were created using proposed devices such as ‘Device-I’, ‘Device-II’, and ‘Device-III’.

Inverter-1 was designed using devices ‘Device-I’ and ‘Device-II’. The selected tunable high-k oxide (Hf_xTi_1−xO₂) values for different regions of the channel are as follows, i.e., ‘k1’ = 50 for the ‘L1’ channel length, ‘k2’ = 80 for the ‘L2’ channel length, and ‘k3’ = 50 for the ‘L3’ channel length. Similarly, Inverter-2 was designed using ‘Device-I’ and ‘Device-III’ by choosing different values of tunable (Hf_xTi_1−xO₂) high-k oxide materials for different regions of the channel, i.e., ‘k1’ = 50 for the ‘L1’ channel length, ‘k2’ = 80 for the ‘L2’ channel length, and ‘k3’ = 50 for the ‘L3’ channel length. The 2D configurations of Inverter-1 and Inverter-2 are displayed in Figure 8 and Figure 9, respectively.

Aluminum metal was used for the construction of the source/drain terminals of the proposed devices (‘Device-I’, ‘Device-II’, and ‘Device-III’). Hf_xTi_1−xO₂ oxide was utilized as a gate dielectric, while SiO₂ oxide was used as a spacer. An intrinsic silicon channel was formed between the source/drain terminals for the design of devices such as ‘Device-I’, ‘Device-II’, and ‘Device-III’. The gate material used to cover the high-k gate oxides was ‘Npoly silicon’ for ‘Device-I’ and ‘Ppoly silicon’ for ‘Device-II’ and ‘Device-III’. The optimized 3D structures of Inverter-1 and Inverter-2 are displayed in Figure 10 and Figure 11, respectively.

4. Results and Discussion

The COGENDA TCAD 3D Device Simulator is utilized for designing devices such as ‘Device-I’, ‘Device-II’, and ‘Device-III’ and their inverters (Inverter-1 and Inverter-2). The following models of the ‘Drift-Diffusion model’, the ‘Lombardi mobility model’, the ‘SRH carrier recombination mechanism’, and ‘Kane’s model’ were utilized to create and simulate the proposed devices and circuits [22].

Digital parameters like ‘ON-current’ (I_ON), ‘OFF-current’ (I_OFF), ‘Current Ratio’ (I_ON/I_OFF), and SCEs such as ‘Sub-Threshold Swing’ (SS) and ‘drain-induced barrier lowering’ (DIBL) were evaluated for the proposed devices. Performance analog parameters such as ‘Transconductance’ (g_m), ‘Transconductance Generation Factor’ (TGF = g_m/I_d), ‘Output Conductance’ (g_d), and ‘Early Voltage’ (I_d/g_d) were calculated for the designed structure. The DC and the transient analysis of optimized inverters designed with the proposed devices (‘Device-I’, ‘Device-II’, and ‘Device-III’) were also measured in the TCAD environment.

4.1. Device: Analysis of Electrical Characteristics and SCEs

The ON-current (I_ON) of the proposed devices was calculated at V_d = 0.1 V, V_g = 1.0, V, and the OFF-current (I_OFF) was measured at V_d = 0.1 V, V_g = 0 V. It has been observed in

Table 3. Comparative analysis of ‘Device-I’, ‘Device-II’, and ‘Device-III’ for k1 = 50, k2 = 80, k3 = 50 at V_d = 0.1 V, and V_g = 1.0 V at 21 nm channel length.

Parameters	Device-I (Radius—5 nm)	Device-II (Radius—5 nm)	Device-III (Radius—8 nm)
ION (A)	1.54 × 10−5	9.07 × 10−6	1.58 × 10−5
IOFF (A)	0.94 × 10−15	1.26 × 10−15	3.27 × 10−14
ION/IOFF	1.63 × 1010	7.20 × 109	4.82 × 108
SS (mV/dec)	61.8	61.4	68.2
DIBL (mV/V)	8.2	8	39

that the ‘Device-I’ has more I_ON and less I_OFF compared to ‘Device-II’ and ‘Device-III’.

‘Device-I’ had a 55.8% greater I_ON/I_OFF ratio compared to ‘Device-II’. ‘Device-III’ had 66.1% more I_OFF compared to ‘Device-I’ and, thus, had a reduced I_ON/I_OFF ratio by 33 times. The switching performance of devices was evaluated using SS. The SS depicts how the drain current behaves in the sub-threshold zone. It is calculated by dividing the decade change in the drain current by the change in the gate voltage, as mentioned in Equation (5). The measurement unit of SS is mV/dec.

$$SS=\partial log{\left[{\displaystyle \frac{\partial \left({\log }_{10}{I}_d\right)}{V_g}}\right]}^{-1}$$

(5)

The optimal value of SS at 300 K is 60 mV/dec. The extracted values for both ‘Device-I’ and ‘Device-II’ were obtained near the ideal value, as mentioned in Table 3. When the potential barrier drops and the drain voltage increases, this phenomenon is referred to as DIBL. Reduced DIBL, i.e., 8.2 mV/V, 8 mV/V, and 39 mV/V, was calculated for ‘Device-I’, ‘Device-II’, and ‘Device-III’, respectively, compared to ideal DIBL (100 mV/V). As the gate dielectric high-k value increases, the gate capacitance also increases, which results in a reduction in SS and DIBL [29,30,31,32,33,34,35,36]. Therefore, such devices are suitable for implementing digital VLSI circuits.

4.2. Device: Analysis of Analog Parameters

The analog parameter transconductance (g_m) measures the device’s voltage conversion capability into current. The mathematical formula for calculating the g_m is expressed in Equation (6).

$$g_m={\displaystyle \frac{\partial I_d}{\partial v_g}}$$

(6)

Table 4. Comparative evaluation of analog performance of ‘Device-I’, ‘Device-II’, and ‘Device-III’.

Parameters	Device-I	Device-II	Device-III
gm (S)	7.03 × 10−5	3.32 × 10−5	5.55 × 10−5
gd (S)	1.77 × 10−14	2.13 × 10−14	8.15 × 10−12
Ve (V)	3.342331	3.71027	0.64657
TGF (V−1)	10	10	10

shows the largest g_m (7.03 × 10⁻⁵ S) for ‘Device-I’ compared to ‘Device-II’ and ‘Device-III’. A smaller bandgap and better control over the channel through the gate terminal are indicated by a higher value of g_m. Figure 12a presents the fluctuation in g_m with respect to gate voltage (V_g) at various drain voltages (V_d), i.e., 0.1 V to 1.0 V [26]. The formula g_m/I_d was utilized to obtain the transconductance Generation Factor (TGF), which is another Figure of Merit that shows how efficiently a device converts current into transconductance. Figure 12b shows the variation in TGF with respect to V_g for V_d = 0.1 V and 1.0 V. It can be observed from Figure 12b that the same value of TGF, i.e., 10 V⁻¹ was extracted for ‘Device-I’, ‘Device-II’ and ‘Device-III’. The output conductance (g_d) was determined by dividing the change in drain current and the change in drain voltage, as expressed in Equation (7).

$$g_d={\displaystyle \frac{\partial I_d}{\partial V_d}}$$

(7)

The lowest value of g_d is 1.77 × 10⁻¹⁴ S, which was measured for ‘Device-I’, as shown in Table 4. The smaller value of g_d improves the analog performance parameters, such as the early voltage (V_e) and intrinsic gain (A) of devices. Figure 13a outlines the variation in g_d with respect to V_d for V_g = 0.1 V.

4.3. Comparative Analysis of Proposed Devices with the Existing Literature

Table 5. Comparative analysis of optimized proposed devices with a channel length of 21 nm compared to existing devices with a channel length of 20 nm.

Devices	Device Dimensions	Proposed Devices (k1 = 50, k2 = 80, k3 = 50) HD-SM-GAA MOSFET	Existing Literature (k = 50) (Kaur et al., 2019) HD-SM-SB-GAA NWFET [24]	% Age Improvement
Device-I	SS (mV/dec)	61.8	63.88	3.25%
	DIBL (mV/V)	8.2	21.28	61.46%
	ION/IOFF	1.63 × 1010	7.10 × 109	2.29 times
Device-II	SS (mV/dec)	61.4	64.06	4.15%
	DIBL (mV/V)	8	25.72	68.89%
	ION/IOFF	7.20 × 109	2.8 × 109	2.57 times

indicates the contrast between the optimized proposed devices of channel length 21 nm with an existing device of channel length 20 nm. It is noted that ‘Device-I’ exhibited a 3.25% improvement in SS, a 61.46% decrement in DIBL, and a 2.29 times enhancement in I_ON/I_OFF compared to the device designed by Kaur et al., 2019. For ‘Device-II’, the performance parameter I_ON/I_OFF increased by 2.57 times compared to the P-Channel device created by the author in [24]. The switching parameters SS and DIBL of ‘Device-II’ were reduced by 4.15% and 68.89%, respectively, compared to the work performed by Kaur et al., 2019 [24]. It has been demonstrated that the designed devices have enhanced parameters and, thus, may be utilized to build low-power circuits [24].

Table 6. Comparative analysis of designed devices with the existing device of channel length 17 nm.

Devices	Device Dimensions	Proposed Devices HD-SM-GAA MOSFET Radius = 5 nm (Diameter = 10 nm), Vd = 0.1 V, Gate dielectric, HfxTi1−xO2 (k1 = 50, k2 = 80, k3 = 50) of 21 nm Channel Length	Existing Literature Diameter 11 nm, Vd = 0.8 V (Nayak et al., 2014), Gate Dielectric, k = 3.9 (SiO2) of 17 nm Channel Length [37]	% Age Improvement
Device-I	SS (mV/dec)	61.8	67.5	8.44%
	DIBL (mV/V)	8.2	50	83.60%
	ION/IOFF	1.63 × 1010	8.25 × 106	1.97 × 103 times
	gm(µS)	70.3	52.9	32.89%
Device-II	SS (mV/dec)	61.4	73	15.89%
	DIBL (mV/V)	8	66	87.87%
	ION/IOFF	7.20 × 109	8.57 × 106	0.84 × 103 times
	gm (µS)	33.2	63.07	47.36%

demonstrates the performance analysis of proposed devices of 21 nm channel length with the device designed by Nayak et al., 2014. It is clear for ‘Device-I’ that the SS and DIBL parameters decreased by 8.44% and 83.60%, respectively, compared to the existing literature [37]. The DIBL showed a higher percentage decline compared to the work performed by Nayak et al., 2014, because of the use of compound gate dielectric material in the proposed devices. The I_ON/I_OFF rose by a magnitude of 10³, and g_m increased by 32. 89% compared to the existing work [37].

Similarly, ‘Device-II’ exhibited a progressive improvement in the performance metrics when compared with the reference work [37]. In Table 6, it is observed that the proposed ‘Device-II’ shows an enhancement in I_ON/I_OFF by 1000 times, and g_m is increased by 47.36% compared to the device created by Nayak et al. in 2014. The other performance parameters, like SS and DIBL, also decreased by 15.89% and 87.87%, respectively, compared to the existing device of channel length 17 nm [37].

4.4. Optimized Inverters

It is clear from Table 4, Table 5 and Table 6 that the proposed devices, i.e., ‘Device-I’, ‘Device-II’, and ‘Device-III’, are suitable for implementing Inverter-1 and Inverter-2. Inverter-1 was built with ‘Device-I’ and ‘Device-II’ in the TCAD environment. Similarly, Inverter-2 was created with a combination of ‘Device-I’ and ‘Device-III’. The performance analysis of optimized inverters was performed by calculating the noise margin and transient analysis.

Transient Analysis and Noise Margin of Inverters

• Transient Analysis: It examines the behavior of circuits when they switch from one steady state to another state [28]. Figure 14 demonstrates the transient analysis of Inverter-1 at a supply voltage (V_DD) of 1.0 V.
• Noise Margin: The noise margin determines the noise immunity of circuits, and this is indicated by NM [29]. The circuit with a higher value of NM shows high noise sensitivity. The expression for calculating NM for low signals (NM_L) and for high signals (NM_H) is expressed as follows:

NM_L = V_IL − V_OL

(8)

NM_H = V_OH − V_IH

(9)

The lowest output value at logic level 0 is represented by V_OL, and the highest output voltage at logic level 1 is represented by V_OH [38]. Logic value 0 designates the lowest input voltage (V_IL), while logic value 1 designates the highest input voltage (V_IH). Figure 15 demonstrates the butterfly curve of Inverter-1 and Inverter-2 at supply voltage levels of 0.5 V and 1.0 V. The calculated noise margin values, i.e., NM_H = 482 mV and NM_L = 461.2 mV of Inverter-1, are demonstrated in Figure 15a. Figure 15b displays the NM values for Inverter-2. The lowest output value at logic level 0 is represented by V_OL, and the highest output voltage at logic level 1 is represented by V_OH [38]. Logic value 0 designates the lowest input voltage (V_IL), while logic value 1 designates the highest input voltage (V_IH). Figure 15 demonstrates the butterfly curve of Inverter-1 and Inverter-2 at supply voltage levels of 0.5 V and 1.0 V. The calculated noise margin values, i.e., NM_H = 482 mV and NM_L = 461.2 mV of Inverter-1, are demonstrated in Figure 15a. Figure 15b displays the NM values for Inverter-2. Inverter-2 has a 1.78% higher NM_H compared to the NM_H of Inverter-1 at 1.0 V, and a similar scenario was observed at 0.5 V, i.e., Inverter-2 had 11.85% more NM_H compared to Inverter-1. Inverter-1 presents a larger value of NM_L at both voltages compared to Inverter-2, as shown in Figure 15. The butterfly curves and calculated NM values for the variable voltage V_DD from 0.2 V to 1.0 V of the proposed inverters are displayed in Figure 16 and Figure 17, respectively. It has been analyzed in both inverters that a higher supply voltage results in a higher NM.

4.5. Comparison of Designed Optimized Inverters with Previous Work

Table 7. Comparative analysis of proposed inverters to existing work.

Present Work	Parameters NMH and NML (mV) at VDD = 1.0 V	Existing Work (Nayak et al., 2014), Diameter = 11 nm, Channel Length = 17 nm, Vd = 1 V, Gate Dielectric, k = 3.9 (SiO2) NMH = 350 mV, NML = 320 mV % Age Improvement [37]
Inverter-1 (Device-I and Device-II)	NMH = 482 mV	38% (Increased)
	NML = 461.2 mV	44% (Improved)
Inverter-2 (Device-I and Device-III)	NMH = 490.6 mV	40% (Enhanced)
	NML = 437.1 mV	37% (Increased)

expresses a 38% NM_H improvement and 44% NM_L enhancement in Inverter-1 compared to the inverter designed by Nayak et al., 2014. Similarly, Inverter-2 presents a 40% and 37% greater value of NM_H and NM_L, respectively, in comparison to the existing literature [37,38]. In the present work, the optimized devices used for implementing inverters were made with tunable Hf_xTi_1−xO₂ high-k gate dielectric materials. This improved the electrical and analog parameters and also reduced the SCEs, like the minimized values of SS and DIBL. Thus, it produced better functionality and greater noise immunity in the proposed inverters. Therefore, the proposed inverters are suitable for low-power applications.

5. Conclusions

Motivated by the need for further investigations into high-performance, energy-efficient semiconductor designs for emerging applications such as smart grids and smart cities, in this article, a potential design for a next-generation transistor called the Hetero-Dielectric Gate-All-Around (HD-GAA) MOSFET was created and investigated.

Specifically, the (HD-GAA) MOSFET is designed to be a next-generation transistor architecture candidate for sustainability, high-performance-embedded computing, and power control applications. Leveraging advanced materials like tunable high-k dielectrics (Hf_xTi_1−xO₂) and innovative GAA topologies, it has been shown in the studies presented herein that the proposed devices deliver enhanced performance, reduced power consumption, and scalability for modern applications in the semiconductor industry. Although further investigations are warranted, this article presents positive, supportive evidence of their suitability for deployment in the context of sustainable smart cities and smart grid applications.

Three devices (Device-I, Device-II, and Device-III) were designed in the COGENDA Visual TCAD environment, and their performance characteristics (I_ON, I_OFF, I_ON/I_OFF, SS, DIBL, g_m, g_d, and V_e) were evaluated. Device-I reduced SS and DIBL by 3.25%, 61.46%, and 8.44% compared to the existing literature. Device-I achieved an I_ON/I_OFF improvement of 2.57 times and 1000 times and reduced SS and DIBL by 4.15% and 68.89%, respectively, compared to existing work.

Optimized inverters built with these devices showed significant noise margin enhancements. Inverter-1 improved NM_H by 38% and NM_L by 44%, while Inverter-2 increased NM_H and NM_L by 40% and 37%, respectively. These improvements highlight the suitability of the proposed devices for low-power digital and embedded systems applications, including SRAM, control circuitry for power converters and couplings, and other related logic circuits, making them a vital step toward a sustainable future in reducing carbon emissions in sustainable smart cities by using semiconductor industries. Future work will further develop and test the new device outlined in this work, and look to implement prototypes of low-cost, low-energy IoT end devices based upon its core design.