A Fast Recovery SiC TED MOS MOSFET with Schottky Barrier Diode (SBD)

Abstract

Achieving low conduction loss and good channel mobility is crucial for SiC MOSFETs. However, basic planar SiC MOSFETs provide challenges due to their high density of interface traps and significant gate-to-drain capacitance. In order to enhance the reverse recovery property of the device, a Schottky barrier diode (SBD) was added to the source contact area, the top of the current spreading region, of a trench-etched double-diffused SiC MOS (TED MOS). Two types of SBD structures were optimized to improve the electrical properties using 3D simulation software, “TCAD Silvaco”. During reverse recovery simulation, the carriers of the device were withdrawn from the SBD, indicating that the new design was effective. It also showed that the recovery properties of the new design depended on temperature, carrier lifetime, and the work functions of metals. All the new designs were evaluated in various circumstances to determine the trend. Ultimately, in high-speed switching circuits, the SiC TED MOS with SBD structure efficiently boosted switching speed, while reducing switching loss.

1. Introduction

The SiC MOSFET was first introduced more than a decade ago, and it stood out due to its simple technological craftsmanship, good unit consistency, and high avalanche energy. In 1997, the SiC DMOSFET, the first double-diffused silicon carbide, was successfully manufactured, but it suffered from the problem of high oxygen electric fields [1]. The JFET effect caused the on-resistance to increase due to the small N-region close to the P-body area being restricted. The high density of interface traps and high gate-to-drain capacitance also made it challenging to overcome this effect. To mitigate this issue, Y. Li proposed an unique SiC vertical trench-gate metal oxide semiconductor field-effect transistor (UMOS-FET) with counter-doped channels [2]. Additionally, R. Howell developed a large-area 10-KV 4H-SiC DMOSFET by growing an epitaxial regrowth layer on top of a p-well implanted region by means of an N${}_{20}$-based gate oxidation process [3]. Recently, an increasing number of research groups have used trench-etched technology to enhance device properties. Due to its potential to provide highly efficient power systems, silicon carbide (SiC) trench MOS with decreased on-resistance (R${}_{on}$) has drawn considerable interest. A DMOS has a wider cell pitch than the trench MOS. For instance, to improve device performance, N. Tega’s research team developed a unique trench-etched double-diffused SiC MOS (TED MOS) [4].

In SiC TED MOS, with its several trenched carrier channels, the impact of trench-MOS cell pitch illustrated that, with the increase in trenched channel numbers, there existed lower on-resistance but more gate-to-drain capacitance, resulting in a trade-off. TED MOS was shown to have a wider channel width than conventional DMOS as TED MOS’s trench pitch shrunk [5]. In TED MOS, both the high mobility and wide (W${}_g$) contribute to improved channel resistance. Additionally, the TED MOS structure attained low interface trap density, particularly in the trench side-wall (TSW) [6]. As a result, SiC TED MOS performed better than DMOS in many ways. Herein, we introduce an SBD on the source contact at the top of the current-spreading region to further elevate the reverse recovery performance of the device. Many research groups have proposed numbers of innovative device structures by integrating the Schottky barrier diode (SBD) in the super junction structure or 4H-SiC trench MOSFETs [7,8,9,10,11,12,13]. Usually, an external SBD, packaged with SiC MOSFET, is used for this task. Herein, we propose the SiC MOSFET integrated with SBD in order to reduce the package cost and parasitic inductance. For example, the research group of Weifeng Sun raised a new device structure by exploring an oxide pillar to separate the n-pillar and p-pillar, which acquired a Schottky diode between the source contact at the top of the p-pillar and p-base. The hole density in the drift region was correspondingly lowered due to the considerable reduction in the hole carrier of the p-pillar injected in the reverse condition [14]. Zhonglin Han proposed a novel 4H-SiC trench MOSFET integrated with mesa-sidewall SBD (TMS-SBD) and compared it with the trench MOSFET integrated with the SBD located on the mesa (TM-SBD). They found it to be more efficient in facilitating the TMS-SBD to achieve a larger breakdown voltage (BV), a lower electric field in the gate oxide, and a better trade-off between BV and specific on-resistance [15]. From the brief review above, it seemed more reasonable to combine SiC TED MOS with the SBD to find out if there is an optimization in the recovery characteristic.

In this work, an SBD under distinct conditions, such as different work functions, temperature, and carrier lifetime, was integrated so as to promote reverse recovery performance by altering the carrier extraction path inside the device. It was valid to utilize a TCAD Silvaco simulation to explore the theory of SiC TED MOS with several parameters, such as channel length, and carrier concentrations, in detailed simulation processes, such as defining meshes, regions, materials, electrodes, models, and methods. Various characteristics, like threshold voltage and current collapse, were tested. A brand new SBD structure was then investigated and obtained an optimized size under the same conditions as before. We found it to be convincing that the SiC TED MOS with SBD could effectively increase the switching speed and reduce the switching losses in high-speed switching circuits.

2. Device Structure Design and Simulation Setup

The schematic of the 3D view for SiC TED MOS, with and without SBD, is shown in Figure 1a,b, as well as the cross-section along two axes (Figure 1c,d). In this study, we explore the device characteristics within three trenched-etch channels, and SiC TED MOS with SBD is distinguished from the typical SiC TED MOS by depositing a parallel SBD on the source contact at the top of the current spreading region in a basic TED MOS structure. All device simulations and mix-mode simulation results were derived from simulations software Silvaco TCAD 2021 and the modeling process included defining meshes, regions, materials, electrodes, and doping concentration. The SiC TED MOS can be divided into the current drift region, current spreading region, left and right channels, and P-body region, where an ‘Atlas 3D’ module is necessary to establish a complete model. The parameters of SiC TED MOS are shown in

Table 1. Key parameters for SiC TED MOS with SBD.

Parameter	Values	Parameter	Values
Drift Region Length	25 $\mathsf{\mu }$m	Drift Region Depth	5 $\mathsf{\mu }$m
Current Spreading Region Length	8 $\mathsf{\mu }$m	Current Spreading Region Thickness	3 $\mathsf{\mu }$m
n${}^{+}$-SiC concentration	1 × 10${}^{19}$ cm${}^{-3}$	n${}^{-}$-SiC concentration	1 × 10${}^{17}$ cm${}^{-3}$
P-Body concentration	5 × 10${}^{15}$ cm${}^{-3}$	carrier lifetime	100 $\mathsf{\mu }$s
Side Channel Height	1 $\mathsf{\mu }$m	Bottom Channel Wide	1 $\mathsf{\mu }$m
Channel Length	8 $\mathsf{\mu }$m	source1 metal work function	4.7–4.9 eV

. In this study, the TED MOS model with three channels is established, and, in order to further explore the influence of the newly-introduced SBD structure, we set the same parameters among all three structures, such as current scattering region concentrations, current drift region concentrations, n+source concentration, n-substrate concentration, and p-body concentration. By setting a reasonable mesh density, and allocating regions for all functional parts, a numerical solution method for TCAD is also essential. The isotherm drift–diffusion model requires the following three equations to be solved: electron concentration, potential, and hole concentration. It is of primary significance to perform calibration of the III-V compound semiconductor parameters and, fortunately, ‘atlas 3D’ is equipped with default 4H-SiC parameters, such as interface charge density, surface recombination velocity, dielectric permittivity, etc. Comparing these parameters with several research papers that include a Silvaco TCAD simulation, such as the work of Yagong Nan, Liao Yang, Kevin Matsui and so on [16,17,18,19,20], it was more reasonable to carry out the following simulation process.

Various models were used before running static and dynamic simulations. The IMPACT SELB impact ionization model was used for activating avalanche breakdown simulations, and, in this study, we set gate voltage at two values (−5 V and 0 V) in breakdown tests to attain reverse breakdown voltage and forward breakdown voltage. The SRH was used for the carrier generation and recombination model. The FERMI was used for the fermi statistics model. The FLDMOB and ALBRCT were used to simulate the mobility and saturation velocity effects. The CALC.STRAIN was used to consider the strain. The POLARIZATION model was invoked for epitaxial strain due to lattice mismatch and spontaneous polarization. After setting up the suitable models, it was equally significant to choose computational methods and, for almost all cases, the NEWTON method was preferred, so it was the default in the static and dynamic simulations.

In dynamic simulations, during the forwarding turn-on simulations, the P-body region was under a forward voltage bias state, as well as the carriers inside the P-body region and current spreading region. When the device was switched off, the transverse field exhausted the carriers inside the body in a transverse manner, leaving the non-equilibrium carriers inside the device in a point and equilibrium state. After that, we could simulate the basic structure for SiC TED MOS, with and without SBD. Mix-mode simulation was utilized in exploring the DUTs test, to investigate the turn-on and reverse characteristics of three structures, as it is more feasible in setting up numerous circuit elements, like capacitance and inductance. It provides several valuable benefits as no compact model needs to be specified for a physically-based numerical device. In addition, approximation errors introduced by compact models can be avoided; particularly for large transient signal performance [21]. The DUTs test was conducted at an applied voltage of 300 V voltage, with a current source of 10 A applied and a reverse change rate of 100 A/$\mathsf{\mu }$s. There are other optional methods to set several parameters, such as temperature, carrier lifetime and work functions, which can obtain various device working conditions. Finally, the ‘Tonyplot’ module was utilized to plot the mix-mode simulation results and to visualize the electric field and capacitance distribution.

3. Results and Discussions

The drain current-gate voltage (I${}_d$-V${}_g$) characteristics of the test structures are plotted in Figure 2a,b. Figure 2a is a linear scale plot, while Figure 2b is in a log scale. Once the channel current reached 1 $\mathsf{\mu }$A, gate voltages could be extracted to compare the threshold voltage between the two devices. As the gate voltage increased, the TED MOS without SBD turned on when the gate voltage was equal to 5.23 V. There was a small difference between the TED MOS threshold and SBD (V${}_g$ = 5.43 V). After introducing the SBD structure, the threshold voltage increased, while the channel current decreased slightly, due to the expansion of gate-to-drain capacitance (C${}_{gd}$) and interface trap density between the current spreading region and the P-body region. Without an SBD structure, a thin oxide layer was deposited on the top of the current spreading region, so this oxide layer should be removed before defining a new SBD electrode. More carriers became trapped so a higher gate voltage was needed to activate the device. On the other hand, the channel mobility in a high electrical field decreased steeply because of the scattering factor in the high electric field. For example, extra metal deposition generates more scattering from surface roughness. Figure 2c illustrates the reverse breakdown voltage of the studied device under the condition that gate voltage (V${}_g$) was −5 V, guaranteeing that all carriers were trapped, and Figure 2d depicts the forward breakdown voltage when the gate voltage was set to 0 V. All devices were under reverse voltage breakdown when drain voltage reached 1600 V and the forward breakdown voltage value achieved 1500 V. It was obvious that the SBD structure would not significantly change the limit of punch-through, as it is related to carrier concentration and channel properties. What is more, there was not much difference in the leakage current under the breakdown simulation, meaning that introducing an SBD structure did not deteriorate avalanche breakdown.

In the current collapse simulation (Figure 3a), the SiC TED MOS, with and without the SBD structure, experienced circulation between on state and off state. Firstly, the gate voltage was set to 10 V to ensure that all carriers were extracted to the spreading channel, and the drain voltage was set to 1 V to drive the channel current. After 1ms, the device switched from on state to off state by altering the gate voltage to −5 V and boosting the drain voltage to 300 V. The peak channel current increased dramatically at 1 $\mathsf{\mu }$s, 4.48 × 10${}^{-5}$ A for the TED MOS with SBD and 4.32 × 10${}^{-5}$ A for the one without SBD, respectively. Once the device had been turned off for almost 1ms, on-state arrived when the transient time equaled 2 $\mathsf{\mu }$s by resetting all voltages to their initial values. The collapse current of the device with SBD was 2.36 × 10${}^{-5}$ A, while without SBD it only reached 2.06 × 10${}^{-5}$ A. This indicated the peculiarity that the SBD turns into a forward bias state when the device changes from the open state to an abrupt off state. The SBD helped to extract more carriers out from the P-Body region, leading to an augmentation of these properties. In Figure 3c three distinguished work functions were defined, with a drain voltage of 10 V and a gate voltage of 100 V, respectively. As the gate voltage decreased, leakage current could be plotted in a log scale plot. SiC TED MOS with SBD exhibited a significantly higher current density when compared to those without SBD, typically by two orders of magnitude. Nonetheless, an increase in the work function of the metal used in constructing the devices resulted in a reduction of the leakage current. The variation in the conduction band energy of the TED MOS devices with different work functions of the metals is depicted in Figure 3d, where it is evident that a higher work function of the metal resulted in a corresponding increase in the Schottky barrier height. The x-axis of Figure 3d is the vertical distance from the top SBD structure to the current spreading region and it is intuitive that, for example, the conduction band of the TED MOS with 4.9 eV metal work function was higher than that with 4.7 eV and 4.8 eV, hampering the carriers from spreading through the SBD structure. so less leakage could be seen. This phenomenon similarly affected the recovery characteristic of the devices with different work functions.

Figure 4a demonstrates the source and source1 currents under the condition that the work function of SBD equaled 4.8 eV. The newly introduced SBD structure was attained by depositing an additional electrode, called source1, and, when calculating the recovery current (I${}_{Recovery}$), both I${}_{Source}$ and I${}_{Source1}$ should be taken into account as a whole. The reverse recovery characteristics of the SiC TED MOSFET devices ultimately depend on the parasitic diode, which becomes a forward bias state and extracts the stored charge when the device changes from on state to off state. It was evident that, in the DUTs test, when the whole device turned on at the beginning, the current mainly flowed through the source electrode. When circuits were switched off, the primary current in the SiC TED MOS was the main current generated by the source1 conduction. This means that the new SBD structure can work as a fly-back diode.

Figure 4b illustrates the reverse recovery current, which was added by source1 and the source current. The inset illustrates the test circuit configuration, wherein the device under test (DUT) and the current transformation rate di/dt were set to 100 A/us by setting RG = 300 $\Omega$ and Conv-SJ-MOSFET (CONV.) to the low side switch. The resistance played the part of circuit switch. After adding an SBD structure, the t${}_{rr}$ descended significantly, and the I${}_{rr}$ achieved 3.08 A, which was reduced by 52.2% for Si TED MOS (6.45 A), the Q${}_{rr}$ attained 1.76 $\mathsf{\mu }$C, which decreased by 53.8% for Si SJ (3.81 $\mathsf{\mu }$C). It is cogent that the introduction of an SBD structure could apparently augment the reverse recovery characteristics.

The leakage gate current is shown in Figure 4c, explaining that a high Schottky barrier height could restrain it, and the DUTs test for the turn-on circuits indicated a gap between SiC TED MOS, with and without SBD (Figure 4d). After applying the SBD structure, the aggrandizement in the contact area between the gate and the drift region caused an enhancement in the gate-to-drain capacitance C${}_{gd}$. Due to its increased capacitance, the charging time for SiC TED MOS was prolonged and had a slight side effect for transmission, but this loss was not particularly appreciable, as more benefits could be gained in the recovery characteristics.

In order to explore more optimized structures, we split the entire SBD structure into two crosswise region transverse SBD structures (Figure 5) and probed into the optimal size for these. In the Figure 5a, these two structures did not change their lengths along the x-axis, while the variable was the width along the y-axis, and they covered most of the area near the top, side, and bottom channels to draw carriers out of the device as much as possible under reverse recovery simulation. Several distinct widths for two SBD structures were simulated under the DUTs test, and their turn-on characteristics are shown in Figure 5b with the 4.8 eV work function. It can be observed in the second inset, that the coverage area of the newly-introduced SBD structure proved to be the essential factor, as the transient time for all test structures had a gap and there was a marginal effect of optimized SBD width. With a width of 1.5 $\mathsf{\mu }$m, the SBD had the lowest turn-on transmission time. Comparing the entire SBD structure in Figure 1b, the turn-on delay of the 1.5 $\mathsf{\mu }$m wide SBD structure was less than that of an unabridged SBD structure. This is because the gate-to-drain capacitance could be reduced without significantly reducing the channel current.

Figure 5c illustrates the same trend that was observed in the reverse recovery simulation. Similarly, the appropriate width lay in the middle range of variables. After using the innovative SBD structure, the t${}_{rr}$ decreased more rapidly than it did for the basic SBD structure, and the I${}_{rr}$ attained 1.13 A, which was a reduction of 82.5% for Si TED MOS (6.45 A), while the Q${}_{rr}$ achieved 0.644 $\mathsf{\mu }$C, which was a reduction of 83.1% for Si SJ (3.81 $\mathsf{\mu }$C). For on resistance, we set the initial conditions of V${}_g$ = −5 V and V${}_d$ = 300 V to ensure that the carriers were sufficiently trapped in the traps. Then, the gate voltage changed to 15 V while the drain voltage decreased to 10 V. When the device switched from the off state to the on state for 100 $\mathsf{\mu }$s, the data was noted to calculate the on-state resistance. By setting the on-state resistance of the SBD structure (Width = 3 $\mathsf{\mu }$m) as 1, all studied structure data were as shown in Figure 5d. In conclusion, setting the SBD structure with width = 1.5 $\mathsf{\mu }$m obtained optimized device characteristics.

Three other factors were simulated (temperature, carrier lifetime, and work functions) during the DUTS reverse tests and the impact of the results on the I${}_{Source1}$ are shown in Figure 6. The structure in Figure 6a is described in Figure 1b and it is apparent that, with the aggrandizement of SBD work functions, the reverse recovery current experienced augmentation as well (Figure 3d). As the Schottky barrier became higher, fewer carriers were spread through it, as plotted in Figure 3d. In this situation, the higher work function was detrimental to the reverse recovery characteristic. As a result, less accumulated charge could be released and this negatively affected reverse recovery. Higher device temperature also had a side effect on the device because it impaired carrier mobility, making it more challenging to extract minor carriers from the device (Figure 3d). In Figure 6d, different carrier lifetimes were tested, and the conclusion drawn that carriers with higher lifetimes led to worse reverse recovery characteristics. The reason is that it takes longer for carriers with higher lifetimes to recombine, and it is harder to consume an accumulated charge, which accounts for the worse recovery characteristic.

For the original SiC TED MOS, the structure in Figure 7a was the same as in Figure 1a, as it did not have an integrated SBD structure, and only the influences of temperature and carrier lifetime were investigated, seen in Figure 7b,c. The same trend could be drawn, since a similar mechanism applied, and it was more difficult for the device to have better reverse recovery characteristics under high temperature and carrier lifetime conditions. The SiC TED MOS with two transverse SBD structures was also explored for the effect of work function, temperature, and carrier lifetime. Figure 5a depicts the basic structure of Figure 8a, and, by examining Figure 8b–d, it can be deduced that temperature, carrier lifetime, and work functions each had an unique impact on the device’s recovery characteristics.

4. Conclusions

In this study, an integrated SBD structure in SiC TED MOS, devised for the purpose of improving reverse recovery characteristics, was demonstrated. The simulated results showed that its breakdown voltage, threshold voltage, and current collapse are acceptable, albeit with increased gate-to-drain capacitance. The SiC TED NOS with SBD decreased the I${}_{rr}$ and Q${}_{rr}$ by 52.2% and 53.8%, respectively, in comparison to the SiC TEDNOS without the SBD. Moreover, the depositing of two transverse SBD structures were more effective in recovery characteristics, and the I${}_{rr}$, Q${}_{rr}$ of SiC declined by 82.5%, and 83.1%, compared to the SiC TED MOS without the SBD structure. In addition, three other factors, namely, temperature, work function, and carrier lifetime, were simulated. The tendency shows that the device prefers an appropriate temperature, low work function, and low carrier lifetime as more carriers are extracted under reverse circuits. The SiC TED MOS with the SBD structure can effectively aggrandize the switching speed and reduce switching loss in high-speed switching circuits.