A High Gain Modified Quadratic Boost DC-DC Converter with Voltage Stress Half of Output Voltage

Abstract

The application of the high gain boost DC-DC converter is gaining more attention due to an increasingly wide range of applications for sustainable green energy solutions, as well as other high voltage applications. In this study, a modified high gain quadratic boost converter is proposed using a single switch. The proposed topology is a member of the family of the non-isolated category with a common ground feature and can operate in a wide range of duty ratios, and is able to provide the required voltage gain. In this proposed circuit configuration, a dual voltage boost cell was formed by incorporating two capacitors in series with two inductors of a conventional quadratic boost converter. Additionally, a capacitor was integrated with a second voltage boost cell. This special configuration increases the voltage gain as well as reduces the voltage stress across the switch. To show its feasibility, a 200-W prototype setup with 48 V input and 400 V output was designed, and the required PWM signal was fed from the microcontroller unit. A detailed analysis of the design parameters and losses are formulated and are shown in this paper. The simulation was performed in SIMPLIS software, and the experimental results agreed with the obtained output voltage gain. The proposed topology showed a peak efficiency of 94.5% at 150-W output power after considering the power losses in all the components of the PCB.

1. Introduction

The global warming problem is becoming more severe nowadays, due to which, research across all disciplines to reduce greenhouse gases is ongoing. Generally, the burning of fossil fuels is the largest source of greenhouse gas production [1]. To make our environment cleaner, renewable energy is the most effective solution currently available. Although nuclear energy has the potential to provide sustainable green energy, its post-process (i.e., containing the nuclear waste) is very dangerous to our environment, and its harmful effect will continue for many years because of the exponential decay process [2]. Renewable energy, mainly solar power-based energy, is the only viable source for enormous amounts of energy, which very soon could fully substitute fossil fuel-based energy systems [3]. However, due to certain limitations, each solar photovoltaic cell generates a very low output voltage in terms of DC bias, whereas many appliances which utilize electricity have until now required a much higher voltage level, both in terms of AC and DC. In order to boost the output voltage and power level, a series and parallel connection of solar cells were performed, but that is still not sufficient enough [4]. On the other hand, the output voltage of the solar module can provide a maximum of 48 V, so to provide the required voltage level for the electronics, a converter is required that offers the necessary solution by working in the form of energy conversion, i.e., a boost converter. Additionally, appliances that require a voltage level in the range of the available bias that a solar module can provide are still in need of a buck-boost converter [5,6,7] to maintain the voltage regulation. Moreover, as transportation systems are shifting from fossil fuel-based power to electric vehicles [8], in order to drive the vehicles the power converter needs to be capable enough to provide a sufficient voltage level for the inverter to drive the main drive system, i.e., high rated induction motor including the other application parts of the electric vehicle [9]. In addition, the application of high voltage gain DC-DC converters for industrial application has been seen for a long time [10], and in the future, they need to become more compact and sophisticated to maintain the sustainability for an application in industry 4.0 [11,12,13,14]. As a result, the research on boost DC-DC converters is drawing more and more attention as their potential application is increasing substantially. In Figure 1 the general application of DC-DC converter is presented.

In general, theoretically, the well-known traditional simple boost converter can achieve a high gain (i.e., 10 times) at a duty ratio near 90–95%, but practically, it is impossible to achieve due to the presence of parasitic resistance in passive components, as it limits the charging current in the inductor loop [15]. Additionally, operating at a very high duty cycle may create a reverse recovery problem for the power diode, so it reduces the system performance by increasing the conduction loss of the converter, which further limits the system efficiency [10]. To overcome all these challenges, the operation of the boost converter is preferable at a lower duty ratio [16]. The reported quadratic boost topology has the potential to boost the voltage level by following the quadratic equation, which, interestingly, can provide much higher voltage gain at a lower duty ratio [17]. In addition, several other techniques have been extensively employed to boost the voltage gain, and the Voltage Multiplier Cell (VMC)-based configuration is one of them [18]. A switched capacitor-based DC-DC converter has already been reported by various research groups [19,20]. Though it has a very simple structure and is an effective technique that provides a high voltage gain by reserving a very low space for the converter, a high inrush current is one of the major problems for this switched capacitor VMC-based boost converter. To overcome this issue, numerous different topologies have also been reported so far [21,22,23,24,25,26,27]. Additionally, the high gain boost converter can also be classified as isolated and non-isolated types. Normally, the isolated topology uses magnetic coupling (i.e., coupled inductor) between the source and load to provide the isolation [21,22,23,24,25]. Moreover, coupled inductor-based proposed converters are quietly very popular due to their capability for providing very high voltage gain by changing the turn ratio, but an extra clamp circuit is needed to improve the system efficiency [28,29]. Moreover, though it increases the voltage gain a more precise magnetic design is also needed. In addition, in most of the reported coupled inductor-based boost converters, the authors have designed the magnetics by a 1:1 or sometimes 1:2 turn ratio [28]. Owing to having complexity, the overall cost is always increased for a coupled inductor-based configuration. Moreover, for high power applications, the resonant converter, mostly the LLC topology, has been showing its potential over recent decades. However, from the cost and control point of view, it is much more complex, and the complexity level increases when more switches are used for the possible application [26,27]. Another major drawback of the conventional boost and conventional quadratic boost converter is the voltage stress across the switching device, which is very high as the value of the stress voltage is exactly equal to the output voltage [29,30,31]. Many research groups have already proposed new techniques that can reduce the voltage stress up to a certain limit [32,33]. Although some reported results have reduced the voltage stress across the switch but in order to do that, in most cases, the converter lost its simple common ground feature [34,35]. So, the integration of more passive components with series and parallel inductors of quadratic boost topology is one of the potential solutions for non-isolated based QBC, which not only helps to increase the voltage gain with lower duty but also fulfills the general requirement by reducing the voltage stress across the switch including the easy control technique. Additionally, inductors dominated by VMC utilize more inductors (i.e., more than two inductors) which further increases the converter size [36].

In this study, a new, modified high gain quadratic boost converter is presented, which was constructed with consecutive mixed voltage boost cells. The proposed converter could be used in various applications where a non-isolated high gain DC-DC converter could be considered. It has various advantages over recently reported non-high gain DC-DC boost converters, which are listed as follows.

• Using only a single switch, the high voltage gain is achieved, which is the first potential advantage over other reported studies where more switches have been used to boost the voltage level.
• Another advantage is the control strategy which is generally very easy for a single switch-based topology.
• The voltage stress across the power MOSFET switch of the proposed study is very low, which is half of the output voltage.

The detailed circuit description of the proposed topology with the proper evolution process is discussed in the following section, and then the ideal and non-ideal voltage gain is calculated. After that, the design of the passive components and the efficiency calculation was conducted. In the later section, the comparison study was conducted, followed by the simulation and experiment results analysis. In the later section, the gain and phase plots are shown for stability analysis.

2. Evolution of the Proposed Modified Quadratic Boost Converter

2.1. Conventional Quadratic Boost Converter

The conventional quadratic boost converter is comprised of two inductors, L₁ and L₂, three diodes, D₁, D₂, and D₃, a single switch, and two capacitors, C₁ and C₀. The circuit diagram of the CQBC is shown in Figure 2.

In a conventional quadratic boost converter, during the first mode of operation, when the switch is on, the inductor L₁ is charged by the source voltage, whereas the inductor L₂ is charged by the capacitor C₁. At this instance, the diode D₃ will be on reverse bias, and the output capacitor, C₀, will transfer the energy to the load. During the second mode, the diode, D₁, will be on reverse bias, and both of the inductors transfer the energy to the load through diodes D₂ and D₃ with a boosted voltage, following the voltage gain formula $\frac{1}{{\left(1-d\right)}^2}$ where the two capacitors store the energy.

2.2. Quadratic Boost Converter with Single Voltage Lift Cell

In this modified QBC shown in Figure 3, the additional capacitor C₂ is connected in series with inductor L₂, which plays a significant role in boosting the output voltage as well as reducing the voltage stress across the switch. In this topology, when the switch is on, the capacitor C₁, which transfers the energy to the inductor L₂, also charges the capacitor C₂ through the diode D₂ at the same time the inductor L₁ is energized by the input voltage. During the second mode of operation, both the inductor L₁, L₂, and capacitor C₂ are involved in boosting the output voltage. The output voltage of this modified topology is higher than the conventional quadratic boost converter, followed by the voltage gain formula $\frac{\left(2-d\right)}{{\left(1-d\right)}^2}$. The voltage stress of this proposed topology is reduced significantly to a certain limit which is another advantage over the CQBC.

2.3. Quadratic Boost Converter with Dual Voltage Lift Cell

Further, the output voltage can be boosted by implementing the same technique with the first inductor, L₁. The proposed circuit topology by Shahrukh khan et al. [37] is shown in Figure 4 where two capacitors, C₁ and C₂, are connected in series with the inductors L₁ and L₂ respectively.

During the first mode of operation, the first voltage lift cell (i.e., L₁ and C₁) is charged by the source voltage through diode D₂. In this mode, the necessary charging current for the capacitors C₁ and C₂ is provided by the source through the diode D₁ and D₃, respectively. Whereas, the second voltage lift cell (i.e., L₂ and C₂) is charged by the capacitor C₃. During mode 2, the four passive components (i.e., L₁, L₂, C₁, C₂) transfer the energy to the load with a voltage gain following $\frac{{\left(2-d\right)}^2}{{\left(1-d\right)}^2}$. In [37], the characteristics of the converter were proposed and studied.

2.4. Proposed Modified Quadratic Boost Converter with Integrated Dual Voltage Lift Cell

The generalized circuit diagram of the proposed converter is depicted in Figure 5. The studied high gain boost converter consists of two inductors, L₁ and L₂, five capacitors C₁, C₂, C₃, C₄, C₀, and six diodes D₁, D₂, D₃, D₄, D₅, D₆, and most importantly, a single power MOSFET switch S₁. The first voltage boost cell consists of four components, i.e., L₁, C₁, D₁, D₂, whereas the second integrated voltage boost cell consists of five components, i.e., L₂, C₂, C₄, D₃, and D₄. Both the configuration during two-mode of operation is discussed in a later section. In order to calculate the ideal voltage gain of the proposed converter, it was assumed that all the passive components were lossless and ideal. Additionally, the diode forward voltage drops and the parasitic resistance were ignored for calculating the ideal voltage gain, whereas, in the later section, the non-ideal voltage gain was calculated considering the diode forward voltage drop. Details of the characteristics of the two-mode operation are discussed as follows.

2.4.1. Operation Principle and Ideal Voltage Gain Calculation, Continuous Current Mode (CCM)

Mode 1 [0, DT]: Switch ON, D₁, D₂, D₃ ON

When the switch was turned on by the PWM signal, the drain terminal was connected to the ground internally; as a result, the energy transfer process occurred from the source to the passive component and from the passive component to other passive components (i.e., capacitor to inductor). The corresponding circuit configuration is shown in Figure 6.

During this mode of operation, the diodes D₁, D₂, and D₃ will be forward biased and will carry the necessary current to transfer the energy. The diodes D₄, D₅, and D₆ will be reverse biased during the first mode of operation. The inductor L₁ and capacitor C₁ are charged by the source voltage (i.e., V_in) through diode D₂, where the charging current of the capacitor C₁ is supplied by the diode D₁. In the second integrated voltage lift cell, the capacitor C₃ transfers the energy directly into the inductor L₂, and the capacitor C₂ is charged by the summation of the voltage source supplied by the capacitors C₃ and C₄. On the other hand, the output capacitor C₀ transfer the necessary load current to the load.

The characteristics equations during the first mode of operation are as follows.

$$V_{L1}=V_{in}=L_1\frac{d{i}_{L1}}{dt}$$

(1)

$$V_{C1}=V_{in}$$

(2)

$$V_{L2}=V_{C3}=L_2\frac{d{i}_{L2}}{dt}$$

(3)

$$V_{C2}=V_{C3}+V_{C4}$$

(4)

$$V_{C0}=-V_0$$

(5)

Mode 2 [DT, T]: Switch OFF, D₄, D₅, D₆ ON

During this interval period, the switch was turned off, ideally with the withdrawal of the PWM signal. The corresponding circuit configuration during mode 2 is shown in Figure 7. In this mode of operation, the energy is directly transferred from the source to the load through the passive component, and it transfers the energy to the other passive component (i.e., C₃, C₄). The diodes D₁, D₂, and D₃ will be in reverse bias; on the other hand, the D₅ and D₆ will carry the necessary current for the load. The charging current for capacitor C₄ is provided by the inductor L₂ through diode D₄.

The characteristics equation during this mode is derived in the following section.

$$V_{L1}=V_{in}+V_{C1}-V_{C3}$$

(6)

$$V_{L1}=2V_{in}-V_{C3}$$

(7)

$$V_{C4}=-V_{L2}$$

(8)

$$V_{L2}=V_{C3}+V_{C2}-V_0$$

(9)

Putting the Equation from (8) and (9) into the Equation (4)

$$V_{C2}=V_{C3}+\left(-V_{C3}-V_{C2}+V_0\right)$$

(10)

$$2V_{C2}=V_0$$

(11)

$$V_{C2}=\frac{V_0}{2}$$

(12)

To obtain the voltage gain, the volt-second method is applied on both Inductor L₁ and L₂. The equations are as follows.

$${{\displaystyle \int }}_0^T{V}_{L1}\left(t\right)·dt=0$$

(13)

$$V_{in}\times dT+\left(2V_{in}-V_{C3}\right)\times \left(1-d\right)T=0$$

(14)

$$V_{C3}=\frac{\left(2-d\right)}{\left(1-d\right)}$$

(15)

$${{\displaystyle \int }}_0^T{V}_{L2}\left(t\right)·dt=0$$

(16)

$$V_{C3}\times dT+\left(V_{C3}+V_{C2}-V_0\right)\times \left(1-d\right)T=0$$

(17)

Putting the value of V_C2 from Equations (12)–(17) the below equation is obtained.

$$V_{C3}\times dT+\left(V_{C3}-\frac{V_0}{2}\right)\times \left(1-d\right)T=0$$

(18)

$$V_0=\frac{2}{\left(1-d\right)}\times V_{C3}$$

(19)

Putting the value of V_C3 from Equations (15)–(20) the ideal voltage gain of the proposed converter is calculated as follows.

$$V_0=\frac{2\left(2-d\right)}{{\left(1-d\right)}^2}\times V_{in}$$

(20)

$$Voltae gain \left(M\right)=\frac{V_0}{V_{in}}=\frac{2\left(2-d\right)}{{\left(1-d\right)}^2}$$

(21)

2.4.2. Non-Ideal Voltage Gain Calculation Considering the Diode Voltage Drop

The diode’s voltage drop is one of the main factors for concern for the deviation of the output voltage from the actual voltage gain. For the non-isolated-based high gain quadratic boost converters, mainly in voltage boost cells-based QBC, there are more diodes to store the energy in the passive components (i.e., the extra passive components for boosting the voltage). The voltage reduction at each step is added together and reflected in the output voltage gain. The equivalent series resistance (ESR) value of each passive component was considered negligible. In the below section, the voltage gain is formulated considering the diode’s forward voltage drop (i.e., V_D) following the same previous method as discussed in the earlier section.

Mode 1 [0, DT]:

Referring to Figure 6, during mode 1 the characteristics equations are as follows

$$V_{L1}=V_{in}-V_D$$

(22)

$$V_{C1}=V_{in}-2V_D$$

(23)

$$V_{L2}=V_{C3}$$

(24)

$$V_{C2}=V_{C3}+V_{C4}-V_D$$

(25)

Mode 2 [DT, T]:

Referring to Figure 7, during mode 2 the corresponding equations are as follows

$$V_{L1}=V_{in}+V_{C1}-V_{C3}-V_D$$

(26)

$$V_{L1}=2V_{in}-V_{C3}-V_D$$

(27)

$$V_{C4}=-V_{L2}+V_D$$

(28)

$$V_{L2}=V_{C3}+V_{C2}-V_0-V_D$$

(29)

Now applying the volt-sec balance method to the inductor L₁ the corresponding voltage gain was calculated and is shown below.

$$V_{C3}=\frac{ \left(2-d\right)}{\left(1-d\right)}{V}_{in}-\frac{ \left(3-2d\right)}{\left(1-d\right)}{V}_D$$

(30)

Applying the volt-sec method on Inductor L₂ and the derived non-ideal voltage gain is shown as follows

$$V_0=\frac{2 \left(2-d\right)}{{\left(1-d\right)}^2}{V}_{in}-\frac{ \left(7-6d+d^2\right)}{{\left(1-d\right)}^2}{V}_D$$

(31)

The related waveform of the ripple current of the inductor, ripple voltage of the capacitor, and the current waveform of the diode and switch are depicted in Figure 8.

3. Design Considerations

3.1. Design of the Inductor

The inductors for this proposed topology were designed based on the current ripple and the applied voltage across it. The differential equation for each of the inductor during the first mode of operation is stated as follows. The minimum requirement value of the inductors was also calculated, which sets the boundary of the CCM and DCM mode of the converter characteristics.

$$V_{L1}=L_1\frac{d{i}_{L1}}{dt}=V_{in}$$

(32)

$$L_1=\frac{V_{in}dT}{\mathsf{\Delta }{i}_{L1}}$$

(33)

$$V_{L2}=L_2\frac{d{i}_{L2}}{dt}=V_{C3}$$

(34)

$$L_2=\frac{V_{C3}dT}{\mathsf{\Delta }{i}_{L1}}=\frac{\left(2-d\right)V_{in}dT}{\left(1-d\right)\mathsf{\Delta }{i}_{L1}}$$

(35)

$$\mathsf{\Delta }{i}_{L1}=\frac{V_{in}dT}{L_1}$$

(36)

$$\mathsf{\Delta }{i}_{L2}=\frac{V_{C3}dT}{L_2}=\frac{\left(2-d\right)V_{in}dT}{\left(1-d\right)L_2}$$

(37)

The average current through L₁ and L₂ are as follows

$$I_{L1}=\frac{2I_0}{{\left(1-d\right)}^2}=\frac{2V_0}{{\left(1-d\right)}^{2}R}$$

(38)

$$I_{L2}=\frac{2I_0}{\left(1-d\right)}=\frac{2V_0}{\left(1-d\right)R}$$

(39)

$${(I_{L1})}_{min}=\frac{2V_0}{{\left(1-d\right)}^{2}R}-\frac{V_{in}dT}{2L_1}$$

(40)

$$L_1\ge \frac{d{\left(1-d\right)}^{4}R}{8\left(2-d\right)f_{sw}}$$

(41)

$${(I_{L2})}_{min}=\frac{2V_0}{\left(1-d\right)R}-\frac{d\left(2-d\right)V_{in}T}{2\left(1-d\right)L_2}$$

(42)

$$L_2\ge \frac{d{\left(1-d\right)}^{2}R}{8f_{sw}}$$

(43)

In Figure 8 the value of the minimum inductor vs. duty cycle was plotted from Equations (41) and (43) for the condition of the CCM, DCM, and Boundary condition mode operating mode.

3.2. Selection of the Capacitor

The capacitor was designed based on the ripple voltage ΔV_CX, the charging current following through it, the duty cycle, and the switching frequency f_sw, respectively. The corresponding differential equation of each capacitor was formulated and is given below.

$$\left\{\begin{array}{c}{\mathrm{C}}_1=\frac{\mathsf{\Delta }{Q}_1}{\mathsf{\Delta }{V}_{C1}}=\frac{\mathsf{\Delta }{I}_{C1}dT}{\mathsf{\Delta }{V}_{C1}}=\frac{\left(2-d\right)d{V}_0}{{\left(1-d\right)}^2\mathsf{\Delta }{V}_{C1}{f}_{sw}R}\\ {\mathrm{C}}_2=\frac{\mathsf{\Delta }{Q}_2}{\mathsf{\Delta }{V}_{C2}}=\frac{\mathsf{\Delta }{I}_{C2}dT}{\mathsf{\Delta }{V}_{C2}}=\frac{d{V}_0}{\left(1-d\right)\mathsf{\Delta }{V}_{C2}{f}_{sw}R}\\ {\mathrm{C}}_3=\frac{\mathsf{\Delta }{Q}_3}{\mathsf{\Delta }{V}_{C3}}=\frac{\mathsf{\Delta }{I}_{C3}dT}{\mathsf{\Delta }{V}_{C3}}=\frac{d{V}_0}{{\left(1-d\right)}^2\mathsf{\Delta }{V}_{C3}{f}_{sw}R}\\ {\mathrm{C}}_4=\frac{\mathsf{\Delta }{Q}_4}{\mathsf{\Delta }{V}_{C4}}=\frac{\mathsf{\Delta }{I}_{C4}dT}{\mathsf{\Delta }{V}_{C4}}=\frac{d{V}_0}{\left(1-d\right)\mathsf{\Delta }{V}_{C4}{f}_{sw}R}\\ {\mathrm{C}}_0=\frac{\mathsf{\Delta }{Q}_1}{\mathsf{\Delta }{V}_{C1}}=\frac{I_{C0}dT}{\mathsf{\Delta }{V}_{C0}}=\frac{d{V}_0}{R\mathsf{\Delta }{V}_{C0}{f}_{sw}}\end{array}\right.$$

(44)

3.3. Voltage Stress across Switching Device and Power Diode

The ideal voltage stress across power switch and power diodes are formulated and are shown as follows. In Figure 9 the steady state voltage and current waveform of each components is shown.

$$\left\{\begin{array}{c}{\mathrm{V}}_{sw}=\frac{V_0}{2}\\ {\mathrm{V}}_{\mathrm{D}1}=\frac{V_{in}}{\left(1-d\right)}\\ {\mathrm{V}}_{\mathrm{D}2}=\frac{{\mathrm{V}}_{in}}{{\left(1-d\right)}^2}\\ {\mathrm{V}}_{\mathrm{D}3}={\mathrm{V}}_{\mathrm{D}4}=\frac{V_0}{2}\\ { \mathrm{V}}_{\mathrm{D}5}=V_{C3}-V_{in}=\frac{V_{in}}{\left(1-d\right)}\\ {\mathrm{V}}_{\mathrm{D}6}=\frac{V_0}{2}\end{array}\right.$$

(45)

4. Formulation of Power Loss of the Proposed Studied Topology

To calculate the efficiency, the loss model was developed by considering the loss due to the parasitic resistance in each component of the system. In Figure 10, the corresponding circuit configuration is depicted.

4.1. Power Losses Calculation in Power Switch

The RMS current-carrying by the switch is denoted as $i_{S{W}_{rms}}$ and $P_{SW}$ _and $P_{on+off}$ are the conduction loss and switching loss of the switch. The corresponding formulated loss is calculated and is shown below.

(46)

4.2. Power Losses Calculation in Power Diodes

The RMS current following through the diode is represented as $i_{D{x}_{rms}}$. The power loss due to ESR of the diodes is denoted as $P_{rDx}$ and another loss due to the forward voltage drop is denoted as $P_{FwDx}$. So, the power loss in each diode is represented as

(47)

(48)

(49)

(50)

(51)

(52)

(53)

The total loss by the diode can be added together and represented as

$$P_{Dtotal}={\displaystyle \sum }_{i=1}^6{P}_{Di}$$

4.3. Power Losses in the Inductor Due to ESRs

The Root mean square current through the inductor is notified as $i_{L{X}_{rms}}$. The ESRs and the associated power loss are denoted as $r_{LX}$ and $P_{LX}$.

(54)

The total loss because of the ESRs of the Inductor can be obtained as

$$P_{Ltotal}={{\displaystyle \sum }}_{i=1}^2{P}_{Li}$$

4.4. Power Losses in the Capacitor

The power loss in a capacitor due to the parasitic resistance present in a capacitor is calculated by considering the RMS current flowing through each capacitor and is denoted as $P_{Cx}$. The equivalent series resistance (i.e., ESR) of each capacitor is represented by $r_{Cx}$.

(55)

(56)

(57)

(58)

(59)

Considering all working capacitors, the total accumulated loss can be calculated as

$$P_{Ctotal}={\displaystyle \sum }_{i=1}^5{P}_{Ci}$$

The total efficiency of the proposed converter was calculated by the below equation

$$\eta =\frac{P_0}{P_0+P_{Ltotal}+P_{Ctotal}+P_{Dtotal+P_{SW}}}$$

(60)

5. Comparison Analysis

A summary of recently proposed high gain, mostly quadratic boost-based topology, is discussed in this section.

Table 1. Comparison with a similar non-Isolated boost converter.

Topology	Switches	Diode	Inductor	Capacitor	Ideal Voltage Gain	Voltage Stress (Vs/Vin)	Common Ground	Ref
CQBC	1	3	2	2	$\frac{1}{{\left(1-d\right)}^2}$	$\frac{1}{{\left(1-d\right)}^2}$	Yes	[29]
Topology 1	1	5	2	4	$\frac{\left(3+d\right)}{\left(1-d\right)}$	$\frac{4}{\left(1-d\right)}$	No	[38]
Topology 2	1	5	2	4	$\frac{2}{{\left(1-d\right)}^2}$	$\frac{1}{{\left(1-d\right)}^2}$	No	[39]
Topology 3	1	3	3	3	$\frac{d}{{\left(1-d\right)}^2}$	$\frac{d}{{\left(1-d\right)}^2}$	Yes	[40]
Topology 4	1	3	2	2	$\frac{d\left(2-d\right)}{{\left(1-d\right)}^2}$	$\frac{1}{{\left(1-d\right)}^2}$	Yes	[41]
Topology 5	1	5	3	3	$\frac{d^2}{{\left(1-d\right)}^2}$	$\frac{1}{{\left(1-d\right)}^2}$	Yes	[42]
Topology 6	2	3	2	2	$\frac{1}{d\left(1-d\right)}$	$\frac{1}{\left(1-d\right)}$	Yes	[30]
Topology 7	1	4	2	3	$\frac{2}{{\left(1-d\right)}^2}$	$\frac{1}{{\left(1-d\right)}^2}$	No	[35]
Topology 8	1	5	3	3	$\frac{2}{{\left(1-d\right)}^2}$	$\frac{2}{{\left(1-d\right)}^2}$	Yes	[43]
Topology 9	1	5	2	4	$\frac{{\left(2-d\right)}^2}{{\left(1-d\right)}^2}$	$\frac{\left(2-d\right)}{{\left(1-d\right)}^2}$	Yes	[37]
Proposed	1	6	2	5	$\frac{2\left(2-d\right)}{{\left(1-d\right)}^2}$	$\frac{\left(2-d\right)}{{\left(1-d\right)}^2}$	Yes

represents the summary of the recently reported high gain boost topology, tabulating from where it specifies a few important characteristic parts of each proposed topology (i.e., components count normalized switch’s voltage stress, etc.). From the specification table, it can be observed that the performance of the high gain boost converter depends on so many factors of the converter specification. It can also be noted that though the desirable performance of the high gain boost is suitable based on low voltage stress and a high voltage gain capability, sometimes it may require many passive components. So, a trade-off must be given in order to select for perfect application.

In the comparison table, topology 9 proposed by Shahrukh khan et al. [37] has been reported recently, and the voltage gain of the proposed topology is denoted in Table 1. In this article, our proposed topology has already overcome the voltage gain, and the normalized voltage stress was reduced compared to their study. Figure 11 presents the ideal voltage gain vs. duty ratio of the reported literature survey from Table 1. The figure justifies the voltage gain profile of the studied circuit configuration. In the later section, the voltage gain is verified by the simulated results as well as by the experimental results.

6. Results and Discussion

This section describes the qualitative performance of the proposed high gain quadratic boost converter. The complete specification of the proposed converter is specified in the following section. A comprehensive list of the parameter’s specifications is given in

Table 2. Component specifications of the proposed converter.

Component	Specification
Input Voltage	24~48 V
Output Voltage	(400~408) V
Duty ratio	0.2~0.6
fsw	50 kHz
Capacitors	C1 = 220 μF/100 V/0.1 Ω, C2 = 100 μF/ 250 V/0.1 Ω, C3 = C4 =100 μF/250 V/0.1 Ω, C0 = 100 μF/450 V/0.1 Ω
Inductor	L1 = 300 μH, L2 = 600 μH, ESR = 0.2 Ω
Power MOSFET	SPW52N50C3, 560 V, 52 A 0.07 Ω
Diodes	CMPFCD86, (600 V, VF-1.5 V, IF-8 A) RF150TF3S(SIMPLIS) (600 V, VF-1.5 V, IF-8 A)
Microcontroller	STM32, Nucleo H743ZI2
Gate Driver IC	TLP250H
Fuse	6.3 A
Power supply	Chroma programmable DC power supply, 621OOH-600S
Input Power	158.6 W
Output Power	150 W
Load Resistance	Chroma programmable electronic load simulator model 63. 1075 Ω, I0-0.374 A

. The inductor of the proposed converter was designed in our laboratory following Equations (33) and (35). For the design of the inductor, an ‘E’ type ferrite core was used, and the turn ratios were calculated theoretically. The required air gap was added by electrical tape, and the inductance was measured at the same time. All other components, capacitor, power MOSFET, Driver IC, and STM32-MCU unit were purchased. The corresponding duty ratio for 400 V output voltage was calculated from the non-ideal voltage gain Equation (31).

6.1. Simulation Results and Potential Verification

To validate the performance of the converter, the proposed circuit was stimulated in SIMPLIS software. The circuit parameter value was selected exactly as described in Table 2. The only difference in the simulation configuration is the power diode. A different diode model (RF1501TF3S) has been chosen due to not having the same diode model number of the diode in SIMPLIS simulation software, which has the same specification as compared to the used diode model (i.e., CMPFC86) for experimental verification, The simulation was carried out with an input voltage of 48 V at a switching frequency of 50 kHz. All of the components were selected as ideal components. The load resistance was selected according to the 150-W output power. Figure 12 shows the circuit configuration from SIMPLIS software.

Simulation Results of the Proposed Boost Converter at Duty d = 0.4, Output Power 150-W

Though the actual duty cycle was considered 0.4, in the experimental section, the MOSFET was not turned off at exactly at the duty cycle of 0.4; instead, it was turned off at duty 0.402 due to the Miller effect. So, the simulation was carried out by selecting the duty cycle of 0.402 and the corresponding theoretical output voltage, referring to Equation (22) was calculated as 428 V. However, due to the presence of a diode forward voltage drop the actual voltage deviates, and as a result the real voltage gain is always lower than the ideal gain. From the datasheet of the diode’s model, the forward voltage drops (i.e., 1.5 V) of the diode were taken into consideration, and referring to Equation (31), the actual output voltage was calculated (i.e., 408 V). However, due to the presence of parasitic resistance in the passive component, the actual voltage is further reduced, which is reflected in the experimental results in the later section.

In Figure 13, the simulated waveform of the (a) input voltage (V_in), (b) duty cycle (V_gs), (c) switch voltage stress of the switch (V_DS), and (d) output voltage (V₀) are shown, respectively. The results show that the output voltage obtained by the simulation was about 408 V which is matching, according to the previously discussed value. The voltage stress of the diodes is shown in Figure 14 and Figure 15. The voltage across each of the working capacitors is shown in Figure 16, whereas the plot of the inductor currents is shown in Figure 17, respectively.

6.2. Experimental Results and Discussion

In this section, the experimental results are discussed. To validate the potential performance of the proposed converter, a prototype capable of providing 200 W output power was developed in our lab and was tested in the laboratory environment. The Hardware prototype is shown in Figure 18. The Experimental results for the 150 W output power were measured and they are thoroughly discussed in this section. The experimental waveform was obtained from the digital oscilloscope and is presented in the later section step by step.

The hardware parameters starting from passive components to the power MOSFET switch and power diodes have the same specification as in the simulation parameters and are shown in Table 2. This proposed study was tested by feeding 48 V DC input voltage and extracting 400 V DC of output voltage (i.e., range 395–405 V). The corresponding duty cycle’s value was measured and then selected to obtain the desired output from the non-ideal gain voltage formula (i.e., Equation (31)). Referring to the non-ideal voltage gain Equation (31), the calculated duty cycle was 0.4 or 40%, which refers to the exact desired output voltage. The PWM signal generated from the STMicroelectronics microcontroller unit was directly fed to the MOSFET driver circuit using the driver IC (i.e., TLP 250H) mentioned in

Table 3. Comparison table of voltage stress of simulated results and experimental results.

Components	Simulated Results	Experimental Results
Output voltage (V0)	408 V	402 V
The voltage across the switch (VDS)	205 V	201 V
Voltage stress across diode D1	76~76.5 V	75 V
Voltage stress across diode D2	126 V	123 V
Voltage stress across diode D3	203.5 V	202 V
Voltage stress across diode D4	203.5 V	201 V
Voltage stress across diode D5	76.3 V	75 V
Voltage stress across diode D6	203 V	202 V

. The electronic DC load was used for taking all the measurements.

In Figure 19, the gate pulse, input voltage, switch’s voltage stress, and output voltage are shown. A 402 V output voltage is measured at the load side experimentally and is shown in Figure 19. At duty 0.4, the actual output voltage gain is about 426 V, and, in this case, a reduction of 26 V can be seen in the experimental results, which is due to the diode’s forward voltage (i.e., due to non-ideal voltage gain, Equation (31)) as well as including some small drops associated with passive components.

Figure 20 represents the voltage stress of diodes D₁, D₂, and D3. For the above-mentioned rated power rating, the corresponding voltage stress of the diodes are 75 V, 123 V, and 202 V, respectively. In Figure 21, the voltage stress across diodes D₄, D₅, and D₆ are plotted. The measured values are V_D4 = 201 V, V_D5 = 75 V, and V_D6 = 202 V, respectively. The voltage across capacitors C₁, C₂, and C₃ are plotted in Figure 22. The corresponding measured voltages are V_C1 = 47 V, V_C2 = 200 V, and V_C3 = 125 V.

The currents through both inductor L₁ and inductor L₂ are shown in Figure 23. The first inductor carries an average current of about 2.15 A, and the second inductor carries an average current of about 1.3 A for 150 W out power, which is in good agreement with the characteristics equation as described in Section 2. The average output current (i.e., 0.378 A) and the input current (i.e., 3.2 A) is experimentally measured and are shown in Figure 24, respectively.

In Table 3 the comparison of the voltage stress across the power MOSFET switch and the power diodes from the simulated results and the experimental results are shown. Both the simulated and experimental results are verified by the characteristics formula for each component.

The efficiency of this proposed converter was measured experimentally by considering various loads, as is shown in Figure 25. All of the data points corresponding to each load were measured, and the duty was varied for the low input voltage to obtain the fixed output voltage (i.e., 400 V). The proposed topology was designed for 48 V input voltage and 400 V output voltage; as a result, the efficiency was reduced for lower input voltage for the same load. Peak efficiency of about 94.5% was obtained at 150-W output power for this proposed high gain quadratic-based boost DC-DC topology.

6.3. Stability Analysis

For stability analysis, the PSIM software is used to achieve the open-loop gain, and the phase plot of the system and is shown below. Figure 26 was generated using the PSIM simulation software.

The circuit configuration is exactly constructed in PSIM considering the equivalent series resistance (ESR) of each component. The gain and phase plot of the system is obtained by applying small-signal perturbation with the gate signal. In Figure 27 the corresponding bode plot is shown.

Figure 27 demonstrates that the system had a positive gain margin and positive phase margin (i.e., GM 10 dB, PM 25 degree). So, the close loop control can be designed easily for this proposed circuit configuration.

7. Conclusions

In this study, a modified non-isolated high gain quadratic boost topology is proposed and studied, which can achieve high voltage gain with a lower duty ratio that enables its potential application in the renewable energy sector as well as other different applications. The obtainable voltage gain for this topology is verified by both the theoretical and experimental results (i.e., in this study Vin 48 V is stepped up to 400 V output voltage). A base 94.5% efficiency is achieved for 150-W output power from the prototype circuit. The performance of the proposed high gain quadratic boost converter is validated by the experimental prototype, which is also verified by the SIMPLIS software simulation results. The gain and phase plot of the system obtained from PSIM justify that the control can be easily implemented. Further, the efficiency can be improved by reducing the switching loss (i.e., using more efficient power MOSFET) and the loss due to the ESR of the passive component.