Three-Level Hybrid Envelope Tracking Supply Modulator with High-Bandwidth Wide-Output-Swing

Abstract

Envelope tracking is a dynamic supply modulation technique, which is mainly used to improve the efficiency of radio frequency power amplifier. For 5G NR mobile devices, this paper presents an envelope tracking supply modulator which is composed of a three-level switching converter and linear amplifier (LA) in parallel. The hysteresis control method is adopted in the supply modulator to improve the bandwidth of the switching converter and the loop response speed. At the same time, a rail-to-rail input-output class AB linear amplifier is designed to achieve a wide output swing and a super source follower is proposed to reduce the output impedance of LA. Designed with the 180 nm CMOS technology, the supply modulator operated at 5G NR 100 MHz envelope signal. The output power of the modulator reaches 1.5 W for a 6 Ω load resistor and the output swing is 4.3 V at 5.0 V supply, and the maximum efficiency reaches 85%.

1. Introduction

Due to the surge in data transmission rates of modern wireless communication systems, the fourth and fifth generation mobile communication systems adopt signal modulation methods with high spectral efficiency, resulting in signals with large peak-to-average power ratio (PAPR) [1]. The appearance of a large PAPR signal will reduce the efficiency of the radio frequency (RF) front-end power amplifier [2,3,4]. Envelope tracking (ET) technology is a dynamic power modulation technology, which can improve the efficiency of power amplifier (PA) and is widely used [5,6,7]. The signal envelope is tracked and amplified by the ET modulator and supplied to PA.

There are many ways to realize ET modulators, and the most reported is the hybrid topology composed of linear amplifier (LA) and switching regulator (SWR) [8,9,10]. The supply modulator consists of a high-efficiency SWR and a broadband LA in parallel to provide dynamic power to the RF PA, as shown in Figure 1. A lot of research has been done on hybrid ET modulators to improve the efficiency. The dual-switch regulator improves the structure of the previous single-switch plus linear amplifier, expands the bandwidth of the SWR, and thus raises the overall efficiency [11,12,13,14]. This topology requires extra inductance and therefore brings an unpredictable noise. In [15,16,17], the LA is coupled to the SWR by AC capacitance, and the high PAPR envelope signal is separated into low frequency and high frequency components by AC coupling capacitance, thus achieving better efficiency of the ET modulator. However, the efficiency is still low due to the slow response of the SWR. Multi-level ET modulators such as three-level (3L) are suitable for high voltage applications [18], by reducing the output current ripple of the switching stage to alleviate the bandwidth requirement of LA, thereby improving the overall efficiency [19,20,21,22]. The traditional control method of the 3L-ET modulator is pulse width modulation (PWM) control [23]. In this structure, the flying capacitor voltage (V_CF) needs to be stabilized at a certain value, and the PWM control requires an additional calibration loop. In [24], a hysteresis control loop was proposed to solve the problem.

Based on the above analysis, this paper presents a hysteresis-controlled 3L-ET modulator and employs a high-speed hysteresis comparator to calibrate the V_CF. At the same time, a wideband LA is designed. The structure of this paper is as follows. Section 2 presents the overall structure of the system and makes a brief analysis. Detailed circuit design of each circuit module in Section 3 and Section 4 describes the simulation results of the overall circuit and the final summary is concluded in Section 5.

2. Supply Modulator System Level Design

The three-level hybrid structure used in this paper is shown in Figure 2 and mainly composed of three parts: (1) a linear amplifier; (2) a switching regulator; and (3) a hysteresis control loop. The load resistance R_Load is equivalent to the supply node impedance of a RF PA. In general, linear amplifiers are characterized by high bandwidth and low efficiency, mainly processing the high-frequency part of the input signal and absorbing the noise current generated by the SWR. The switching regulator has the advantage of high efficiency and mainly deals with the DC and low-frequency parts of the input signal. The hysteresis control loop, as a connection between the linear stage and the switching stage, can control the on-off of the switching MOSFET.

The efficiency of the hybrid ET modulator can be expressed as

$$\eta =\frac{P_{out}}{P_{out}+P_{loss}}$$

(1)

where P_out is the average output power of the ET modulator and P_loss represents the total power loss. The control loop is mostly logic devices, the power loss is less, so the P_loss is mainly concentrated in the linear stage and the switching stage.

This section will introduce the main blocks of the circuit and analyze the system power consumption.

2.1. Wideband Linear Amplifier

As the bandwidth of the modulated signal increases, the power supply modulator needs to track a higher bandwidth envelope signal, thus requiring more high-frequency output current from LA, which limits overall system efficiency improvements. On the one hand, the bandwidth of the hybrid ET modulator is affected by LA. On the other, the bandwidth of SWR is also gradually increased to reduce the contribution of LA. However, the wideband SWR needs a wideband LA to absorb the high frequency ripple of the switching stage, which makes the LA design more difficult.

The proposed LA has a large unity-gain bandwidth and high driving capability, the overall architecture is shown in Figure 3, including rail-to-rail input stage, buffer stage and class-AB output stage.

The power loss of the LA includes static loss and dynamic loss. The dynamic power loss comes from the nMOS and pMOS of the output stage as follows:

$$P_{LA\_dy\_loss}=P_{n\_loss}+P_{p\_loss}$$

(2)

$$P_{n\_loss}=(V_{DD}-V_{out})\times \left(i_{out}-i_{sw}\right), if i_{out}>i_{sw};$$

(3)

$$P_{p\_loss}=V_{out}\times \left(i_{sw}-i_{out}\right), if i_{out}<i_{sw};$$

(4)

where V_DD is the supply voltage, V_out is the output voltage at the load, i_sw is the switch stage current, and i_out is the current flowing into the collector/drain of the RF power amplifier. P_{LA_dy_loss} is related to the amplitude probability distribution of the input envelope signal and the peak envelope voltage [25].

The quiescent power loss mainly comes from the quiescent bias current, independent of the output power. Its reduction relies on the design of low-power circuits. In order to improve the driving ability of the LA and reduce the quiescent current as much as possible, a voltage follower is used in this paper. The proposed voltage follower can effectively reduce the output impedance, the specific implementation method is discussed in next section.

2.2. High Efficiency Switching Modulator

The switching regulator employs two pairs of complementary switching transistors as shown in Figure 2. The voltage at the V_SW node is 0 to V_DD/2 or V_DD/2 to V_DD, under the ideal conditions, the voltage range across the transistor is maintained at V_DD/2. Therefore 3L-SWR can use thin gate-oxide transistors with lower parasitic and lower on-resistance. Compared with the standard two-level buck converter, this converter can reduce the inductor current ripple to 1/4 and the output voltage ripple to 1/8, thus achieving lower switching losses [26].

The power losses in the switching stage include conduction losses and switching losses. Assuming that under the same voltage, the relationship between 3L- switching loss and 2L- switching loss is expressed in [24]

$$\frac{P_{3L\_swloss}}{P_{2L\_swloss}}=\frac{4\times \frac{1}{2}{C}_{P3L}{V}_{SW3L}^2{f}_{SW3L}+C_{FP}{V}_{SW3L}^2{f}_{SW3L}}{2\times \frac{1}{2}{C}_{P2L}{V}_{SW2L}^2{f}_{SW2L}}$$

(5)

where C_P3L and C_P2L are the parasitic capacitors of the transistors in 3L-SWR and 2L-SWR, respectively. V_SW3L is the switching voltage and f_SW3L is the switching frequency of a parasitic capacitor in the 3L-SWR, V_SW2L and f_SW2L correspond to the parameters in the 2L-SWR. The flying capacitor has parasitic capacitor C_FP, as given in [25]. The relationship between C_FP and C_F is $C_{FP}=\alpha C_F, \alpha <1$, therefore the switching loss is related to the size of the capacitor C_F.

The conduction loss and ripple loss are caused by the on-resistance of pMOS and nMOS. The ratio of conduction loss and ripple loss of the 3L-SW and 2L-SW is given as

$$\frac{P_{con3L}}{P_{con2L}}=\frac{2\times R_{on3L}{I}_{L3L}^2\times \left(1+I_{r3L}\right)}{R_{on2L}{I}_{L2L}^2\times \left(1+I_{r2L}\right)}$$

(6)

where R_on3L and R_on2L are the on-resistance of the single device in 3L-SWR and 2L-SWR, respectively. I_L3L and I_L2L represent the average inductor currents for 3L-SWR and 2L-SWR, assuming they are equal. I_r is the ratio of the inductor current ripple to the average inductor current, while I_r3L is four times smaller than I_r2L at the same inductance L and the same f_SW as shown in [19]. In Equation (6), the ratio can be less than one. If the inductor current ripple is very small, P_con3L/P_con2L is only related to the on-resistance, so the 3L-buck converter using thin gate oxide transistors has an advantage over the 2L-buck converter.

Therefore, a 3L-SWR is used to ease the design difficulty of the LA for wideband applications. The detailed circuit design is analyzed in Section 3.

3. Circuit Design

3.1. Linear Amplifier

This section describes a class-AB linear amplifier with rail-to-rail input and output ranges. Figure 4 shows the detailed circuit design of LA. It is worth noting that a source follower (SF) is adopted as a buffer to reduce the output impedance and improve driving capability.

The input stage operates in parallel with pMOS and nMOS differential input pairs, enabling the input common-mode range to reach both rails of the supply voltage. To achieve this, it is necessary to ensure that the input-stage transconductance ($g_m$) remains constant over the entire common-mode range. In this structure, the constant transconductance is achieved by using tail current compensation [27]. The class AB output stage can output large current, and has a certain ability to supply power for the load while providing low output impedance.

The output stage is designed to be a common source amplifier to provide high current driving capability. The buffer stage includes two source followers to reduce the output impedance of the circuit. Figure 5a shows a conventional source follower (CSF) [28], the output impedance is approximately $1/\left(g_{m1}+g_{mb1}\right)$. However, the CSF only reduces the output impedance to a certain extent, and it is not suitable for the case if the load is small. Therefore, this paper employs a super source follower (SSF) with feedback loop, as shown in Figure 5b. In this circuit, the feedback loop composed of M_NF, M_ND, and M_PB. This loop controls the output transistors MP1 and MN1. The current I_b1 is greater than the current I_b2. Assuming that all transistors are in saturation region, then the current difference between I_b1 and I_b2 flows through the input transistor M_NF to the drive transistor M_ND.

Using the classical feedback theory to calculate the output impedance of the SSF, it can be expressed as in Equation (7). R_op is the open-loop output impedance, Aβ is the loop gain. The output impedance of SSF is given by Equation (8).

$$\frac{V_x}{I_x}=\frac{R_{op}}{1+A\beta }$$

(7)

$$R_O=\frac{1}{g_{mF}\times \left(1+g_{mD}{r}_{o2}\right)}$$

(8)

where g_mF is the transconductance of M_NF, g_mD is the transconductance of M_ND, and r_o2 is the output impedance of current source I_b2.

The output impedance of the LA is simulated, and Figure 6a shows the output impedance versus frequency for different common-mode (CM) input voltages. The frequency response of the LA is shown in Figure 6b, which shows the amplitude and phase margin of the amplifier in open-loop condition. It can be seen that the DC gain is 78 dB, with a phase margin of 45 degrees and the unit gain-bandwidth of 171 MHz. Figure 7 shows the transient simulation results, which verifies that the LA in this paper can amplify the 100 MHz envelope signal well.

3.2. Three-Level Switching Stage

The switching stage of three-level structure buck converter with two pairs of complementary power devices is shown in Figure 8. The drive capability of the logic signal transmitted by the control loop to 3L-SWR is relatively weak, and the size of the power device is usually large, so the buffer stage is needed to improve the driving capability of the control logic signal. Another function of the buffer stage is to prevent the power devices from being turned on at the same time to cause shooting-through phenomenon.

The PWM waveform output by the control loop is responsible for the turn-on or turn-off of the switching device, and the specific implementation is shown with four operation states in Figure 9. Each state has two transistors on. The four situations of the control loop output are shown in

Table 1. States of the power transistors.

State	P1N1	P2N2	VSW
case 1	High	High	GND
case 2	Low	High	VDD/2
case 3	High	Low	VDD/2
case 4	Low	Low	VDD

, where high and low represent V_DD and 0 V, respectively.

Case 1, when the control loop output sets P1N1 and P2N2 to logic high, MP1 and MP2 are turned off, MN1 and MN2 are turned on, the output node V_SW is GND. The result is that the inductor current I_SW decreases.

Case 2, when the control loop output P1N1 is logic 0 and P2N2 is logic high, turning MP1 and MN2 on, MP2 and MN1 off, the output node V_SW is V_DD/2, increasing I_SW, and the capacitor C_F is in a charging state.

Case 3, when P1N1 is logic high and P2N2 is logic low, MP2 and MN1 are turned on, and MP1 and MN2 are turned off. At the same time, the capacitor C_F is discharged, the I_SW continues to increase, and the output node V_SW is V_DD/2.

Case 4, when P1N1 and P2N2 are both logic low, MP1 and MP2 are turned on, MN1 and MN2 are turned off, the output node V_SW is V_DD, and the I_SW continuous output, ensuring that SWR provides more load current. The four states are regarded as a cycle, and the V_CF is stabilized around V_DD/2 under the action of the control loop.

As described in Section 2.2, the power loss of 3L-SWR is related to parasitic capacitor and on-resistance, and the loss can be minimized by choosing the appropriate capacitor C_F and the size of MP and MN. Generally, there are three types of capacitors: metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, and MOS capacitors. Large capacitors increase losses and take up chip area. According to the capacitor density, parasitic capacitor percentage and linearity of the capacitor, nMOS capacitors are more suitable, as discussed in [29]. In order to make the voltage variation range of the capacitors smaller, nMOS capacitor C_F is selected as 10 nF.

The buffer stage in Figure 8 consists of a chain of inverters, which gradually increase the size and slowly increase the driving capability without wasting too much power loss.

3.3. Control Loop

The logic control circuit connects the linear stage and the switching stage. Through the adjustment of the control circuit, the output current of the LA and SWR is reasonably arranged to maximize the efficiency. The control loop in this paper consists of high-speed hysteresis comparators and logic gate circuits, as shown in Figure 10. The output voltage V_{O_LA} of LA determines which path is used (0 < V_{O_LA} < V_DD/2 selects the logic path Ctrl-A, V_DD/2 < V_{O_LA} < V_DD selects the path Ctrl-B). The current detection resistor R_SEN connects the LA and the output terminal, and the voltage of R_SEN is V_sense. The simplified representation is shown in

Table 2. Operation of the control loop.

Input	Comparator State	Result
0 < VO_LA < VDD/2 (Ctrl-A) A3: high	A1: high		Case: 1
	A1: low	A2: high A2: low	Case: 2 Case: 3
VDD/2 < VO_LA < VDD (Ctrl-B) A3: low	A1: low		Case: 4
	A1: high	A2: high A2: low	Case: 2 Case: 3

(the Result column corresponds to Table 1), and the control logic analysis is as follows:

• Ctrl-A: When I_SW > I_L, I_LA absorbs excess current, the sinking LA current increases, the output of the A1 comparator is high, and the output of P1N1 and P2N2 is high, resulting in the decrease in I_SW and I_LA. Due to the decrease in I_SW, the sourcing current of I_LA increases, and the output of A1 is low. At this time, when V_CF is lower than V_DD/2, the output of A2 comparator is high, resulting in P1N1 being low and P2N2 being high, increasing I_SW. When V_CF is higher than V_DD/2, the A2 comparator output is low, resulting in P1N1 high and P2N2 low, which also increases I_SW.
• Ctrl-B: the sourcing current of I_LA increases, the output of the A1 comparator is low, and the output of P1N1 and P2N2 is low, increasing the I_SW. If I_SW is higher than the load current I_L, I_LA will absorb the excess current. Like ctrl-A, it repeats the above operation.

Summarizing the above analysis, if the sinking LA current increases, the output of the A1 is high, P1N1 and P2N2 are not in low state at the same time, the corresponding V_SW will not be V_DD. Similarly, if the sourcing LA current increases, the output of the A1 is low, P1N1 and P2N2 are not high at the same time, the V_SW will not be GND. Figure 11 is the simulation result of the control circuit, which verifies the above analysis.

The control loop employs high-speed hysteretic comparators (Figure 10). This comparator is different from ordinary comparators in that it adopts a positive feedback loop as shown in Figure 12, which is composed of transistors M1-4. M3 and M4 have the same W/L, and M1 and M2 are the same. The hysteresis width H is related to β = (W/L) _3,4/(W/L)_1,2, and H is changed by adjusting β. In this design, the hysteresis width of comparators A1, A2, and A3 are 10 mV, 20 mV, and 50 mV, respectively.

4. Simulation Results

In this paper, the envelope tracking modulator is designed with 180 nm process. Figure 13 shows the layout of the ET supply modulator. The operation conditions of the modulator are that the supply voltage is 5 V, the equivalent load of PA is 6 ohms, and an on-chip integrated capacitor of 10 nF. In addition, a 1.1 uH off-chip inductor is used for simulation.

The transient simulation results of the ET modulator are shown in Figure 14. The input signal comes from 5G NR 100 MHz envelope signal with maximum PAPR 7.5 dB (after the PAPR reduction process). Figure 14a shows the simulation waveform. From top to bottom, it shows the input envelope waveform, output waveform, and 3L-SWR switching node voltage. The total output current, SWR output current, and LA output current are shown in Figure 14b. Current transient simulation results show that the total output current is equal to the sum of the I_LA and the I_SWR. When the I_SWR is greater than the I_Load, the LA sinks the excess current. On the contrary, when the I_SWR is less than the I_Load, the LA supplies the remaining current. This ensures that most of the I_Load is provided by the SWR, further improving the overall efficiency of the system.

Figure 15 shows the curve of the overall efficiency and output power of the ET modulator with the change of load. When the load resistance is 10 ohms, the efficiency reaches the maximum close to 85%, and the output power is 0.92 W.

Table 3. Performance comparison with the prior arts.

Reference	[3]	[6]	[11]	[5]	[12]	[22]	This Work
CMOS Technology	180 nm	180 nm	250 nm	180 nm	180 nm	65 nm	180 nm
Supply (V)	3.6	4.7	5	3.6	5	2.4	5
BW	LTE-A 40 MHz	LTE 10 MHz	5G NR 40 MHz	LTE 10 MHz	10 MHz	LTE 80 MHz	5G NR 100 MHz
PAPR (dB)	NA	7.5	12	7.24	6.95	7.84	7.5
Output voltage (V)	0.3–3.3	1.1–3	0.5–4	1.1–3.4	0.5–4.5	NA	0.3–4.6
Output power (W)	2.5	0.7 *	0.3 *	0.4 *	NA	1	1.5
Peak efficiency (%)	91	81.5	79.1	83	80	91	85

* ET PA output power.

summarizes the performance of the envelope amplifier designed in this work and compares it with some previous work. The bandwidth of the envelope signal in this paper is 100 MHz; under this condition, the modulator has higher efficiency and output power. The output voltage range of the modulator is 0.3 V–4.6 V. The higher output voltage can provide a large power supply voltage to PA, which is suitable for a broad application. Thanks to the hysteretic comparator, the flying capacitor does not require an additional calibration circuit, which reduces the difficulty of circuit design.

5. Conclusions

A hybrid envelope tracking supply modulator consisting of a class-AB linear amplifier, a three-level switching regulator, and a high-speed hysteresis control loop was presented in this paper. The proposed super source follower enables the linear amplifier to have a low output impedance at a very high frequency. Meanwhile, the hysteresis control method improves the loop response speed and the bandwidth of the switching regulator. The simulation results show that the modulator can track the 100 MHz envelope signal well with 85% peak efficiency. In addition, the modulator has a maximum output power of 1.5 W at the supply voltage of 5 V.