A Maximum Efficiency-86% Hybrid Power Modulator for 5G New Radio(NR) Applications

Abstract

A hybrid power modulator is presented for the radio frequency (RF) power amplifiers of 5th generation mobile communication technology (5G) new radio (NR) applications. A hybrid power modulator utilizing a two-level switching converter and a broadband and high-efficiency linear amplifier is presented. A further improvement in the efficiency of the circuit is achieved by using an optimized supply voltage of the two-level switching converters of 4.5 V. In this way, the overall efficiency is improved by more than 5% compared to using a 5 V supply voltage. The linear amplifier consists of four stages. In order to improve bandwidth and circuit stability, a compensation circuit is added to the linear amplifier that eliminates the poles of the main amplifier by introducing additional zeros, indirectly pushing the pole distribution out of the bandwidth. Using this approach, the linear amplifier achieves a 3-dB bandwidth of 180 MHz and an efficiency of 51%. The hybrid power modulator achieves a maximum output power of 2.4 W and an efficiency of 86% when tracking a 100 MHz 5G-NR signal under a 4 Ω load in a 180 nm CMOS package.

1. Introduction

In communication systems, the power amplifier is the most critical component but also the most energy-consuming component. Therefore, the performance of the designed power amplifier directly affects the performance of the entire system [1,2,3,4]. Up to now, envelope tracking technology (ET) [4,5,6,7] has been the main technology used to improve the efficiency of power amplifiers. The basic architecture of ET technology is shown in Figure 1. The baseband signal is up-converted after delay correction as the input signal of the power amplifier. The baseband signal of the other channel is used as the input signal of the power modulator after envelope detection and envelope processing. The power supply modulator is the key to ET technology, and its output voltage should track the input signal of the envelope well. The power supply modulator has high conversion efficiency to improve the efficiency of the entire power amplifier system. In order to enhance the efficiency and bandwidth of power supply modulators, various methods have been proposed. Power supply modulators come in three main forms, switching converters [8,9,10], linear amplifiers [11,12,13,14,15], and hybrid power modulators [16,17,18,19,20,21,22]. When switching converters process relatively wide information, the frequency of the switching transistor of the switching converter is required to be 5–6 times that of the processing envelope signals. This increases losses and reduces efficiency. Wide band-gap device technology has been proposed to improve the efficiency of switching converters [23,24,25]. Multi-phase structure and multi-level structure have also been achieved [26,27]. For linear amplifiers, it is easy to introduce losses and decrease the efficiency with the increase of peak-to-average ratio. The hybrid power supply modulator mainly includes switching converters, linear amplifiers, and controllers. This structure makes switching converters process information to improve efficiency, while the linear amplifiers process information to improve linearity. In order to improve efficiency, the controller is a tradeoff between efficiency and bandwidth. The hybrid power supply modulator has more advantages than other structures. The characteristics of linear amplifiers in hybrid power supply modulators are wide band, small output impedance, high gain, and large swing [28,29,30]. The common control methods are PWM control [31] and hysteretic control [32]. Switching converter structures are multi-phase [31,33] or multi-level [34]. Controlling multilevel switching converters is a challenge. More levels need more complicated circuits to be designed [35]. In [16], the bandwidth of a dual-mode hybrid power supply modulator, which consists of a hybrid power modulator and an average power tracking, is limited to 40 MHz. In [31], a hybrid power modulator composed of a class-AB linear amplifier and a two-phase switching converter is proposed, but it only tracks 4 MHz rectified sine waves. In [36], an ac-coupling of the outputs of the linear amplifier is proposed to improve the efficiency of a hybrid power supply modulator; however, the output method requires a large coupling capacitance, resulting in increased area. In [37], tracking and controlling the current of a linear amplifier optimizes the current distribution which results in limiting bandwidth. It can be seen from the studies cited above, although different structures have been tried in attempts to implement power supply modulators, it is challenging to design a highly efficient and wide bandwidth hybrid power supply modulator.

In communication systems based on envelope tracking technology, a mismatch between the envelope and the phase reduces Error Vector Magnitude (EVM). Thus, it is also important to increase the bandwidth of a hybrid power modulator. In this paper, an efficiency-86% hybrid power modulator for 5G New Radio (NR) is proposed. A current-mirror amplifier with current reuse is introduced, which is followed by a class-AB buffer. Compared to other linear amplifiers, this method achieves a wide bandwidth and high efficiency by introducing extra zeros. It optimizes the voltage value to improve its efficiency without multi-phase or multi-level switching converters. In the second section, the technology and methods of realizing hybrid power supply modulators are discussed. In the third, the results are analyzed. In the final section, the conclusions are reported.

2. Technology and Methods

The hybrid power supply modulator is mainly divided into three parts, a switching converter, a linear amplifier, and a hysteresis comparator, as shown in Figure 2. The linear amplifier realizes the linear amplification of the envelope signal, and mainly consists of operational amplifiers and push-pull circuits. The linear amplifier mainly provides voltage and a small current to the power modulator, as shown in Figure 3. The output stage adopts a class-AB structure. The class-AB structure has three advantages: first, the power transistor in the structure is in a micro-conduction state, and the power consumption is small in this state; second, the output of the first stage amplifier can track the input signal better; and, third, the bias mode of the class-AB type allows the transistor to have a larger current output capability [38].

The switching converter is directly controlled by the hysteresis comparator. When the envelope signal is in the low-frequency band, the switching converter is turned on and off to provide current to the power supply modulator. The linear amplifier mainly deals with high-frequency signals. In Figure 2, module A is the linear amplifier, module B is the hysteresis comparator, and module C is the switching converter. $i_{out}=i_{sw}+i_{linear}$, where $i_{linear}$ is the output current of the linear amplifier, $i_{sw}$ is the current of switching converter, and$i_{out}$ is the current of the whole circuit, as shown in Figure 3.

When the input signal (vip) frequency is low, the slew rate of the switching converter SR_isw is much higher than the slew rate of SR_iload [39], and the switching converter can track the input signal. The linear amplifier cancels the ripple from the switching converter. When the input signal (vip) is high frequency, the slew rate of the switching converter SR_isw is lower than the slew rate of SR_iload; when this happens, the switching converter cannot track the input signal, and the linear amplifiers provide a high slew rate of SR_ilinear to track the high-frequency signal assisting the switching converter.

2.1. The Structure of the Linear Amplifier

In the process of designing a hybrid power modulator, the output resistance of the linear amplifier should be very low to drive the following circuits. Its high voltage gain ensures tracking accuracy. The wide bandwidth of the linear amplifier is required for quick response. The unit gain bandwidth requires a large loss current while increasing the linear stage bandwidth, and a large current consumption. How to meet the requirements of the linear amplifier is also a key point.

The current-mirror amplifier with current reuse is based on a current mirror operational trans-conductance amplifier (OTA) as shown in Figure 4. An additional control circuit is added to increase the output current, as shown in Figure 5. In static conditions, the static currents of M3 and M4 are shunted by adding two transistors M12 and M13, which reduces the output current and indirectly increases the output impedance. The magnitudes of the current flowing through M12 and M13 are controlled by the detection input differential voltage of M10, M11, M14, and M15. The output impedance, gain, and slew rate of a current-mirror amplifier with current reuse are better than those for a current-mirror OTA under the same working conditions. Therefore, this structure of a current-mirror amplifier with current reuse is more suitable for the design of linear amplifiers.

The stability of a linear amplifier depends primarily on the distribution of poles and zeros. The phase margin (PM) is referred to as a unique parameter for a closed-loop system. A good phase margin can make the system more stable. How to ensure that the linear amplifier has suitable stability is also a key issue in the study of power supply modulator chips. One approach to accomplishing this is to introduce a compensation circuit to move poles into the system to stabilize the whole system. Utilizing traditional Miller compensation [13], the main idea is to reduce the bandwidth in exchange for the improvement of the phase margin. In this paper, a phase enhancement method in the main amplifier is used to improve the stability of the linear amplifier [14,15].

In this paper, two zeros are introduced by using negative feedback and positive feedback resistor-capacitor links. Two zeros are used to cancel the original two poles in the main amplifier, thereby indirectly pushing the frequency of the secondary poles out of the bandwidth range as shown in Figure 6. This increases the bandwidth and phase margin. As the frequency of the zero is entirely determined by the passive component values, zero-pole cancelation can be easily achieved [15]. The second pole ($P_2$) can be eliminated by adjusting the first zero ($Z_1$) with the sum of $R_1$ and $R_2$. The second zero ($Z_2$) can then be tuned to the frequency of the third pole ($P_3$) [15].

This paper assumes that C₁ = C₂ = C [16].

$${\mathrm{Z}}_1\approx -\frac{1}{C(R_1+R_2)}$$

(1)

$$Z_2\approx -\frac{R_1+R_2}{C(R_1{R}_2)}$$

(2)

$$P_1\approx -\frac{1}{(C_L+2C)r_{o4}+2C{r}_{o3}}$$

(3)

$$P_2\approx -\frac{(C_L+2C)r_{o4}+2C{r}_{o3}}{2C_{L}C{r}_{o4}{r}_{o3}+C^2(4r_{o4}{r}_{o3})}$$

(4)

$$P_3\approx -\frac{2C_L+4C}{C_{L}C(R_1+R_2)}$$

(5)

In order to make full use of the power supply voltage and reduce power consumption, the output stage needs to provide a large current and a small quiescent current. The output stage adopts class-AB amplifier architecture after compromise M53 and M54 are used to form a floating voltage source to fix the gate voltage to make the output stage work in class-AB mode. As for the compensation of the secondary amplifier and the class-AB amplifier, since the pole of the main amplifier is offset by the introduced zero point, the main pole of the secondary amplifier becomes the main pole of the whole circuit. As the transistor of the class-AB amplifier is large, it can be used as compensatory capacitance. At the same time, because the output load resistance of the class-AB amplifier is small, and the drain resistance of the power amplifier is only about 4 ohms, the high-frequency pole will move to high frequency. Therefore, it is not necessary to compensate again. In summary, the final design of the main part of the linear amplifier is shown in Figure 7.

2.2. The Switching Converter and the Hysteresis Comparator

The hysteresis comparator plays an essential role in achieving high efficiency as shown in Figure 8. Hysteresis control has the advantages of fast response speed, no need for an additional stable compensation circuit, simple implementation, and a small area. By detecting the output current between the linear amplifier and the switching converter, the linear amplifier is indirectly controlled by the hysteresis comparator to generate additional output current to offset the amplification error current that is generated by the switching converter.

When the detection current is too small, the switching frequency will become higher, which results in a larger switching loss. When the detection current is too large, the switching frequency will become smaller, which results in more current being provided by the linear stage and worse linearity. Therefore, the circuit parameters (R_sense, L, h) need to be optimized to achieve a circuit design of high efficiency and high linearity. $R_{sense}$ is the current sensing resistor, L is a filter inductance, h is the hysteresis width, and, as shown in Equations (6)–(11), the switching converter $f_{sw}$is related to R_sense, L, h, $V_{dd},\mathrm{and}{V}_{out}$.

$$\Delta i_{SW}=-\Delta i_{linear}$$

(6)

$$\Delta i_{SW}=k_1{T}_1=\frac{V_{dd}-V_{out}}{L}{T}_1$$

(7)

$$\Delta i_{linear}=\frac{V_{sense}}{R_{sense}}$$

(8)

$$T_1=\frac{2V}{R_{sense}(V_{dd}-V_{out})}L$$

(9)

$$T_2=\frac{2h}{R_{sense}{V}_{out}}$$

(10)

$$f_{SW}=\frac{R_{sense}(V_{dd}-V_{out})}{2V_{dd}hL}$$

(11)

The hysteresis comparator includes an input stage amplifier, pre-judgment, and an output stage. The prediction gain is improved by the cross-connection of the positive feedback transistors, M40, and M41. Assuming that $i_p$ is much greater than $i_n$, M39 and M41 are turned on and M40 and M42 are turned off, as shown in Figure 9. The width-to-length ratio of M39 and M42 is $\alpha$; while the width-to-length ratio of M40 and M41 is $\beta$. The current of M41 is the mirror of the current of M39. As shown in Equation (13), wherein gm is the trans-conductance of the transistor M34, when $\alpha$ is not equal to $\beta$, the comparator functions as a hysteresis comparator. The upper corner voltage of the comparator is $V_h$, the lower corner voltage is $V_l,\mathrm{and} I_b$ is the current of M36 [20].

$$i_p=\frac{\alpha }{\beta }{i}_n$$

(12)

$$V_h=\frac{I_b}{g_m}\frac{\frac{\beta }{\alpha }-1}{\frac{\beta }{\alpha }+1},when\beta \ge \alpha$$

(13)

$$V_h=-V_1$$

(14)

The efficiency of the power supply modulator also depends on the application. For broadband applications, the hysteresis width should be minimized—although this is the opposite for narrowband applications in some cases because a small hysteresis bandwidth will cause a higher switching frequency and more losses [39]. How to improve the efficiency of power supply modulators with different input signals has become a focus of research. In order to solve this problem, some researchers have changed the controllers or the number of switching converters. In this paper, optimizing the supply voltage of the switching converters improves efficiency. Optimizing the supply voltage in steps of ΔV (V₁ − V_n) indirectly increases the switching frequency [15], as shown in Figure 10. In Figure 10, the reference voltage VDD2min is defined as the average value of 2*vip, ti (i = 1, 2,…) is the time period of i, and W_t (t = 1, 2,…) is a series of subsections of the output of the linear amplifier.

3. Results and Discussion

All circuits as shown in Figure 11 are fabricated in a 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) technology package. Circuits are simulated by Cadence software.

The simulation of the closed-loop performance of the linear amplifier is shown in Figure 12. Figure 12a shows the case of Miller compensation of the closed-loop performance. It shows a twice gain frequency of 32 MHz and a phase margin of 60°; thus, the GBW is about 64 MHz. Figure 12b shows the case for compensation of the closed-loop performance using positive feedback to introduce extra zeros. This shows a twice gain frequency of 117 MHz and a phase margin of 42°; thus, the GBW is about 234 MHz. At 100 MHz, the phase margin is about 60°. Meanwhile, the 3-dB bandwidth of the linear amplifier simulated is about 180 MHz, as shown in Figure 13. Compared to the Miller compensation approach, this method is better.

The instantaneous simulation of the hybrid power modulator is carried out, in which the input signal is a 5G-NR signal with a bandwidth of 100 MHz. The results show that the average power efficiency of the linear amplifier is 51%.

Transient simulation of the hybrid power modulator is also carried out, in which the input signal is vip, the output current is i_out, the output voltage of switching converters is V_sw, and the output current through the inductor L is i_sw, Rload = 7 Ω, as shown in Figure 14. The different VDD2 and different Rload on the output efficiency are shown in Figure 15.

A comparison of the performance of the hybrid power modulator proposed in this work and modulators reported in the literature is shown in

Table 1. Comparison of power supply modulators.

	[41]	[42]	[43]	[44]	[39]	This Work
Year	2013	2015	2017	2018	2020	2022
Technology (μm)	0.18	0.18	0.18	0.18	0.18	0.18
Structure	hybrid	hybrid	hybrid	hybrid	hybrid	hybrid
Supply (V)	5.5	5	3.6	2.7–4.2	3.6	5,4.5
Bandwidth (MHz)	20	20	10	20	40	100
Signal	LTE	16QAM/ LTE	LTE/QPSK	LTE	LTE-A	OFDM
Efficiency (%)	83	75.9	83	78–86	85	86
Output power (W)	0.67	0.4	>0.3	1	2.5	2.4
PAPR (dB)	6.7	7.5	7.24	NA	NA	8
Core area (mm2)	NA	1.4	1.1	0.78	0.6	NA
Chip area (mm2)	1.47	NA	NA	NA	2.25	1.44

. Hybrid power modulators consist principally of linear amplifiers, switching converters, and controllers. Optimizing the performance of each module reduces losses and improves bandwidth. To achieve this, changing the level number of the switching converter is a research trend [40]. The method by which the controller controls the switching converters by changing the way that voltage is detected [39,41,42,43,44] is also the focus of research to improve efficiency.

4. Conclusions

In this paper, the linear amplifier compensation circuit of a hybrid power modulator is improved by introducing extra zeros. Compared with an approach based on Miller compensation, this method results in an improved gain bandwidth product. A further improvement in efficiency is achieved by using an optimized supply voltage of the two-level switching converter of 4.5 V. The maximum efficiency of the hybrid power supply modulator is 86%, and the output power is 2.4 W in a 0.18-$\mathsf{\mu }$m CMOS package.