An S/C/X-Band 4-Bit Digital Step Attenuator MMIC with 0.25 μm GaN HEMT Technology

Abstract

In this paper, a 4-bit digital step attenuator using 0.25 μm GaN HEMT technology for wideband radar systems is presented. A switched-path attenuator topology with resistive T-type attenuators and double-pole double-throw (DPDT) switches was used to achieve both low insertion loss and phase/amplitude error. The measured insertion loss of the reference state is 2.8–8.3 dB at DC-12 GHz. The input and output return loss are less than 12 dB at DC-12 GHz. An attenuation coverage of 30 dB with a least significant bit of 2 dB was achieved at DC-12 GHz. A root mean square (RMS) amplitude error of 1 dB and a phase error of 8.5° were achieved, respectively. The attenuator chip size is 2.45 mm × 1.75 mm including pads. To the best of the authors’ knowledge, this is the first demonstration of a GaN-based digital step attenuator.

1. Introduction

Recently, GaN has been receiving attention for its use in wideband and high-power radar applications. GaN-on-SiC HEMT technology is especially popular in radar applications due to its high breakdown voltage and good thermal properties. Despite considerable progress in GaN process technology, it is still challenging to implement microwave control circuits such as phase shifters, true time delay, and digital step attenuators [1]. The attenuator is one of the key components of wideband phased-array radar systems [2,3,4,5]. The low insertion loss and the amplitude and phase errors are the important performance specifications in designing a wideband attenuator. When the attenuator has high insertion loss, an additional gain compensation amplifier is necessary, which results in increasing the DC power consumption and the size of the system. When it has high phase and amplitude errors depending on the attenuation states, additional phase and amplitude correction circuits should be included in the circuit. Figure 1 shows some popular digital step attenuator topologies. The switch-embedded T-type or π-type resistive attenuators can be implemented with a small chip area and have low insertion loss, since the switch transistors are embedded with the resistive attenuation networks shown in Figure 1a [4,5]. However, these topologies generally have high phase error and a limited operating bandwidth due to the variation of the parasitic elements in the switch transistors, depending on on- and off-states. Therefore, small transistors should be used to reduce the capacitance variation of the switch transistors, which results in attenuators with high attenuation coverage not being realizable without degrading bandwidth and phase error. In addition, because the size of the switch transistors is limited in GaN technology, designing the attenuator is difficult. The switched path attenuator in Figure 1b provides lower phase errors with a wide operating frequency bandwidth [6]. Because single-pole double-throw (SPDT) switches can be implemented in the resistive attenuation networks separately, an attenuator with low phase error and wide operating bandwidth can be achieved. However, when multiple bits are implemented in the switched path attenuator, it shows relatively high insertion loss, because the accumulated losses of the SPDT switches are high. A large chip area is necessary in general since the number of the SPDT switches is twice the number of control bits.

In this paper, an S/C/X 4-bit wideband passive digital step attenuator MMIC using 0.25 μm GaN HEMT technology is presented for its low insertion loss and RMS phase and amplitude errors from DC to 12 GHz.

2. Design of the GaN HEMT SPDT Switch

The proposed 4-bit digital step attenuator topology is shown in Figure 2. The attenuator consists of SPDT switches at the input and the output ports, three double-pole double-throw (DPDT) interstage switches, and T-type resistive attenuation networks. The digital step attenuator is implemented with only passive devices. Therefore, the digital step attenuator can operate in both the transmitter and the receiver with nearly zero DC power consumption.

Because the switch transistors are generally large in GaN technology, the large parasitic capacitances reduce the operating frequency bandwidth. Even though large switch transistors are used, the parasitic elements of the switch transistors can be nearly identical in each attenuation state due to the switched path topology. This results small phase variations being provided even at high attenuation states. Wideband operating bandwidth can be achieved in this topology. For the 4-bit digital step attenuator, the RF signal passes only five series transistors, and so the insertion loss and the chip size can be reduced considerably. There are two resistive attenuation networks of the T-type and π-type, as shown in Figure 3. In this design, a T-type resistive attenuator is used to reduce the ground effect, in which the single shunt resistor can be directly connected to the substrate ground though the substrate via a hole with minimal inductance. The resistance values of the T-type attenuators can be calculated with Equations (1)–(3). The series resistance (R_SR) and parallel resistance (R_SH) values of the T-type resistive networks for each attenuation state are summarized in

Table 1. Component values of T-type resistive attenuators.

Attenuation (dB)	RSR (Ω)	RSH (Ω)
2	5	215
4	11	104
8	21	47
16	36	16

.

$${\mathrm{R}}_{\mathrm{SR}}={\mathrm{Z}}_0\left(\frac{\mathrm{K}-1}{\mathrm{K}+1}\right)$$

(1)

$${\mathrm{R}}_{\mathrm{SH}}={\mathrm{Z}}_0\left(\frac{2\mathrm{K}}{{\mathrm{K}}^2-1}\right)$$

(2)

$$\mathrm{K}=\frac{{\mathrm{V}}_{\mathrm{I}}}{{\mathrm{V}}_{\mathrm{O}}}={10}^{\mathrm{dB}/20}$$

(3)

As shown in Figure 4a, the series transistors (T1, T2) are used in the SPDT switch for switching the attenuation states, and the shunt transistors (T3, T4) are used to improve switch isolation. Only four cross-connected series transistors (T1–T4) are used in the DPDT switch in Figure 4b. The shunt transistors for the isolation are not included in the DPDT switch in order to reduce parasitic shunt capacitances, since small-size switch transistors are not available in commercial GaN HEMT technology and a moderate isolation characteristic can be achieved with only series switches at less than 12 GHz. The series inductors of L₁ and L₂ are implemented to enhance the input- and output-matching performance. A simulated insertion loss of less than 1.3 dB is achieved and the isolation is greater than 15 dB at 12 GHz. Since only two interconnecting metal layers are available in the GaN HEMT process, the top, thick metal layer is used in the inductors and the microstrip transmission lines for a high Q-factor, and the bottom, thin metal layer is used for the digital control lines. A 2.5D electromagnetic simulation was performed carefully to design the matching inductors and interconnection microstrip transmission lines.

3. Measurement Results

The 4-bit wideband digital step attenuator MMIC was fabricated with 0.25 μm GaN HEMT technology on a GaN-on-SiC substrate. A microphotograph of the 4-bit GaN digital step attenuator MMIC is shown in Figure 5. The chip size is 2.45 × 1.75 mm² including DC and RF pads. The DC and the digital control pads of the GaN digital step attenuator MMIC are bonded on the PCB, which includes the serial-to-parallel interface with a negative gate control voltage generator for the digital control voltages of −3.3 V(off-state) and 0 V(on-state). On-wafer measurement was performed to characterize the GaN digital step attenuator MMIC using a vector network analyzer and short-open-load-through (SOLT) calibration.

Figure 6 shows the measured insertion loss and normalized attenuation performance of the GaN digital step attenuator MMIC. The insertion loss of 2.8−8.3 dB is achieved in the reference state at DC-12 GHz. The attenuation range of 30 dB and the attenuation step of 2 dB are achieved with flat attenuation performance versus the frequencies. As shown in Figure 7, the input and output return losses of >12 dB are achieved from DC to 12 GHz. Figure 8 shows the measured RMS amplitude and phase errors. The measured RMS amplitude error is less than 1 dB and the RMS phase error is less than 8.5° at DC-12 GHz. The total DC power consumption is nearly 0 mW. A performance comparison of the previously published III-V digital step attenuator MMICs is summarized in

Table 2. Performance comparison of the relevant digital control step attenuators.

Reference	[7]	[8]	[9]	This Work
Frequency (GHz)	1–15	7.5–9.1	11–13.5	DC-12
Technology	GaAs 0.18 μm	GaAs 0.25 μm	GaAs 0.25 μm	GaN 0.25 μm
Number of Bits	6	6	5	4
Attenuation Range (dB)	31.5	31.5	15.5	30
Attenuation Step (dB)	0.5	0.5	0.5	2
Insertion Loss of Ref. (dB)	3.0–6.1	6.5–6.9	<6.5	2.8–8.3
Return Loss of Ref. (dB)	>12	-	>15	>12
RMS Amplitude Error (dB)	<0.25	<0.3	<0.4	<1
RMS Phase Error (Deg.)	<5	-	<2.5	<8.5
Chip size (mm2)	3.12	5.8	9.0	4.3

.

4. Conclusions

A DC-12 GHz 4-bit digital step attenuator MMIC using 0.25 μm GaN HEMT technology was presented. The proposed attenuator was implemented using DPDT switched-path topology and shows low insertion loss, RMS phase, and amplitude errors. The maximum attenuation range was 30 dB with an attenuation step of 2 dB. The measured insertion loss of the reference state was 2.8−8.3 dB at DC-12 GHz. The RMS phase and amplitude errors were less than 8.5° and less than 1 dB, respectively. The DC power consumption was nearly zero. The compact chip size was 2.45 mm × 1.75 mm including pads. The proposed GaN digital step attenuator MMIC can be expected to be applied to high-power and wideband phased array radar systems covering the S/C/X-band.