Interferences of Electromagnetic Pulses on Microcontroller Units

Abstract

In this study, electromagnetic interference testing of microcontroller units (MCUs) under different electromagnetic pulse (EMP) amplitudes, full width at half maximum (FWHM), and at different angles was carried out on an EMP cell. The coupling path of the radiation-type EMP experiment on the circuit board is random. However, in several experiments with two pins specific to a certain integrated circuit, by measuring the interference voltage of MCU pins, the statistical results indicate that as the pressure of the air gap switch of the power source increased, both the breakdown voltage and the electric field in the transverse electromagnetic (TEM) cell increased, resulting in higher electromagnetic interference (EMI) received by these two pins. As the capacitance of the storage capacitor increased, the EMI also increased. In addition, the results showed that the interference of EMP on the MCU had strong directionality; i.e., path selectivity, which was related to the structure of the MCU. X-ray imaging of the destroyed MCU showed that when the internal wiring direction of the pin is consistent with the propagation direction of the interference pulse, the EMI was minimal or even unnoticeable.

1. Introduction

In the realm of modern semiconductor devices, one notable form of damage resulting from external electrical stresses is that caused by electromagnetic pulses (EMP). Due to the difficulties in establishing an EMP failure model and understanding the failure mechanism, the EMP effect on electronic systems is typically described and evaluated using failure thresholds, which are then used to reinforce the devices or electronic systems accordingly [1,2,3]. Typically, EMP experiments are classified into two types [4,5,6,7,8]: radiative EMP experiments and direct injection EMP experiments. Since the coupling path on the circuit board in the radiation EMP test is random, it is difficult to ensure that all coupling paths are related to the component being tested. Thus, it is challenging to model circuit failures in the radiation EMP test [9]. In view of this problem, the International Electrotechnical Commission (IEC) has formulated a set of test standards to improve the feasibility and credibility of component-level tests [10,11,12]. On the module level, although the test has the same limitations, it still has a certain value because of its authenticity [13,14]. In the direct injection experiment, it is possible to know all the electrical circuits and design the coupling paths of the component. Hence, it is easy to model circuit failures, and the failure threshold of the component can be easily obtained [15,16,17,18]. Therefore, the failure threshold of the test component is often obtained through the direct injection EMP experiment, and the radiation EMP experiment is used to simulate the real environment. By evaluating the sensitivity of a specific pin or port under strong electromagnetic interference (EMI), the sensitivity of a component-level microcontroller unit (MCU) to different electromagnetic environments can be measured, thereby obtaining the electromagnetic environment for the normal operation of the module [19,20,21,22,23,24,25]. In this study, an EMP simulator was used to measure the interference voltages at MCU pins under different voltages and full width at half maximum (FWHM) conditions in a radiation EMP test.

2. Experimental Environment

2.1. MCU

MCU is a sophisticated semiconductor IC that includes a processor unit, memory modules, communication interfaces, and peripherals. It achieves chip-level computing by consolidating the memory, counter, USB, A/D conversion, UART, PLC, DMA, and LCD drive circuits onto a single chip while reducing the frequency and specifications of the central processing unit (CPU). This versatile device can be utilized in various control applications. In this study, we conducted EMI tests to assess the performance of a specific chip against EMPs. The MCU considered in this study was an enhanced 1T 8051 Flash MCU, which has a max 48 MHz peripheral operation, a 24 MHz core operation, an operating voltage range of 2.1–5.5 V, and a general-purpose input/output (GPIO) of up to 46. It contains two-way analog comparators, two-way operational amplifiers, and provides six-channel complementary pulse-width modulation (PWM) pulse output with dead zone control. Moreover, it supports up to 23 channels of 12-bit ADC, 4 UARTs, 1 SPI, and 1 I2C. It is built to industrial standards, works at temperatures from −40 °C to 105 °C, and provides LQFP32, LQFP44, and LQFP48 packages. The IC package of the MCU in this study was 44 pins.

According to IEC 62132-1, the input and output pins of analog signals were configured as 10 kΩ resistance grounding, the input pins of digital signals were configured as direct grounding, and the output pins of digital signals were configured as 14 pF capacitor grounding. According to the recommendations of IEC-61967-1, IEC-61967-2, IEC-62132-1, and IEC-62132-2 regarding the standard test plate and the size of the TEM cell, the circuit used in this study was 104 mm × 104 mm (Figure 1).

2.2. EMP Simulator

The EMP simulator was a compact EMP simulator, which was composed of a power source and a flat plate radiator (Figure 2). The radiator consisted of three components; namely, the front transition section, the rear transition section, and the workspace. Figure 3 and Figure 4 present an image of the radiator and its dimensions. The TEM wave propagated in the workspace, so the workspace was also referred to as the TEM cell. The output voltage indices of the simulator were as follows: the rise time was 7.6 ns, the half-pulse width changed with the capacitance of the power source, and the maximum FWHM was 1730.8 ns. The maximum amplitude of the EMP voltage was about 30 kV, and the maximum field strength generated in the TEM cell was 200 kV/m. Figure 5 (Left) shows the coordinate system of the TEM cell, and the typical time-domain waveform of the electric field measured at the origin is shown in Figure 5 (Right).

3. Experimental Protocol

The integrated circuit (IC) chip was placed in the center of the test plate (Figure 1) and transferred to the workspace of the TEM cell during the test (Figure 6). Solder was applied between the test plate and the TEM test window to ensure good initial contact. The remaining components were placed on the back of the test plate and came in surface mount packages.

(1)

An oscilloscope was used to monitor pins 34 and 44 of the MCU. When the MCU was working normally, pin 44 output a PWM pulse, and pin 34 produced a communication signal level at a regular time interval. The reason for choosing these two pins is because the system clock is used to coordinate and control various inputs and outputs of the system, and generally uses rising edge triggering, making it very sensitive to instantaneous electromagnetic interference. Pin 44 can serve as an output observation window. In addition, another port of the oscilloscope was used to monitor the output waveform of the EMP simulator.

(2)

The MCU was placed in the TEM cell while in working condition. Each time a set of data was measured, the plate was rotated 90° counterclockwise, and the measurement was repeated under the same conditions. Hence, measurements were collected at a total of four positions. Please note that when pins 1–11 were parallel with the x-axis of the TEM cell, the angle was defined as 0°.

(3)

During the test, different storage capacitors were used to change the FWHM of the pulse, and the breakdown voltage was adjusted by changing the pressure of the air gap switch at the power source (i.e., the amplitude of the voltage).

(4)

Starting from the smallest storage capacitance, the initial air pressure was 1 atm, and the electrode distance was 2 mm, which remained constant. Each group of tests was repeated three times, and then the air pressure was increased by 1 atm until the pressure reached 4 atm. Then, the test plate was rotated, and the above tests were repeated. After all tests at four positions were completed, the storage capacitor was replaced. A total of three storage capacitors were used in this study.

The oscilloscope had a bandwidth of 500 MHz, and Figure 6 shows the test setup. The connection method of the test piece is shown in the upper-right corner of the figure. In the experiment, it is obvious that the EMC and oscilloscope cable also have a coupling effect. However, this coupling effect can be ignored relative to the MCU, mainly because the shielding structure design of the oscilloscope cable (including input impedance matching and coaxial structure) can effectively eliminate this coupling. In addition, the non-negligible length of cable can effectively attenuate the electromagnetic pulse conducted by coupling.

4. Results and Analysis

4.1. Results

(1)

Storage capacitance (FWHM/rising edge)–pressure (field strength)–angle tests

Table 1. Interference data when the capacitance was 15,000 pF.

Storage Capacitor (pF)	Angle (°)	Pressure (atm)	FWHM (ns)	Voltage (kV)	Electric Field Intensity (kV/m)	Pin 34 Vp (V)	Pin 44 Vp (V)
15,000	0	1	524.53	13.2	88	1.9	7.76
		2	503.87	16.07	107.11	2.3	8.08
		3	489.6	18.47	123.11	3.06	8.28
		4	478.8	20.73	138.22	3.51	8.43
	90	1	513.07	14.6	97.33	2.37	7.81
		2	510.67	15.47	103.11	2	7.8
		3	500.53	17.13	114.22	2.21	7.88
		4	483.6	20.4	136	3.04	8.24
	180	1	545.87	12.67	84.44	1.7	7.49
		2	518.93	14.93	99.56	2.22	7.6
		3	493.73	18.33	122.22	2.78	7.8
		4	482.93	20.4	136	3.15	7.94
	270	1	566.27	11.73	78.22	1.89	7.44
		2	498.67	18.13	120.89	3.49	7.69
		3	493.47	18.4	122.67	3.53	7.73
		4	477.73	20.47	136.44	4.03	7.99

,

Table 2. Interference data when the capacitance was 5793 pF.

Storage Capacitor (pF)	Angle (°)	Pressure (atm)	FWHM (ns)	Voltage (kV)	Electric Field Intensity (kV/m)	Pin 34 Vp (V)	Pin 44 Vp (V)
5793	0	1	236.13	10.8	72	1.42	7.29
		2	228.4	13.67	91.11	1.29	7.31
		3	213.33	16.87	112.45	1.96	7.39
		4	198.27	21.13	140.89	3.14	7.87
	90	1	230.4	12.33	82.22	1.37	7.47
		2	227.87	13.2	88	0.91	7.37
		3	223.87	15	100	1.28	7.44
		4	195.87	21.27	141.78	2.73	8.05
	180	1	235.73	11.13	74.22	1.62	7.57
		2	223.6	14.07	93.78	1.85	7.76
		3	215.33	16.8	112	1.85	7.76
		4	201.47	20.13	134.22	3.06	8.25
	270	1	227.07	11.8	78.67	2	7.45
		2	211.6	15.53	103.56	3.03	7.75
		3	214.27	17	113.33	2.96	7.63
		4	195.33	21.6	144	4.41	8.2

and

Table 3. Interference data when the capacitance was 1910 pF.

Storage Capacitor (pF)	Angle (°)	Pressure (atm)	FWHM (ns)	Voltage (kV)	Electric Field Intensity (kV/m)	Pin 34 Vp (V)	Pin 44 Vp (V)
1910	0	1	90.4	10.27	68.44	1.14	7.44
		2	84.8	15.13	100.89	1.7	7.61
		3	84	16.2	108	1.69	7.68
		4	81.33	20.6	137.33	2.37	8.33
	90	1	86.2	12.35	82.33	2.26	7.52
		2	87.73	14.07	93.78	1.49	7.51
		3	82.53	16.73	111.56	2.02	7.76
		4	81.07	19.93	132.89	2.56	7.93
	180	1	87.87	11.87	79.11	2.04	7.81
		2	87.07	13.27	88.44	1.59	7.47
		3	82.13	17.93	119.56	2.83	8.13
		4	78.67	21.13	140.89	2.92	8.49
	270	1	87.33	11.6	77.33	1.89	7.67
		2	84.13	14.33	95.56	1.96	8.19
		3	84.93	16.27	108.45	1.86	8.24
		4	79.87	20.07	133.78	3.25	8.74

present the test data on the interference of storage capacitance (FWHM/rising edge)–pressure (field strength)–angle on pins 34 and 44. The data presented are the average result from three repeated tests.

(2)

Output waveform

Figure 7 and Figure 8 show the output pulses of pins 34 and 44 with and without interference. It can be seen from Figure 7 that when the EMP simulator was not working, the outputs of pins 34 and 44 were normal. When the EMP simulator output EMPs, as shown in Figure 8, there was a strong interference signal (red and blue pulses). Specifically, pin 34 had a decaying oscillation waveform, whereas pin 44 had a spike similar to the electric waveform. It is worth noting that at this time, pin 34 was outputting a 0-level communication clock signal, but the interference signal may affect the communication clock of the MCU. The amplitude of the interference at pin 44 was much greater than the PWM amplitude. Therefore, if interference were to occur in the PWM dead time, it could cause false conduction of switches.

4.2. Analysis

As the pressure of the air gap switch of the power source increased, the interference exhibited an increasing trend. This was true for the tests at each position, because as the pressure of the air gap switch increased, the breakdown voltage increased, and the electric field in the TEM cell also increased, thereby enhancing the interference.

With the increase of the capacitance, the rising edge of the EMP did not change much, but the FWHM of the EMP increased and the interference increased, suggesting that the EMP interference was related to the action time. The longer the action time, the greater the interference. This phenomenon was mainly due to the cumulative effect of interference on the circuit system.

The significant difference in interference levels between pin 44 and pin 33 is clearly due to the significant difference in input impedance between these two pins—such as inconsistent parasitic capacitance at the pin inlet and parasitic inductance of the internal leads of the pin—resulting in inconsistent wave impedance of the path. Therefore, there are differences in the reflection and refraction of interference electromagnetic waves, but this is entirely due to the design or manufacturing process of the integrated circuits.

Due to the randomness of the interference, to evaluate the interference on the MCU at different positions, the data in Table 1, Table 2 and Table 3 were rearranged and summarized into

Table 4. The position at which the interference on pin 34 was the highest.

Position (°)	1 atm	2 atm	3 atm	4 atm	Total
0	0	0	0	0	0
90	C1, C3	0	0	0	2
180	0	0	C3	0	1
270	C2	C1, C2, C3	C1, C2	C1, C2, C3	9

,

Table 5. The position at which the interference on pin 34 was the lowest.

Position (°)	1 atm	2 atm	3 atm	4 atm	Total
0	C3	0	C3	C3	3
90	C2	C1, C2, C3	C1, C2	C1, C2	8
180	C1	0	0	0	1
270	0	0	0	0	0

,

Table 6. The position at which the interference on pin 44 was the highest.

Position (°)	1 atm	2 atm	3 atm	4 atm	Total
0	0	C1	C1	C1	3
90	C1	0	0	0	1
180	C2, C3	C2	C2	C2	5
270	0	C3	C3	C3	3

and

Table 7. The position at which the interference on pin 44 was the lowest.

Position (°)	1 atm	2 atm	3 atm	4 atm	Total
0	C2, C3	C2	C2, C3	C2	6
90	0	0	0	C3	1
180	0	C1, C3	0	C1	3
270	C1	0	C1	0	2

. C1, C2, and C3 represent different storage capacitors. The data at different FWHMs of the EMP were compared across the same position and the same pressure (i.e., electric field amplitude). For instance, the value in row 5 and column 3 of Table 4 shows that at 2 atm and with the plate at 270°, pin 34 had the maximum interference amplitude under all three FWHMs.

From Table 4, Table 5, Table 6 and Table 7, the maximum and minimum number of interferences at a certain position were used as the evaluation indices. Pin 34 had the most and least interference when the plate was at 270° and 90°, respectively. Pin 44 had the most and least interference when the plate was at 180° and 0°, respectively.

Figure 9 shows X-ray images of the MCU, which reveals that the internal pins of pin 34 and pin 44 differ by 90 degrees. Figure 10 shows that pin 34 was near the power inlet in the TEM cell when the plate was at 90°. At this point, the interference on pin 34 was the lowest. When pin 34 was close to the load—that is, when the MCU was at 270°—the interference on pin 34 was the highest. The results suggest that EMI is path-dependent and has strong direction selectivity. The direction selectivity is reflected by the specific internal structure of the MCU. Therefore, the interference to the MCU in the test was related to its position.

For the convenience of analysis, the data were summarized to compare the interference voltages of the three groups. The results, presented in

Table 8. Comparison of interference of different storage capacitors on pin 34.

Storage Capacitance (pF)	Maximum Interference (Number of Groups)	Minimal Interference (Number of Sets)
15,000	A, B, C, D, E, F, G, H, J, L, N, O	0
5793	M, P	B, E, F, G, I, K
1910	I, K	A, C, D, H, J, L, M, N, O, P

Note: The test conditions represented by each letter are as follows: A: 0° and 1 atm; B: 0° and 2 atm; C: 0° and 3 atm; D: 0° and 4 atm; E: 90° and 1 atm; F: 90° and 2 atm; G: 90° and 3 atm; H: 90° and 4 atm; I: 180° and 1 atm; J: 180° and 2 atm; K: 180° and 3 atm; L: 180° and 4 atm; M: 270° and 1 atm; N: 270° and 2 atm; O: 270° and 3 atm; P: 270° and 4 atm.

, show that the higher the FWHM, the greater the interference to the MCU.

5. Conclusions

Through EMI testing of an MCU, this study demonstrated that as the electric field increased, the radiation interference of EMPs on the MCU increased. As the capacitance increased, the rising edge of the EMP remained unchanged, yet the FWHM of the EMP increased, indicating that the EMI was related to the action time and had a strong cumulative effect. The radiation interference of EMPs had a strong directionality—that is, path selectivity. This was related to the internal structure of the MCU. Therefore, during the design of a chip with an MCU, the directions of the pins for important signals should be made the same as the propagation direction of possible interference pulses.