1. Introduction
Strained Si materials offer the advantages of high carrier mobility, adjustable band gap, and compatibility with the traditional Si process. They are the preferred alternative in research on high-speed, high-performance, scaled MOSFETs [
1,
2]. Threshold voltage is the most critical parameter of MOSFETs, and it affects the AC/DC and subthreshold characteristics of the device. Research on the threshold voltage of strained silicon devices is significant, as it determines the devices’ on-off characteristics. Studying the threshold voltage of strained silicon devices helps to understand their operating state and features and can lead to optimized device design and improved performance and reliability. As device dimensions continue to shrink, the influence of short-channel effect becomes more significant. Strained silicon devices can mitigate or suppress short-channel effect through strain engineering techniques, and the threshold voltage is a crucial parameter in studying these effects. Accurate control of the threshold voltage and accurate threshold voltage adjustment are crucial for process optimization and device fabrication. Researching the threshold voltage of strained silicon devices can facilitate the development of improved process methods and technologies, enabling more precise and stable control of threshold voltage, thereby enhancing process controllability and stability. When designing integrated circuits using strained silicon devices, it is necessary to have an accurate threshold voltage model. By delving into the factors that influence threshold voltage, more precise models can provide essential theoretical support for integrated circuit design and for optimizing performance to meet design requirements. So, research on the threshold voltage of strained silicon devices plays a significant role in optimizing device performance, suppressing short-channel effect, optimizing processes, and supporting integrated circuit design. In current state-of-the-art chip designs, to stop short-channel effect, advanced device designs are extensively used, and strained silicon devices are among these designs. Examples include Intel’s Core processor using 32 nm process technology and TSMC’s 7 nm process, where strained silicon technology has been implemented. This research is essential for advancing the development and application of strained silicon technology. There are many studies on the threshold voltage of strained Si NMOSFETs [
3,
4,
5,
6,
7]. However, the influences of substrate bias, short-channel effect, narrow-channel effect, and drain-induced barrier lowering effect on threshold voltage have still not been fully considered, and therefore the results cannot be fully applied to the design requirements of devices and integrated circuits under realistic process conditions.
In this paper, a threshold voltage model of a long channel is built using the gradual channel approximation theory and the potential of the strain Si MOSFET longitudinal is analyzed. The influence of substrate bias on threshold voltage is fully considered in the model. However, a one-dimension method cannot meet the requirement of threshold voltage accuracy for scaled devices. To improve the threshold voltage accuracy, two-dimensional and quasi-two-dimensional analysis methods are often used [
8,
9]. When solving a two-dimensional Poisson equation in the depletion region utilizing a two-dimensional method, the physical meaning of model parameters is deficient due to some approximations made on boundary conditions. In this paper, a quasi-two-dimensional method is used to solve a two-dimensional Poisson equation. A threshold voltage model is built fully considering the short-channel effect, DIBL effect, and the narrow-channel effect. To ensure that the simulation results can better match test results, it is necessary to correct the model using process parameters [
10]. So, an integrated physical compact model for threshold voltage of a strained Si NMOSFET is built fully considering the physical effects on threshold voltage.
Through experiments, devices of different sizes were fabricated under the same process conditions, and relevant parameters were extracted using parameter extraction software. The calculation results of the model were compared with the simulation results, which further proved the correctness of the threshold voltage intensive physical model of strained Si NMOSFETs established in this paper. The results provide an important reference for the analysis and design of strained Si devices and also provide an essential theoretical basis for further integrated circuit design.
Tunneling current is a crucial parameter in strained silicon devices, as it reflects the electron tunneling through the bandgap or energy barrier in the strained silicon structure. By studying tunneling current, the performance of a device under low-voltage conditions, including conduction capability, energy efficiency, and noise characteristics, can be evaluated. As device dimensions continue to shrink, tunneling current becomes more significant in strained silicon devices. Therefore, research on tunneling current is significant for limiting device size and achieving micro- and nanoscale devices. By understanding and controlling tunneling current, design and process optimization can be conducted to reduce the increase in tunneling current caused by size effects. Tunneling current is also a key factor that affects the reliability of strained silicon devices. Understanding the sources, characteristics, and mechanisms of tunneling current helps to find methods to reduce or suppress tunneling current, thus improving device reliability and reducing the probability of failure. Research on tunneling current in strained silicon devices provides a foundation for developing new technologies and applications. Understanding the characteristics and control methods of tunneling current can provide critical guidance and support for designing novel devices and developing new strained silicon technologies. In conclusion, studying tunneling current in strained silicon devices is important for evaluating performance, limiting device size, enhancing reliability, and advancing strained silicon technology. This research has a significant impact and guiding value in optimizing device design, improving processes, and promoting the application of strained silicon technology in the field of microelectronics.
2. Theoretical Model Derivation
Biaxial strain can significantly increase electron mobility and is widely used in strained Si NMOSFETs [
11,
12].
Figure 1 shows the sectional structure of a strained Si NMOSFET. A graded
layer with a Ge composition gradient is grown on the Si substrate, which can effectively reduce surface scattering and increase electron mobility. A thick relaxed
layer is grown on the graded
layer, serving as a virtual substrate. Finally, a very thin Si layer is epitaxially grown on the relaxed
layer, introducing tensile strain in the Si layer due to different lattice constants between the Si and
layers. S, G, D, and B represent the source, gate, drain, and substrate contacts, respectively.
and
are the thicknesses of the strained Si layer and substrate depletion layer, respectively.
and
are the doping concentrations of the strained Si layer and relaxed
layer, respectively.
2.1. Long-Channel Threshold Voltage Model
Strictly speaking, modeling a MOSFET is a three-dimensional problem. However, from a practical standpoint (unless the channel width W and channel length L are tiny), it can be approximated as a two-dimensional system, which means considering only the y-direction along the channel and the x-direction perpendicular to the channel. Additionally, if the variation in the electric field Ey along the y-direction is much smaller than that in the corresponding electric field Ex along the x-direction, the device can be treated using a one-dimensional approximation method.
2.1.1. Zero Substrate Bias Threshold Voltage Model ()
The device structure shown in
Figure 1 establishes and solves a one-dimensional Poisson’s equation along the x-direction, perpendicular to the channel, when the substrate bias is zero, i.e.,
. Therefore, the threshold voltage model for strained Si NMOSFETs can be derived with long channels under zero substrate bias.
In the relaxed
layer, the strain from the
quantum well causes it to relax. In the relaxed
layer, the electron concentration can be disregarded, and the Poisson’s equation can be established as follows:
Among them,
represents the potential with substrate B as the reference point and
represents the dielectric constant of the relaxed
layer. The boundary conditions are as follows:
where
E is the electric field intensity. By integrating Equation (1), we can obtain the electric field and electric potential of the layer as follows:
Therefore, when
, the electric field and electric potential at the surface of the relaxed
layer are, respectively:
For the strained
Si layer, using the depletion approximation and ignoring the electron concentration, we can establish the one-dimensional Poisson’s equation as:
where
is the dielectric constant of the strained
Si layer. The boundary conditions are as follows:
By integrating Equation (7), we can obtain the electric field and electric potential of the strained
Si layer as follows:
The surface electric field and surface potential of the strained
Si layer at the Si/SiO
2 interface are determined by the boundary conditions as:
The depletion layer thickness in the relaxed
layer can be obtained from Equation (13) as follows:
Along the x-direction perpendicular to the channel, the applied gate voltage can be decomposed into the voltage drop across the gate oxide due to the equivalent total depletion charge, surface potential
, and flat-band voltage
[
13]:
The total depletion charge
is the sum of the depletion charges in the strained Si layer and the relaxed SiGe layer, i.e.,
:
By substituting Equations (14) and (16) into Equation (15), we can simplify and obtain:
where the values of
,
, and
can be calculated using the following formulas:
When
is equal to the threshold surface potential,
, where
is the threshold voltage at zero substrate bias. Its expression is as follows:
2.1.2. The Effect of Substrate Bias on Threshold Voltage
If a reverse bias
is applied between the substrate and the source, the surface potential
with the source as the reference point can be determined as follows:
When the substrate bias is zero,
. If the substrate bias is not zero, the threshold voltage is defined as the gate-source voltage (
) at which the surface potential
equals the threshold surface potential, as obtained from Equation (18):
Substituting Equation (18) into Equation (20) yields the following result:
where
, taking into account the non-uniformity of substrate doping and the influence of substrate voltage [
14], and introducing process fitting parameters
and
, the threshold voltage equation for a long-channel strained Si NMOSFET, in this case, is as follows:
2.2. The Influences of Short-Channel Effect and Drain-Induced Barrier Lowering Effect on Threshold Voltage
As the device dimensions ( and ) continue to decrease, the electric field along the channel direction becomes stronger. The assumption of a gradually varying channel no longer holds, and when L becomes comparable to the depletion region width at the source-drain junctions, the MOSFET is considered to be a short-channel device. In this case, the one-dimensional Poisson’s equation is no longer applicable. For the depleted region in the relaxed layer, a quasi-two-dimensional analysis method is adopted to establish the threshold voltage model for short-channel strained Si NMOSFETs.
2.2.1. Establishment and Solution of the Quasi-Two-Dimensional Equations
As shown in
Figure 2, a Gaussian box is established within the depleted region of
, with a thickness of
. The influence of the free electron concentration is neglected (depletion approximation). By integrating the four surfaces within the plane, the following equations can be obtained:
The first term on the left side of the above equation represents the electric flux entering the Gaussian box from the upper surface, and the second term represents the total electric flux entering the Gaussian box along the y-direction. The whole edge electric flux entering the Gaussian box is equal to the total ionized charge within the Gaussian box, as shown on the right side of the equation. At the bottom of the depleted region, the potential and electric field are both zero due to the connection with the substrate.
Here,
is given by
, where
is a fitting parameter related to the process and can be obtained through parameter extraction. The expression for
can be obtained by replacing
with
Equation (14) as follows:
The boundary conditions for Equation (23) are
. The solution is given by:
The equation
represents the built-in voltage, where
is the doping concentration of the source/drain region and
is the doping concentration of the relaxed
layer. In this equation,
,
represents the Boltzmann constant,
,
is the temperature, and
is the charge of an electron. In the strained Si NMOSFET with the strained Si layer, the surface potential is
at the surface of the depletion layer in the relaxed
layer. Assuming the strained Si layer is thin, we can approximately treat it as a one-dimensional structure:
where
represents the surface potential of the long-channel strained Si NMOSFET.
2.2.2. Threshold Voltage
As shown in Equation (26), the surface potential can be minimized along the y-direction. The surface potential at
is referred to as the threshold surface potential, and the corresponding gate-source voltage is the threshold voltage. By taking the derivative of Equation (26) with respect to y and finding the zero-crossing point, the surface potential at that point will be the minimum surface potential:
When
, substituting this condition into Equation (27) and rearranging, we can obtain:
where
. In the expression for
, the first term in the numerator can be attributed to the short-channel effect (SCE), which represents the influence of the change in channel length on the threshold voltage when
is constant. The second term in the numerator can be attributed to the drain-induced barrier lowering (DIBL) effect, which represents the influence of the change in
on the threshold voltage as the channel length varies; then,
. Considering the impact of the process, we introduce process parameters [
14]
,
,
,
,
, and
, which are obtained through parameter extraction. Therefore, the influences of the SCE and DIBL effect on the threshold voltage can be expressed as:
where
in Equation (29),
is substituted for
,
, and
.
2.3. The Influence of Narrow-Channel Effect on Threshold Voltage
As shown in
Figure 3, in the strained Si NMOSFET device process, there exists a conical oxide transition region between the thin gate oxide layer and the thick field oxide layer, which is referred to as a bird’s beak. When the gate voltage is applied, a gate-controlled depletion region is formed at the edge transition region of the device. The total additional depletion charge caused by the gate voltage at the device edge is
(
for each edge). If the channel width W of the device is much larger than the depletion layer width,
caused by the gate and the additional depletion charge
caused by the gate voltage can be neglected compared to the total depletion charge
. However, if W is comparable to
, the extra charge
cannot be ignored, resulting in an increase in the threshold voltage. The increment of threshold voltage is given by
, which means that as W decreases, while L remains constant,
increases. To facilitate circuit simulation, different approximations are made for the shape of the depletion region. It is found that
is inversely proportional to the device width W and directly proportional to the thickness of the gate oxide layer and the surface potential under strong inversion conditions. Further considerations are given to the substrate bias
and the specific process effects, resulting in the development of a semi-empirical
model:
and
are process-fitting parameters, which are obtained through parameter extraction.
2.4. Complete Threshold Voltage Model
Based on the analysis of threshold voltage in long channel devices, the influences of substrate bias, short-channel effect, drain-induced barrier lowering effect, and narrow-channel effect on threshold voltage were studied. Considering all the factors related to threshold voltage, the complete threshold voltage of a strained Si NMOSFET is determined as:
Among them, the expressions for
,
,
, and
are given by Equations (22) and (29)–(31), respectively. By substituting these expressions into Equation (32), we can obtain the complete expression for the threshold voltage of a strained Si NMOSFET as:
3. Tunneling Current Model
When MOSFET devices are scaled down proportionally, tunneling current significantly deteriorates the devices’ performances. To illustrate the impact of tunneling current, it is further explained through
Figure 4,
Figure 5 and
Figure 6.
Figure 4 depicts the device’s structural model, while
Figure 5 and
Figure 6 illustrate the principles of tunneling current and the composition of tunneling current, respectively.
There are three direct tunneling mechanisms in strained silicon MOSFET devices: (1) electron tunneling from the strained silicon conduction band to the gate conduction band (CBET), (2) hole tunneling from the strained silicon valence band to the gate valence band (VBET), and (3) hole tunneling from the strained silicon valence band to the gate conduction band (VBHT).
However, in a strained silicon device with a Poly-Si/SiO
2/SSi system, electrons cannot tunnel from the valence band to the conduction band, and holes also cannot tunnel. Therefore, the VBET and VBHT current components are negligible and can be ignored. The gate direct tunneling current in a strained silicon MOSFET device is mainly due to CBET and can be modeled as such [
15]:
where
represents the direct tunneling current density,
represents the barrier height,
represents the oxide layer thickness, and A and B are physical parameters with values of
and
, respectively. Here,
represents the Planck constant, and
represents the effective mass of electrons in the strained silicon conduction band. Therefore, when assuming
, the gate tunneling current at the point can be approximated as:
In the equation,
represents the gate tunneling current density at
;
, where
is an adjustment parameter with a default value of 1;
represents the gate-to-source voltage at
;
. If the gate leakage current is much smaller than the drain current, then:
In Equation (36), an approximate form is used to describe the characteristics of small-sized devices. This approximation is correct and reasonable when the value is very small or huge.
To more accurately represent tunneling current, the total gate tunneling current can be expressed in integral form as:
According to the mathematical definition of the average value, , the current intensity is equal to the product of current density and area. From Equation (37), we can obtain . For the method of integrating to solve tunneling current, its physical interpretation is that the total current intensity is the product of the gate oxide interface area and the average current density passing through the interface. Here, represents the gate tunneling current density at position .
By using Equations (35) and (36) and the integral formula
, if we let
, where
, we can obtain the total gate tunneling current as:
Combining Equation (33), we can obtain the complete tunneling current model for strained Si devices under small-size effects.
5. Conclusions
In this article, we focus on strained Si NMOSFET devices. We investigate the influences of substrate bias, short-channel effect, and drain-induced barrier lowering effect on threshold voltage, based on the gradual channel approximation and a quasi-two-dimensional Poisson equation. The influence of narrow-channel effect is also studied in detail, and a comprehensive physical model for the threshold voltage is established. The threshold voltage-related parameters are extracted through experiments. Subsequently, the influences of short-channel effect, narrow-channel effect, drain-induced barrier lowering effect, and substrate bias on threshold voltage are discussed in detail. When the drain-source voltage is biased at
, the short-channel effect and drain-induced barrier lowering effect cause a threshold voltage shift of 18.57%; a change in channel width results in a threshold voltage shift of 2.75% (as shown in
Figure 15); and when the substrate bias is set to
, the threshold voltage shifts by 27.22%. Based on the threshold voltage model in this article, we explore the tunneling current in off-state, and provide the experimental results. Future research should involve establishing corresponding models for other structures and smaller-sized devices. The developed physical models for the threshold voltage and tunneling current of strained Si NMOSFETs provide important references for the analysis and design of strained Si large-scale integrated circuits.