Systematic Analysis of Spacer and Gate Length Scaling on Memory Characteristics in 3D NAND Flash Memory

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The manuscript presents the effects of oxide/nitride pitch scaling on the performance of 3D NAND flash memory. The authors evaluate how reducing spacer length (Ls) and gate length (Lg) impacts program speed, erase speed, and Z-interference, and also study how the concave and convex channel structures effect on memory performance by TCAD simulation. However, the manuscript needs some revisions to improve it.

In Figure3, should be clearly labeled (a, b, c, d, and e) on each plot correspond to different parts of the analysis of electron-trapped charge distribution in the charge trap layer during the program operation. It’s better to mark these plots clearly.

I think a table summarizing the key simulation parameters would be clearer for readers and make it easier for readers to show the simulation results.

I understand that this study mainly relies on TCAD simulation results. In the future, experimental validation would make the findings more solid and reliable. 

In general, this study shows a plenty of simulation results to understand the scaling and structure effects on 3D NAND flash memory performance. I recommend the manuscript for publication with minor revisions.

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This paper has systematically studied the impact of oxide-nitride pitch scaling and channel curvature on 3D NAND flash memory, which offers guidelines for enhancing reliability and performance. The paper is well structured and clear to follow, covering the entire different scenarios in pitch scaling. Here are some minor questions for the authors to address.

1. Fig. 4 discusses the impact of gate edge shape on electron concentration, and concludes that the angled-corner is more favorable, therefore precisely control is required. However, from the etching process, the angled-corner is not easy to achieve and might be non-robust. And the corner shape is quite dependent on the aspect ratio too. Therefore sometime we need a trade-off. Can the authors briefly propose a practical solution for the angled-corner fabrication or any alternatives?

2. In Fig. 10d, please have a clear description of the slope shown in the plot,  and how/why the data area is chosen for this linearity calculation?

3. In part 5, the authors studied the concave and convex structures, then how about the ideally flat structure? If with a lapping process, it can be flat without such curvatures. The flat structure can be used as a reference.

4. Please have a paragraph discussing the flexibility/difficulties of applying these conclusions from TCAD simulation to the real fabricated devices.

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

The paper presents well-thought and performed investigation which presents useful results and considerations. There are some minor issues:

-          Why the subsections 3.1. and 3.2. are named Program speed and Erase speed as no such speeds are considered and studied in the paper.

-          It is recommended the symbols and the colors in figures 2 a,b to be unified.

-          Lines 159-161 : “Meanwhile, as confirmed in Figures 2a-b, it can be seen that program speed decreases even in the Ls scaling structure, although to a lesser extent compared to Lg scaling. To analyze the cause of program speed reduction…”

There is no program speed in Fig.2 but a threshold voltage.

-          there are some unclear sentences, e.g.:

Line 166-169: ”The smaller the Ls value, the greater the influence of the pass voltage applied to the adjacent WL, and the program voltage is concentrated only in the lower area of the selected WL, increasing the electric field and forming a narrow distribution of e-trapped charges.”

Lines 192-193: “This discrepancy can be interpreted as a fringing field of the read voltage applied to the selected WL according to the value of programmed Vth.”

Comments on the Quality of English Language

English needs minor revision

Author Response

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Author Response File: Author Response.pdf