Low-Power Radiation-Hardened Static Random Access Memory with Enhanced Read Stability for Space Applications

Abstract

In space environments, radiation particles affect the stored values of SRAM cells, and these effects, such as single-event upsets (SEUs) and single-event multiple-node upsets (SEMNUs), pose a threat to the reliability of systems used in the space industry. To mitigate the impacts of SEUs and SEMNUs, this paper proposes the Read Stability Improved and Low Power (RSLP16T) SRAM cell. It was confirmed that in SEU-induced simulations, all nodes of the RSLP16T could be restored with a charge amount of less than 100 fC. Additionally, it was verified that a similar level of restoration was possible for SEMNUs occurring in pair of storage nodes. The proposed cell achieves a high level of read stability due to a high pull-down cell ratio (current ratio, CR) at the storage nodes and the fact that only a pair of nodes is in contact with the bit lines during read operations. Because all node paths use a stacking structure for internal transistor configuration and a relatively higher number of cells are composed of PMOS, it consumes the least hold power. While these improvements come at the cost of slightly increased delay time and area, performance evaluation revealed that the equivalent quality metric (EQM) was the highest, indicating that the benefits outweigh the drawbacks. The proposed integrated circuit is implemented in the 90 nm CMOS process and operated on 1 V supply voltage.

1. Introduction

The human life has been simplified and security enhanced by the space industry, which provides various utilities such as satellite communications, military surveillance, guidance, and tracking systems. In the aerospace sector, satellites play a crucial role [1]. The performance of satellite communication and control relies on processors, and improving these processors necessitates the use of more high-performance cores. To support these cores, additional cache memory is required [2], and the primary memory device used for this cache memory is static random access memory (SRAM). Therefore, the performance and reliability of SRAM are vital in the aerospace industry. Space contains radiation and high-energy charged particles [3]. These particles collide with the channel of the MOSFETs that make up SRAM, forming electron–hole pairs. The generated electron–hole pairs drift towards the channel due to the reverse bias formed between the channel and the substrate (or NWell). This results in the generation of an unintended pulse. If such a pulse is applied to a memory cell over a sufficient magnitude and duration, it can flip the stored data value in the cell [3].

Semiconductor devices have become more susceptible to single-event upsets (SEUs) [1]. This is largely due to the emphasis on miniaturization in various semiconductor-based industries, including memory. Consequently, it is critical to enhance SEU resistance for reliable semiconductor designs. Current technologies can also induce single-event multiple-node upsets (SEMNUs). This phenomenon occurs due to charge-sharing, where a single charged particle simultaneously affects multiple nodes. If the affected nodes belong to the same memory cell, it results in an SEU; if they belong to different cells, it leads to an SEMNU [4,5].

Triple modular redundancy (TMR) is frequently used in memory systems to mitigate the effects of SEUs. This approach stores a single bit of data across three separate cells, ensuring data retention through majority voting even if one cell encounters an SEU. However, TMR significantly increases area and power consumption [6,7]. Similarly, error correction code (ECC) provides memory fault tolerance but requires additional circuitry and memory cells for encoders and decoders, introducing considerable area, power, and delay overhead [8,9].

In traditional 6T SRAM, data storage is managed through a latch formed by cross-coupled inverters. An SEU-induced alteration at one storage node is likely to change the value of the opposing node in the feedback loop, effectively reversing the stored bit [10]. Conventional 6T SRAM is highly vulnerable to SEU effects. To combat this, research has focused on modifying SRAM cell architectures [9,11,12,13,14,15,16]. For instance, the QUATRO-10T cell introduced in [11] uses negative feedback to help mitigate SEUs; however, it only provides immunity when storing a logic high. Nodes storing a ‘0’ remain susceptible to upset, resulting in partial immunity and suboptimal read/write performance. An improved write capacity was later offered by the WE-QUATRO cell [12], but it still lacks complete SEU protection at ‘0’-storing nodes and only minimally enhances read stability. Similarly, the QUCCE12T cell from [9] aims to minimize layout area using refined wiring but fails to adequately restore SEUs at ‘0’ nodes, offering only slight improvements in read stability. Overall, these architectures provide only partial SEU resistance. The DICE cell [13], designed for SEU tolerance, can recover from SEUs across sensitive nodes but neglects SEMNU protection where multiple nodes are simultaneously affected. The RHD12T cell proposed in [14] addresses SEMNU recovery within certain node pairs, though it still cannot withstand SEUs at ‘0’ nodes and has increased leakage power. The RSP14T cell [15] improves SEU immunity and reduces leakage yet still faces high leakage issues. The RHPD14T cell [16] attempts to diminish SEMNU susceptibility with its polar design, enhancing specific node robustness against SEUs. However, this design introduces significant leakage power and poor read stability despite enhanced write capabilities. In summary, these cell designs tend to offer only partial SEU protection with insufficient focus on SEMNU effects. They grapple with issues such as compromised read/write stability and high leakage power. Achieving stable memory operation is essential for overall system performance, particularly in space environments where power efficiency critically affects system longevity [1,10].

This paper proposes RSLP16T, which can recover its original state even after all sensitive nodes have been flipped by a significant level of SEUs. Additionally, this structure exhibits strong resilience to SEMNUs at the storage node pair (Q–QB). This paper is divided into the following sections. Section 2 explains the basic operation and provides an analysis of SEU recovery for the proposed cell. Section 3 presents simulation setups and comparative studies of RSLP16T and other soft error immune SRAM cells. Finally, Section 4 concludes the paper.

2. Proposed Architecture

2.1. RSLP16T Cell

The RSLP16T cell is shown in Figure 1, with its corresponding layout in Figure 2. This design features two storage nodes (Q and QB) and two internal nodes (S1 and S0). In the operation of this cell, when the word line (WL) is set to VDD and the write word line (WWL) is set to GND, the storage and internal nodes are accessed through their respective transistors (N7 and N8 for the bit line BL; P5 and P6 for the bit line bar, BLB). It is assumed for both the proposed and comparison cells that a state where Q = 1 (QB = 0, S1 = 1, S0 = 0) is held. This assumption is valid due to their symmetry in operations and SEU recovery behavior.

2.1.1. Hold Mode

In this mode, WL/WWL are connected to VSS and VDD, respectively, ensuring that each node is isolated from the bit lines (BL/BLB). To minimize wake-up time, the bit lines remain in a precharged state. As depicted in Figure 1, the pull-up transistors P3 and P1 for nodes Q and S1 remain on, while the pull-down transistors for nodes QB and S0 are off, thus allowing each node to reliably maintain its initial state.

2.1.2. Write Mode

To write the state Q = 0, BL/BLB are driven to VSS and VDD, respectively, with WL set to VDD and WWL to VSS. This opens connections for each node to the bit lines, pulling them to the opposite values of their stored states. Once node values surpass the threshold voltage difference necessary to flip states, the transistors managing pull-up and pull-down paths toggle, finalizing the write operation.

2.1.3. Read Mode

For reading, both word lines are set to VDD, and bit lines are precharged to VDD. Through the discharging path N4 and N6, BLB discharges while BL retains its initial precharged state, since the pull-down paths via N3 and N5 remain closed.

When the potential difference between the two bit-lines exceeds 50 mV, the read operation is performed [17]. Since the access transistors P6, P5 are in a closed state, the internal nodes S1, S0 are electrically isolated from the bit lines during the read operation.

2.2. Recovery Analysis

SEUs occur in sensitive nodes, particularly those located near the reverse-biased drain junction of an off transistor, making these nodes particularly vulnerable to transient pulses. Specifically, when an SEU happens at the drain of a PMOS transistor, it produces a positive transient pulse, indicating a transition from ‘0’ to ‘1’, while an SEU at the drain of an NMOS transistor results in a negative transient pulse, signifying a transition from ‘1’ to ‘0’. In the configuration depicted in Figure 1, the internal node S1, responsible for storing ‘1’, is exclusively surrounded by PMOS transistors. Consequently, the only SEU that can affect S1 is a transition from ‘0’ to ‘1’. Thus, given the assumed condition where Q = 1, S1 = 1, QB = 0, and S0 = 0, S1 does not qualify as a sensitive node. Instead, this section focuses on SEUs and SEMNUs affecting the sensitive nodes Q, QB, and S0.

2.2.1. SEU at Q

When an SEU flips the state of node Q from ‘1’ to ‘0’, the transistors N2 and N6 are turned off, while P7 is activated. This scenario keeps the pull-up paths P2 and P4 for the nodes QB and S0 in the off state, resulting in both nodes entering a high impedance (high-Z) state while still maintaining their initial value of ‘0’ [4]. For the S1 node, although P7 is activated, N1 remains off, allowing the S1 node to retain its original state. Consequently, the unaffected S1 node enables node Q to restore its initial state of Vdd through the action of transistor P3.

2.2.2. SEU at QB

When an SEU causes the node QB to flip from ‘0’ to ‘1’, both N5 and N1 are activated, while P8 remains in the off state. For the S0 node, even though P8 is off, the pull-up path P2 is also kept off, resulting in S0 entering a high impedance (high-Z) state, thereby preserving its initial value. Furthermore, each pull-down path for nodes Q and S1 consists of two transistors. In this scenario, transistors N3 and P7 remain off, while the pull-up transistors P3 and P1 remain activated, allowing both Q and S1 to retain their initial state of ‘1’. Consequently, QB is restored to its initial state through the actions of N6 and N4.

2.2.3. SEU at S0

When an SEU flips the state of node S0 from ‘0’ to ‘1’, transistors P1 and P3 are turned off while N3 is activated. However, because N5 remains off, the Q node stays in a high impedance (high-Z) state. For the S1 node, both P7 and N1 also remain off, resulting in S1 entering a high-Z state as well. As a result, node S0 is restored to its original state of ‘0’ by the combined actions of transistors P8 and N2.

2.2.4. SEMNU at Q-QB

When an SEMNU occurs and flips the state of the storage node pair Q and QB, QB transitions from ‘0’ to ‘1’ while Q changes from ‘1’ to ‘0’. This results in P8, N2, and N6 turning off while P7, N1, and N5 turn on. For the S0 node, both transistors P8 and P2 remain off; as a result, S0 maintains a high impedance (high-Z) state, preserving its initial value. For the S1 node, with P1, P7, and N1 all activated, both the pull-up and pull-down paths are available. However, because P1 carries a significantly stronger drain current compared to the combined effect of three N1 transistors and P7, S1 is effectively pulled up by P1, ensuring that it retains a value of ‘1’.

As a result, Q is restored to ‘1’ by P3. Subsequently, when N6 turns back on, QB is restored to ‘0’ by N6 and N4. Consequently, the proposed cell demonstrates the ability to recover from single-event upsets (SEUs) affecting Q, QB, and S0, as well as from SEMNUs impacting the Q–QB node pair. If an SEMNU occurs in the Q–S0 and QB–S0 pairs, the values stored in the cell may be flipped. However, as illustrated in Figure 2, the layout design ensures that the drain terminals of the NMOS and PMOS transistors (P8/N5 and P6/P4) are separated by a minimum distance of 1.62 µm, thereby reducing the likelihood of SEMNUs occurring in structurally unrecoverable regions like Q–S0 and QB–S0 [10,18]. Additionally, during the layout fabrication, elements and wiring were arranged symmetrically to maintain consistent symmetry.

3. Simulation Results and Analysis

Simulations utilizing 90 nm CMOS technology were conducted to evaluate the performance of the RSLP16T cell. The superiority of the RSLP16T was highlighted through comparisons with various conventional cells, such as WE-QUATRO [12], QUCCE12T [9], RHD12T [14], RSP14T [15], and RHPD14T [16]. During this process, the cell ratios of the transistors comprising the comparison cells were implemented according to the conditions presented in their respective studies.

In this research, the most significant improvement in performance is leakage power, as SRAM cells predominantly operate in the hold state without frequent recharges. Minimizing leakage power during this state significantly influences the overall power consumption of the cell [1,10]. The simulation results comparing leakage power in the hold state (HPWR) are outlined. In the hold state, leakage power arises from two primary sources: leakage through the bit lines and leakage from the internal inverter structure. The leakage through the bit lines contributes more significantly to total leakage power due to the higher carrier mobility of NMOS transistors compared to PMOS. Meanwhile, the leakage power from the internal inverter structure is reduced when there is higher resistance in the pull-up and pull-down paths of the inverter. The RHPD14T cell, which has access transistors made up of two pairs of NMOS, experiences significant leakage power due to its characteristics, resulting in the highest leakage overall. In contrast, the RSLP16T also contains two pairs of transistors but achieves the lowest leakage power. This advantage arises from the higher ratio of PMOS transistors within its internal structure, with two of the four access transistors being PMOS. Moreover, as illustrated in Figure 3, the arrangement of internal transistors in a stacking configuration [19] effectively minimizes leakage power, further contributing to the efficiency of the RSLP16T design.

3.1. Read Stability Simulation and Comparison

The ability of an SRAM cell to retain its state during reading is evaluated using the read static noise margin (RSNM). This metric can be derived from either the largest square area that fits within the butterfly curve measured at each storage node during the read operation or from the diagonal length of the curve, as shown in Figure 4 [20]. Figure 5 and Figure 6 illustrate the parameters related to stability and delay during read operations for both the proposed cell and the comparison cells.

For RHD12T and RSP14T, the use of a pair of access transistors results in a higher RSNM compared to other conventional cells. Among these, RHD12T demonstrates a greater pull-down cell ratio (CR) compared to RSP14T (3.33/3.0), indicating that RHD12T achieves a slightly elevated RSNM. Conversely, designs like QUCCE12T, WE-QUATRO, and RHPD14T utilize two pairs of access transistors, which increases the sensitivity of the nodes to noise, resulting in lower RSNM values.

The RSLP16T, while also featuring two access transistors, only utilizes a single pair during a read operation. Consequently, the storage nodes are directly connected only to the bit lines (BL and BLB), resulting in the highest CR (4.0) for the storage nodes, which maximizes the RSNM. The architectural design of the cell permits S0 (or S1) to be pulled down by PMOS transistors, thereby creating a weaker ‘0’; however, the nodes directly linked to the BL and BLB during the read operation are strong storage nodes.

3.2. Read Delay Simulation and Comparison

Read delay, often referred to as read access time (TRA), is defined as the time interval that elapses from the moment the word line voltage rises to 50% of VDD after transitioning from an initial low state. This interval continues until a voltage difference of 50 mV is established between the bit line (BL) and the bit line bar (BLB). Generally, TRA is significantly influenced by the reading current flowing through the access transistors and pull-down transistors, as well as the capacitance associated with the bit line. This relationship underscores the importance of optimizing both the electrical characteristics of the transistors and the capacitive load to achieve better read performance.

Thus, the more access transistors that are used in a read operation, the more paths connecting to the bit line exist, so the delay tends to decrease; however, on the other hand, due to parasitic components of these transistors, the delay of the read operation may also increase [10]. Examining the graph of Figure 5, most cells show that using either one or two pairs of access transistors leads to similar levels of delay, as all are utilized for reading operations. RSLP16T has two pairs of access transistors, but due to considering read stability, only one pair is used for read operations. Consequently, the remaining pair of access transistors acts as parasitic components, resulting in a longer read delay compared to other cells.

3.3. Write Delay and Stability Comparison

The stability and delay characteristics during the write operation for the cells can be observed in Figure 7 and Figure 8. Write delay or write access time (TWA) is measured from the time the word line and write word line reach 50% of VDD to the moment Q and QB are flipped [5]. Cases such as WE-QUATRO, QUCCE12T, and RHPD14T utilize both pairs of access transistors simultaneously to help flip the states of internal nodes, thus commonly yielding a shorter TWA. RSP14T and RHD12T only involve one pair of transistors in the write operation, resulting in a relatively long TWA. RSLP16T, while having the largest number of transistors internally, uses PMOS for one pair among the two pairs of access transistors for SEMNU recovery, thereby not significantly aiding in reducing write delay. Consequently, the cell structure proposed in this paper demonstrates a TWA that is slightly slower than average.

The ability of an SRAM cell to switch states during write operations is evaluated based on write capability. Typically, the write static noise margin (WSNM) is used to assess write capability; however, recent studies have claimed that the word line write trip voltage (WWTV) is a more reliable method to evaluate the write capability of SRAM cells [18,21]. To measure WWTV, the write operation is simulated, and the voltage difference between VDD and the word line at the point of the storage node inversion is determined. In the case of RSLP16T, although the internal nodes have low CR, the final write time for the entire node is long; however, the storage nodes, as stated earlier, have a large CR (4.0), leading to fast inversions and relatively high write stability.

3.4. SEU (SEMNU) Immunity Comparisons

The tolerance of an SEU can be evaluated by measuring the critical charge (Qc), and the values for each cell can be found in

Table 1. Comparisons of critical charge ($Q_C$).

Cell	Effective Qc (fC)
WE-QUATRO [12]	16.46
QUCCE12T [9]	16.76
RHD12T [14]	23.52
RSP14T [15]	24.61
RHPD14T [16]	42.58
RSLP16T	>100

. This evaluation typically employs a method that artificially induces a double exponential SEU waveform on the node using a current source and a capacitor [4,5]. For the current source, a negative pulse is applied to the OFF NMOS and a positive pulse to the OFF PMOS. The theoretical formula for this current source is represented by

$$I\left(t\right)=I_o(e^{{\displaystyle \frac{-t}{{\tau }_a}}}-e^{{\displaystyle \frac{-t}{{\tau }_{\beta }}}})$$

(1)

$$I_0=Q/({\tau }_a-{\tau }_{\beta })$$

(2)

I₀ approximates the peak current, and Q is the total applied charge. Parameters ${\tau }_a$ and ${\tau }_{\beta }$ are time constant parameters for forming the double exponential, set to 200 ps and 50 ps, respectively, for this paper [4,5]. Critical charge signifies the minimum amount of charge needed for SEU to toggle the stored value of the cell at the most sensitive node and is the total charge applied at the moment when Q and QB are inverted [21]. To evaluate this point, I₀ is gradually increased, and the corresponding total charge at the I₀ value where Q and QB toggle is compared. The simulations for SEU and SEMNU at the structurally recoverable node pair (Q–QB) of RSLP16T and its fundamental operation are presented in Figure 9. As discussed in Section 2, for the initial state Q = 1, the SEU waveforms for the nodes Q, QB, and S0 are as shown in Figure 10, confirming that they withstand significantly larger charges than other comparison cells under full SEU conditions. The simulations were carried out by sequentially applying current pulses corresponding from 20 fC to 100 fC to each node, with the previously mentioned up-pulse and down-pulse time constants set at 50 ps and 200 ps, respectively. Furthermore, it can be observed that the proposed cell can recover from an SEMNU induced at the storage node pair Q–QB, even at levels above 100 fC. Additionally, it can be observed in both Figure 9 and Figure 10 that the recovery waveforms for nodes storing ‘0’ experience a longer delay in their restoration. As previously explained, this delay occurs because the restoration of the nodes storing ‘0’ takes place after the recovery of the nodes storing ‘1’.

The area of each cell was compared through the designed layouts, considering the features presented in each paper, and the comparison results are shown in

Table 2. EQM and area comparisons.

Cell	Area (um2)	EQM
WE-QUATRO [12]	15.28	18.09
QUCCE12T [9]	14.21	23.10
RHD12T [14]	17.07	19.39
RSP14T [15]	17.93	19.05
RHPD14T [16]	17.19	26.88
RSLP16T	23.01	133.01

. The proposed cell has a larger area compared to the comparison cells, as it possesses the highest number of transistors.

3.5. Comparison with Electrical Quality Metric

Evaluating the performance of SRAM cells involves various metrics, most of which maintain trade-off relationships. Increasing CR to enhance stability or reduce delay can lead to greater leakage power and, in the worst case, compromise resistance to SEU or SEMNU. Consequently, a universal metric, known as electrical quality metric (EQM), is commonly utilized to reflect all these indicators [4,5]. A higher EQM indicates better cell performance.

$$EQM={\displaystyle \frac{Q_c\times RSNM\times WWTV}{H_{PWR}\times T_{WA}\times T_{RA}\times Area}}$$

(3)

As shown in Table 2, since the performances of these cells generally exhibit trade-off relationships, RSLP16T, possessing similar levels of EQM, shows good performance in read stability and leakage power while demonstrating some disadvantages in delay and area. However, the internal nodes maintain robust resilience against SEU effects, leading to a higher level of EQM than other cells.

4. Conclusions

A soft-error-immune read-stability-improved low-power SRAM cell, called RSLP16T, was presented in this work for the space industry. All nodes affected by SEUs demonstrate strong tolerance above 100 fC, and the design considerations for recovery mechanics from SEMNUs in the storage node pair ensure the structural integrity of the cell. The remaining cases were also considered at the layout design stage. The proposed cell exhibited the highest level of read stability and above-average write stability while maintaining the lowest amount of leakage power among all comparison cells, evidencing that it can offer the longest operational lifespan in power-constrained space applications while minimizing the potential for operational failure.